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f33b4d8c70
Updated TDF physical interface extraction to align with new TDF format
2024-02-15 19:40:22 +00:00
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bf39260e0e
Refactored TDF parsing exceptions
2024-02-13 20:48:06 +00:00
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a8a679320c
Tidying
2024-02-13 20:24:52 +00:00
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f5677b6235
Updated TDF address space, memory segment and memory segment section extraction to align with new TDF format
2024-02-13 20:24:25 +00:00
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4b6e21e43f
Typo correction
2024-02-12 19:39:21 +00:00
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8474867563
Added try... member functions to property group class
2024-02-12 19:34:59 +00:00
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a39099d5dd
Began updating TDF parsing to align with new format.
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- Convenience functions for fetching attributes from XML elements
- Property groups are now being parsed correctly
- Property group lookups (including nested lookups) are working correctly
2024-02-12 19:23:34 +00:00
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a60f5b833a
Updated property group structure to align with new TDF format
2024-02-12 19:18:16 +00:00
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09a5be91fd
Revised TDF format to accommodate targets from other families
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- Refactored all AVR8 TDFs to conform to new format
2024-02-09 00:13:22 +00:00
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647b8aa8a3
Enum value for all possible memory segment types
2023-12-19 21:54:30 +00:00
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0d1ab0205d
Used 'aliased' memory segment type for "MAPPED_PROGMEM" segments in AVR8 TDFs
2023-12-19 21:53:25 +00:00
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e3d7ea7226
Persistent memory segment type for "PROD_SIGNATURES" segments in AVR8 TDFs
2023-12-19 21:50:51 +00:00
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cc33eea712
RISC-V target ID verification upon activation
2023-12-17 18:43:16 +00:00
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66cbd89051
- Refactored AVR8 constructor, moving TDF construction to the TargetControllerComponent
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- The `TargetControllerComponent` now resolves the target via the new generated mapping approach
- Added `TargetDescriptionFile` derived class
- Removed obsolete JSON map processing code
- Other bits of refactoring and tidying
2023-12-17 18:40:52 +00:00
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4dd6050781
Renamed variant 'ordercode' to 'name'
2023-12-13 23:03:04 +00:00
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e2ed0002bd
More TDF reformatting
2023-12-13 20:40:14 +00:00
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4e373ea45d
Tidying AVR8 TDFs
2023-12-13 20:33:41 +00:00
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b5587d1e3c
Added target family attribute to AVR8 TDFs and renamed AVR family attribute to avr-family
2023-12-13 00:50:10 +00:00
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41a6e0bbbd
Tidying
2023-12-12 23:25:29 +00:00
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ec51a21846
- Began refactoring TDF build scripts
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- Separated TDF validation and mapping generation
- Moving away from the JSON mapping file, to a generated header file containing the TDF mapping.
- Other bits of tidying
2023-12-12 23:19:21 +00:00
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275885e6ec
Moved TargetFamily enum into separate header file
2023-12-12 19:02:54 +00:00
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7924478145
Tidying TDF processing in preparation for RISC-V accomodation
2023-12-10 13:04:05 +00:00
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d6c3f8044a
Tidying
2023-12-08 23:04:13 +00:00
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f4b30dbdf6
Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface
2023-12-08 23:04:04 +00:00
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eab1688b1a
Memory access commands should be LSB
2023-12-02 14:00:06 +00:00
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c792f92493
Corrected hart discovery bug
2023-12-02 13:59:18 +00:00
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c962c5e4ca
Tidying
2023-11-26 15:58:28 +00:00
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17a72bf231
Implemented RiscV::writeMemory()
2023-11-26 15:58:18 +00:00
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ddcb122137
Tidying
2023-11-25 23:19:38 +00:00
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d88b828bad
Implemented RiscV::reset()
2023-11-25 21:19:57 +00:00
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35fef9b41b
Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency
2023-11-25 19:39:34 +00:00
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9743e9a719
Use post-increment function to increment address when reading memory in RiscV::readMemory()
2023-11-25 19:36:11 +00:00
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32ea3cb960
Implemented RiscV::readMemory()
2023-11-25 19:09:53 +00:00
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eda6fe0c7f
Enable/disable debug module on activation/deactivation of RISC-V targets
2023-11-25 19:08:40 +00:00
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fa13bc2a99
Implemented RISC-V register reading/writing (only 32-bit registers are supported, for now)
2023-11-25 07:45:31 +00:00
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2fc639fb14
Tidying
2023-11-25 07:44:50 +00:00
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73b1328f9f
RISC-V general purpose register descriptors
2023-11-24 15:19:52 +00:00
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fad19ce114
Implemented RiscV::getStackPointer()
2023-11-24 15:19:07 +00:00
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3908ad6848
Switched to using underlying RegisterNumber type for RISC-V register numbers
2023-11-23 23:31:13 +00:00
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c0531a00da
Implemented RISC-V setProgramCounter()
2023-11-23 19:44:08 +00:00
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ba32e9baf9
Tidying
2023-11-23 17:53:50 +00:00
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5d552e4e7c
Implemented RiscV getProgramCounter()
2023-11-23 16:42:02 +00:00
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86d3709e46
Tidying
2023-11-23 16:35:09 +00:00
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db7d735d68
Implemented RISC-V stepping
2023-11-23 16:34:35 +00:00
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257c316369
RISC-V register access
2023-11-23 16:32:53 +00:00
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522187382a
RISC-V abstract commands
2023-11-23 15:21:46 +00:00
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776ce3c44d
Tidying
2023-11-23 13:53:12 +00:00
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c1c9a0ceeb
RISC-V hart selection
2023-11-23 12:56:26 +00:00
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c4dc3c89f5
Tidying
2023-11-22 22:44:03 +00:00
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ad1261ebc8
Implemented RiscV::getState()
2023-11-22 00:53:51 +00:00
