RISC-V general purpose register descriptors

src/Targets/RiscV/Registers/RegisterNumbers.hpp

@@ -6,6 +6,14 @@
 
 namespace Targets::RiscV::Registers
 {
+    enum class RegisterNumberBase: ::Targets::RiscV::RegisterNumber
+    {
+        CSR = 0x0000,
+        GPR = 0x1000,
+        FPR = 0x1020,
+        OTHER = 0xc000,
+    };
+
     enum class RegisterNumber: ::Targets::RiscV::RegisterNumber
     {
         DEBUG_CONTROL_STATUS_REGISTER = 0x07b0,

src/Targets/RiscV/RiscV.cpp

@@ -26,7 +26,21 @@ namespace Targets::RiscV
 
     RiscV::RiscV(const TargetConfig& targetConfig)
         : name("CH32X035C8T6") // TODO: TDF
-    {}
+        , stackPointerRegisterDescriptor(
+            RiscVRegisterDescriptor(
+                TargetRegisterType::STACK_POINTER,
+                static_cast<RegisterNumber>(Registers::RegisterNumber::STACK_POINTER_X2),
+                4,
+                TargetMemoryType::OTHER,
+                "SP",
+                "CPU",
+                "Stack Pointer Register",
+                TargetRegisterAccess(true, true)
+            )
+        )
+    {
+        this->loadRegisterDescriptors();
+    }
 
     bool RiscV::supportsDebugTool(DebugTool* debugTool) {
         return debugTool->getRiscVDebugInterface() != nullptr;
@@ -90,7 +104,7 @@ namespace Targets::RiscV
                     )
                 }
             },
-            {},
+            {this->registerDescriptorsById.begin(), this->registerDescriptorsById.end()},
             BreakpointResources(0, 0, 0),
             {},
             TargetMemoryType::FLASH
@@ -258,6 +272,26 @@ namespace Targets::RiscV
         return false;
     }
 
+    void RiscV::loadRegisterDescriptors() {
+        for (std::uint8_t i = 0; i <= 31; i++) {
+            auto generalPurposeRegisterDescriptor = RiscVRegisterDescriptor(
+                TargetRegisterType::GENERAL_PURPOSE_REGISTER,
+                static_cast<RegisterNumber>(Registers::RegisterNumberBase::GPR) + i,
+                4,
+                TargetMemoryType::OTHER,
+                "x" + std::to_string(i),
+                "CPU General Purpose",
+                std::nullopt,
+                TargetRegisterAccess(true, true)
+            );
+
+            this->registerDescriptorsById.emplace(
+                generalPurposeRegisterDescriptor.id,
+                std::move(generalPurposeRegisterDescriptor)
+            );
+        }
+    }
+
     std::set<DebugModule::HartIndex> RiscV::discoverHartIndices() {
         auto hartIndices = std::set<DebugModule::HartIndex>();
 

src/Targets/RiscV/RiscV.hpp

@@ -2,6 +2,7 @@
 
 #include <cstdint>
 #include <set>
+#include <map>
 
 #include "src/Targets/Target.hpp"
 #include "src/DebugToolDrivers/DebugTool.hpp"
@@ -18,6 +19,8 @@
 #include "src/Targets/RiscV/DebugModule/Registers/AbstractControlStatusRegister.hpp"
 #include "src/Targets/RiscV/DebugModule/Registers/AbstractCommandRegister.hpp"
 
+#include "RiscVRegisterDescriptor.hpp"
+
 namespace Targets::RiscV
 {
     class RiscV: public Target
@@ -95,12 +98,18 @@ namespace Targets::RiscV
         bool programmingModeEnabled() override;
 
     protected:
-        DebugToolDrivers::TargetInterfaces::RiscV::RiscVDebugInterface* riscVDebugInterface = nullptr;
         std::string name;
+        std::map<TargetRegisterDescriptorId, RiscVRegisterDescriptor> registerDescriptorsById;
+
+        RiscVRegisterDescriptor stackPointerRegisterDescriptor;
+
+        DebugToolDrivers::TargetInterfaces::RiscV::RiscVDebugInterface* riscVDebugInterface = nullptr;
 
         std::set<DebugModule::HartIndex> hartIndices;
         DebugModule::HartIndex selectedHartIndex = 0;
 
+        void loadRegisterDescriptors();
+
         std::set<DebugModule::HartIndex> discoverHartIndices();
 
         DebugModule::Registers::ControlRegister readDebugModuleControlRegister();

src/Targets/RiscV/RiscVRegisterDescriptor.hpp

@@ -0,0 +1,38 @@
+#pragma once
+
+#include <cstdint>
+
+#include "src/Targets/TargetRegister.hpp"
+
+#include "RiscVGeneric.hpp"
+
+namespace Targets::RiscV
+{
+    struct RiscVRegisterDescriptor: public ::Targets::TargetRegisterDescriptor
+    {
+        RegisterNumber number;
+
+        RiscVRegisterDescriptor(
+            TargetRegisterType type,
+            RegisterNumber number,
+            TargetMemorySize size,
+            TargetMemoryType memoryType,
+            std::optional<std::string> name,
+            std::optional<std::string> groupName,
+            std::optional<std::string> description,
+            TargetRegisterAccess access
+        )
+            : ::Targets::TargetRegisterDescriptor(
+                type,
+                std::nullopt,
+                size,
+                memoryType,
+                name,
+                groupName,
+                description,
+                access
+            )
+            , number(number)
+        {}
+    };
+}