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9b60bb5682
Updated memory segment access values for AVR flash segments
2024-12-24 19:38:04 +00:00
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7fe5b88dd8
Refactored Insight GUI to accommodate the many changes made to Bloom's internals
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Also lots of tidying.
2024-12-24 18:27:59 +00:00
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28e0a6d9e4
Renaming and other tidying
2024-12-21 13:51:00 +00:00
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bcdae97638
Restricted memory access member function to system address space, in RISC-V debug translator
2024-12-21 02:11:13 +00:00
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79b7457c89
GPIO pad state access and manipulation for WCH RISC-V targets
2024-12-21 02:10:31 +00:00
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db05a97215
Fixed process name change regression
2024-12-20 13:21:22 +00:00
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37bc1b9ac9
Tidying
2024-12-19 23:48:16 +00:00
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e50bd931bd
Renamed bloom process from "Bloom" to "bloom"
2024-12-19 23:48:10 +00:00
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d485263c6d
Enabled memory inspection for boot segment of WCH RISC-V targets
2024-12-19 23:47:24 +00:00
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c8f02080b6
Tidying
2024-12-18 01:19:21 +00:00
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a05b0450ab
Tidying up register access GDB monitor commands
2024-12-18 01:12:48 +00:00
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ef19ffe996
New wrb GDB monitor command, for writing to individual bit fields of target registers
2024-12-18 01:11:41 +00:00
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b7aea71327
Fixed stale program counter bug
2024-12-16 21:38:30 +00:00
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36abea6ce1
Tidying
2024-12-16 21:38:09 +00:00
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9486cc0163
Help text for target driver passthrough commands
2024-12-16 21:37:24 +00:00
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6873b2f53a
Tidying
2024-12-15 17:34:11 +00:00
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40859201e4
Target driver passthrough commands
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Added `pm` commands to manage the program mode of WCH targets
2024-12-15 17:32:58 +00:00
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1392cda74f
Adding boot/user mode switching functionality for WCH RISC-V targets
2024-12-15 02:47:39 +00:00
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4ff7c76621
New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors
2024-12-15 00:40:54 +00:00
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6dd8f0453e
Block memory writes to read-only selected program memory segments
2024-12-15 00:33:48 +00:00
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9e5d69dee4
Tidying
2024-12-14 16:17:54 +00:00
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48a7ae5dd0
Passed target state to GDB command handlers, and removed unnecessary PC read
2024-12-14 16:17:02 +00:00
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87ffc10306
Tidying
2024-12-14 02:10:02 +00:00
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2580cecb26
Handle mapped program memory segment aliasing properly, on WCH RISC-V targets
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- Added `program_segment_key` target config param, to allow the user to specify the desired program memory segment
- Added the ability to resolve the currently aliased segment, by means of probing the mapped segment
- Added program counter transformation, when the mapped segment is aliasing a foreign segment
- Other bites of tidying
2024-12-14 02:09:25 +00:00
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b5ffca6753
Acknowledge and reinitialise debug register on unexpected target reset, in RISC-V translator
2024-12-14 02:03:58 +00:00
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00919e4057
WCH-Link erase command doesn't erase the whole chip, as initially thought. It only erases the program memory segment.
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The boot segment appears to be left untouched.
2024-12-13 22:48:20 +00:00
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a971e92a58
Tidying
2024-12-08 23:33:39 +00:00
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c15eba5ca9
Seg fault bug fix
2024-12-08 23:33:14 +00:00
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3afcb65f31
Automatically exit IAP mode on WCH-Link tools
2024-12-08 23:33:07 +00:00
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1477719264
Tidying
2024-12-07 16:48:06 +00:00
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cbfbd9f4b8
Applied debug-interface-specific access restrictions for memory and registers
2024-12-07 16:43:16 +00:00
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289919f330
Tidying
2024-12-05 23:11:31 +00:00
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9f945a8d79
Fixed bug where the RISC-V target's program counter was being excluded from the response to the ReadRegisters GDB command
2024-12-05 23:10:04 +00:00
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33ed399337
WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying
2024-12-05 23:09:01 +00:00
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966244a01a
Tidying
2024-11-29 01:53:01 +00:00
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0bf470328b
Updated POWEREDBY.md
2024-11-29 01:41:07 +00:00
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ed4af3a55b
Further reduced root README
2024-11-29 01:26:12 +00:00
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1d4def228b
Tidying
2024-11-29 01:19:58 +00:00
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265e60c1b7
Fixed bug in RISC-V ISA string parsing
2024-11-29 01:13:12 +00:00
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a70b3e5878
Made architecture attribute mandatory in TDFs
2024-11-29 01:07:09 +00:00
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49cf2e5e9a
Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.
2024-11-29 01:06:44 +00:00
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cde5d83599
Replaced const reference strings with string_view, where possible, in StringService
2024-11-29 01:04:36 +00:00
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8e86cfb152
Tidying
2024-11-28 21:49:03 +00:00
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9c1b194af1
Changed all bloom.yaml config keys/values to use snake_casing
2024-11-28 21:44:04 +00:00
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a63dd1b4ef
Corrected architecture string in AVR8 TDFs
2024-11-27 20:02:43 +00:00
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d613c9909b
Tidying
2024-11-26 21:01:25 +00:00
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899cbc92c4
Made default value of reserveSteppingBreakpoint target config param vary across targets
2024-11-24 19:33:28 +00:00
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7c647caa67
Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity
2024-11-24 19:32:00 +00:00
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dc87b92fb2
Tidying
2024-11-24 00:28:41 +00:00
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71150163c4
Added abstract data register count check when identifying supported memory access strategies
2024-11-24 00:01:17 +00:00
