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275885e6ec
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Moved TargetFamily enum into separate header file
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2023-12-12 19:02:54 +00:00 |
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7924478145
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Tidying TDF processing in preparation for RISC-V accomodation
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2023-12-10 13:04:05 +00:00 |
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d6c3f8044a
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Tidying
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2023-12-08 23:04:13 +00:00 |
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f4b30dbdf6
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Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface
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2023-12-08 23:04:04 +00:00 |
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eab1688b1a
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Memory access commands should be LSB
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2023-12-02 14:00:06 +00:00 |
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c792f92493
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Corrected hart discovery bug
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2023-12-02 13:59:18 +00:00 |
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c962c5e4ca
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Tidying
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2023-11-26 15:58:28 +00:00 |
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17a72bf231
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Implemented RiscV::writeMemory()
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2023-11-26 15:58:18 +00:00 |
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ddcb122137
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Tidying
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2023-11-25 23:19:38 +00:00 |
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d88b828bad
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Implemented RiscV::reset()
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2023-11-25 21:19:57 +00:00 |
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35fef9b41b
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Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency
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2023-11-25 19:39:34 +00:00 |
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9743e9a719
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Use post-increment function to increment address when reading memory in RiscV::readMemory()
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2023-11-25 19:36:11 +00:00 |
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32ea3cb960
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Implemented RiscV::readMemory()
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2023-11-25 19:09:53 +00:00 |
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eda6fe0c7f
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Enable/disable debug module on activation/deactivation of RISC-V targets
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2023-11-25 19:08:40 +00:00 |
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fa13bc2a99
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Implemented RISC-V register reading/writing (only 32-bit registers are supported, for now)
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2023-11-25 07:45:31 +00:00 |
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2fc639fb14
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Tidying
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2023-11-25 07:44:50 +00:00 |
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73b1328f9f
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RISC-V general purpose register descriptors
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2023-11-24 15:19:52 +00:00 |
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fad19ce114
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Implemented RiscV::getStackPointer()
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2023-11-24 15:19:07 +00:00 |
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3908ad6848
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Switched to using underlying RegisterNumber type for RISC-V register numbers
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2023-11-23 23:31:13 +00:00 |
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c0531a00da
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Implemented RISC-V setProgramCounter()
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2023-11-23 19:44:08 +00:00 |
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ba32e9baf9
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Tidying
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2023-11-23 17:53:50 +00:00 |
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5d552e4e7c
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Implemented RiscV getProgramCounter()
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2023-11-23 16:42:02 +00:00 |
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86d3709e46
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Tidying
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2023-11-23 16:35:09 +00:00 |
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db7d735d68
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Implemented RISC-V stepping
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2023-11-23 16:34:35 +00:00 |
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257c316369
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RISC-V register access
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2023-11-23 16:32:53 +00:00 |
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522187382a
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RISC-V abstract commands
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2023-11-23 15:21:46 +00:00 |
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776ce3c44d
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Tidying
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2023-11-23 13:53:12 +00:00 |
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c1c9a0ceeb
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RISC-V hart selection
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2023-11-23 12:56:26 +00:00 |
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c4dc3c89f5
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Tidying
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2023-11-22 22:44:03 +00:00 |
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ad1261ebc8
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Implemented RiscV::getState()
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2023-11-22 00:53:51 +00:00 |
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fc1fd22499
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Made a start with RISC-V target implementation
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2023-11-22 00:38:40 +00:00 |
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d3c7cddb82
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Added TargetFamily to TargetDescriptor and comparability check in AVR GDB debug server
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2023-11-22 00:37:29 +00:00 |
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0d5213c84c
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RISC-V debug module register structs
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2023-11-21 22:13:17 +00:00 |
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826da3e921
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Initial pass at a RiscVDebugInterface and implementation (for WCH-Link debug tools)
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2023-11-21 21:40:40 +00:00 |
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ad2c709374
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Corrected seg fault when deactivating an AVR8 target in the absence of an AVR8 debug interface.
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2023-11-18 14:50:54 +00:00 |
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9904d93314
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Support for reserved hardware breakpoint (for stepping on AVR8 targets)
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2023-09-23 21:50:04 +01:00 |
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b38872e837
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Program memory cache
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2023-09-22 17:52:28 +01:00 |
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b5df37ae9b
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Removed TargetProgramCounter type alias
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2023-09-21 00:40:30 +01:00 |
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d7b59cac59
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Support for hardware breakpoints
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2023-09-20 23:43:29 +01:00 |
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df5a141089
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Tidying
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2023-09-20 23:29:58 +01:00 |
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ea33faf535
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Tidying
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2023-09-14 21:16:03 +01:00 |
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c80984021b
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Added 0xFFFF opcode as some AVRs treat it as an SBRS instruction.
Also some tidying
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2023-09-14 21:10:57 +01:00 |
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667b0327e8
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Tidying
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2023-09-10 18:33:23 +01:00 |
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3203635397
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Added AVR8 instruction mnemonic enum
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2023-09-10 13:59:42 +01:00 |
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20cbf14809
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AVR8 opcode decoder
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2023-09-10 01:18:53 +01:00 |
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47f9ce0415
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Tidying
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2023-09-07 23:21:36 +01:00 |
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586c11157c
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Refactored byte item selection and highlighting in hex viewer
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2023-08-24 17:25:28 +01:00 |
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579b9a1f28
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Updated TDF documentation
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2023-08-20 15:48:39 +01:00 |
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e6cafdb3cf
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Adjusted TDF mapping to use paths relative to the resources directory
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2023-08-20 15:34:44 +01:00 |
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9a6e22e6c7
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Corrected member initialisation order (addressing -Wreorder warnings)
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2023-08-19 21:53:00 +01:00 |
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