doryan/BloomPatched
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  • 4dc019e915 Moved RISC-V CSR and GPR address spaces to TDF. Some other bits of refactoring/tidying Nav 2024-12-27 03:41:31 +00:00
  • 00c4cee6c2 Added address space unit size to MemorySegment and MemorySegmentSection Some recfactoring Nav 2024-12-27 01:53:02 +00:00
  • 7aeb2ddf08 Tidying Nav 2024-12-24 20:11:47 +00:00
  • fd45bad970 Deleted debug server documentation as I don't have time to maintain it. Nav 2024-12-24 20:11:32 +00:00
  • 674b11575d Tidying Nav 2024-12-24 19:58:48 +00:00
  • c288e0e838 Reused CPU peripheral for GPRs in AVR8 driver Nav 2024-12-24 19:58:22 +00:00
  • 9b60bb5682 Updated memory segment access values for AVR flash segments Nav 2024-12-24 19:38:04 +00:00
  • 7fe5b88dd8 Refactored Insight GUI to accommodate the many changes made to Bloom's internals Also lots of tidying. Nav 2024-12-24 18:27:59 +00:00
  • 28e0a6d9e4 Renaming and other tidying Nav 2024-12-21 13:45:32 +00:00
  • bcdae97638 Restricted memory access member function to system address space, in RISC-V debug translator Nav 2024-12-21 02:11:13 +00:00
  • 79b7457c89 GPIO pad state access and manipulation for WCH RISC-V targets Nav 2024-12-21 02:10:31 +00:00
  • db05a97215 Fixed process name change regression Nav 2024-12-20 13:21:22 +00:00
  • 37bc1b9ac9 Tidying Nav 2024-12-19 23:48:16 +00:00
  • e50bd931bd Renamed bloom process from "Bloom" to "bloom" Nav 2024-12-19 23:48:10 +00:00
  • d485263c6d Enabled memory inspection for boot segment of WCH RISC-V targets Nav 2024-12-19 23:47:20 +00:00
  • c8f02080b6 Tidying Nav 2024-12-18 01:19:21 +00:00
  • a05b0450ab Tidying up register access GDB monitor commands Nav 2024-12-18 01:12:48 +00:00
  • ef19ffe996 New wrb GDB monitor command, for writing to individual bit fields of target registers Nav 2024-12-18 01:11:41 +00:00
  • b7aea71327 Fixed stale program counter bug Nav 2024-12-16 21:38:30 +00:00
  • 36abea6ce1 Tidying Nav 2024-12-16 21:38:09 +00:00
  • 9486cc0163 Help text for target driver passthrough commands Nav 2024-12-16 21:36:47 +00:00
  • 6873b2f53a Tidying Nav 2024-12-15 17:34:11 +00:00
  • 40859201e4 Target driver passthrough commands Added pm commands to manage the program mode of WCH targets Nav 2024-12-15 17:32:58 +00:00
  • 1392cda74f Adding boot/user mode switching functionality for WCH RISC-V targets Nav 2024-12-15 00:41:49 +00:00
  • 4ff7c76621 New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors Nav 2024-12-15 00:40:54 +00:00
  • 6dd8f0453e Block memory writes to read-only selected program memory segments Nav 2024-12-14 23:50:20 +00:00
  • 9e5d69dee4 Tidying Nav 2024-12-14 16:17:54 +00:00
  • 48a7ae5dd0 Passed target state to GDB command handlers, and removed unnecessary PC read Nav 2024-12-14 16:17:02 +00:00
  • 87ffc10306 Tidying Nav 2024-12-14 02:09:39 +00:00
  • 2580cecb26 Handle mapped program memory segment aliasing properly, on WCH RISC-V targets Nav 2024-12-14 02:09:25 +00:00
  • b5ffca6753 Acknowledge and reinitialise debug register on unexpected target reset, in RISC-V translator Nav 2024-12-14 02:03:58 +00:00
  • 00919e4057 WCH-Link erase command doesn't erase the whole chip, as initially thought. It only erases the program memory segment. The boot segment appears to be left untouched. Nav 2024-12-13 22:48:20 +00:00
  • a971e92a58 Tidying Nav 2024-12-08 23:33:39 +00:00
  • c15eba5ca9 Seg fault bug fix Nav 2024-12-08 23:33:14 +00:00
  • 3afcb65f31 Automatically exit IAP mode on WCH-Link tools Nav 2024-12-08 23:33:07 +00:00
  • 1477719264 Tidying Nav 2024-12-07 16:48:06 +00:00
  • cbfbd9f4b8 Applied debug-interface-specific access restrictions for memory and registers Nav 2024-12-07 16:43:16 +00:00
  • 289919f330 Tidying Nav 2024-12-05 23:11:31 +00:00
  • 9f945a8d79 Fixed bug where the RISC-V target's program counter was being excluded from the response to the ReadRegisters GDB command Nav 2024-12-05 23:10:04 +00:00
  • 33ed399337 WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying Nav 2024-12-05 23:09:01 +00:00
  • 966244a01a Tidying Nav 2024-11-29 01:50:15 +00:00
  • 0bf470328b Updated POWEREDBY.md Nav 2024-11-29 01:41:07 +00:00
  • ed4af3a55b Further reduced root README Nav 2024-11-29 01:26:12 +00:00
  • 1d4def228b Tidying Nav 2024-11-29 01:13:18 +00:00
  • 265e60c1b7 Fixed bug in RISC-V ISA string parsing Nav 2024-11-29 01:13:12 +00:00
  • a70b3e5878 Made architecture attribute mandatory in TDFs Nav 2024-11-29 01:07:09 +00:00
  • 49cf2e5e9a Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base. Nav 2024-11-29 01:06:44 +00:00
  • cde5d83599 Replaced const reference strings with string_view, where possible, in StringService Nav 2024-11-29 01:04:36 +00:00
  • 8e86cfb152 Tidying Nav 2024-11-28 21:49:03 +00:00
  • 9c1b194af1 Changed all bloom.yaml config keys/values to use snake_casing Nav 2024-11-27 20:18:00 +00:00
  • a63dd1b4ef Corrected architecture string in AVR8 TDFs Nav 2024-11-27 20:02:43 +00:00
  • d613c9909b Tidying Nav 2024-11-26 21:01:25 +00:00
  • 899cbc92c4 Made default value of reserveSteppingBreakpoint target config param vary across targets Nav 2024-11-24 19:33:28 +00:00
  • 7c647caa67 Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity Nav 2024-11-24 19:32:00 +00:00
  • dc87b92fb2 Tidying Nav 2024-11-24 00:28:41 +00:00
  • 71150163c4 Added abstract data register count check when identifying supported memory access strategies Nav 2024-11-23 23:12:38 +00:00
  • e4e2bd1796 Added WCH-LinkE to Bloom's udev rules Nav 2024-11-23 22:51:55 +00:00
  • 775649c6e8 Tidying Nav 2024-11-23 21:09:41 +00:00
  • 282086eaa2 Tidied exceptions Nav 2024-11-23 21:09:33 +00:00
  • 9aef4be2f1 Added PostAttach command in WCH-Link interface. Also some bits of tidying Nav 2024-11-23 20:41:56 +00:00
  • d8131080ec Implemented memory access via program buffer, in RISC-V debug translator Nav 2024-11-23 20:14:47 +00:00
  • e207440cd9 Renamed common header file Nav 2024-11-18 21:11:54 +00:00
  • a574fe3461 Tidying Nav 2024-11-17 18:19:11 +00:00
  • a3ed513b84 Fixed bug in EDBG driver that was resulting in program memory corruption when flashing the target with software breakpoints installed Nav 2024-11-17 18:18:44 +00:00
  • 5908b74cc1 Ignore duplicate hardware breakpoint insertions Nav 2024-11-17 18:17:27 +00:00
  • f6819d35de Tidying Nav 2024-11-17 16:15:13 +00:00
  • c14aab0fc4 Fixed dangling reference bug that was resulting in invalid mapped_io segment in EDBG session object. Nav 2024-11-17 13:13:15 +00:00
  • 3009cdd951 Tidying Nav 2024-11-16 21:50:04 +00:00
  • 4147af618b Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias) Nav 2024-11-16 21:49:49 +00:00
  • eebba986b5 RISC-V GDB server Nav 2024-11-16 20:43:22 +00:00
  • 26f4f8f90e Tidying Nav 2024-11-16 20:06:55 +00:00
  • 07283a2dc7 Flash programming support for WCH-LinkE tool Nav 2024-11-16 20:05:26 +00:00
  • 0118306e30 Refactored UsbInterface::writeBulk member function to use std::span instead of std::vector Nav 2024-11-16 19:58:07 +00:00
  • a7ee6cbae2 Refactored page alignment code in EDBG and RISC-V debug translator driver Nav 2024-11-16 19:54:40 +00:00
  • 8f61c5a839 Handled flash erase without subsequent flash write commands, in AVR GDB server Nav 2024-11-16 18:54:28 +00:00
  • de02bf318c Corrected HW breakpoint count bug in WchRiscV target Nav 2024-11-06 20:06:55 +00:00
  • 7662dec100 Tidying Nav 2024-11-06 20:05:59 +00:00
  • 285fc41c23 Corrected bug in EDBG driver memory access routines. It was incorrectly using the FUSES memory type when in debug mode (that memory type isn't available in debug mode, only program mode. Was causing a target reset). Nav 2024-11-06 19:46:27 +00:00
  • 24b41ca420 Added access property to Target Nav 2024-11-02 22:34:42 +00:00
  • f0b7f3193c Corrected string->int conversion bug in TargetPinDescriptor. The numericPosition member should really be removed. Will revisit later. Nav 2024-10-27 00:28:41 +01:00
  • 4f166cc7d7 Tidying Nav 2024-10-27 00:27:16 +01:00
  • e7b270a30c Corrected bug in GDB server config (IP address param wasn't being validated properly) Nav 2024-10-27 00:26:41 +01:00
  • 623743995b Made the EDBG CMSIS-DAP command delay optional for all debug tools, and disabled it by default. The command delay was really choking Bloom's EDBG driver, causing a very noticeable drag on Bloom's performance. It's much faster with the command delay disabled. There was a good reason for why I introduced this some time ago. Without it, some EDBG debug tools were misbehaving - I remember that for certain. But now, I cannot seem to reproduce these issues. Very odd. If the issues do reappear, I may have to enable the command delay by default, again, for some debug tools. For now, if any users experience issues, I'll just suggest they manually enable the command delay via their project config. Also, I'm not going to document this new config option, as I would prefer the user to approach me if they experience issues as a result of this, so that I'll know if it needs revisiting. Nav 2024-10-27 00:25:42 +01:00
  • 4160d4259a Corrected bug in EDBG driver, where we weren't waiting for a stopped event when we should have been Nav 2024-10-27 00:02:00 +01:00
  • e82d59d190 Tidying Nav 2024-10-26 19:27:16 +01:00
  • 08af052ba9 Corrected bug in AVR GDB memory access command handlers, which allowed GDB to perform out-of-bounds accesses Nav 2024-10-26 19:26:56 +01:00
  • cb8e5f1d24 Confirmed that GPR and IO memory segments to not come after the SRAM segment, on AVR8 targets Nav 2024-10-26 19:24:08 +01:00
  • 8cf96ba5df Tidying Nav 2024-10-26 17:19:00 +01:00
  • 1db70be31e Move AVR-specific GDB memory address translation to AvrGdbTargetDescriptor Nav 2024-10-26 17:18:42 +01:00
  • b6cbdf5a0d Changed AVR-GDB command packet class to a bare interface class Nav 2024-10-26 16:19:05 +01:00
  • 5be3ab4503 Tidying Nav 2024-10-25 23:12:31 +01:00
  • 9df41ccfc5 Made VCont step/continue command handlers generic (non-target-specific) Nav 2024-10-25 23:12:04 +01:00
  • 8be311cbc0 Refactored GDB server base class, making it a template class, allowing for much more flexibility for derived target-specific implementations Nav 2024-10-25 22:22:25 +01:00
  • 72d0c28d08 Fixed bug in assertion in RISC-V debug translator Nav 2024-10-20 00:44:09 +01:00
  • 4e28d3c488 Present register width as opposed to register byte size in new register access GDB monitor commands Nav 2024-10-20 00:23:00 +01:00
  • a65be393be Tidying Nav 2024-10-19 23:11:22 +01:00
  • 7a54632966 Implemented disabling of GDB packet acknowledgement, and disabled it by default. The new packetAcknowledgement debug server config param can be used to keep it enabled. Nav 2024-10-19 23:10:34 +01:00
  • 9b1489fbf2 Removed WchLinkVariant::UNKNOWN Nav 2024-10-19 14:22:43 +01:00
  • 00d6f5fb71 Corrected bug in RISC-V debug translator where a reset wasn't always keeping the target halted Nav 2024-10-19 14:22:12 +01:00
  • 1bb2214721 Tidying Nav 2024-10-18 00:02:00 +01:00