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ecd0f5b054
First pass at RISC-V hardware breakpoints (Trigger module)
2024-10-06 17:54:08 +01:00
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4f9bb0ac3e
Target variant keys
2024-08-19 19:43:02 +01:00
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c662e946ca
Updated application to code to accomodate changes to TDF format (new pad elements and changes to variant elements)
2024-08-16 23:02:35 +01:00
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3f88e2022c
Refactored descriptor ID generation and added IDs to peripherals, register groups and registers
2024-07-25 19:03:26 +01:00
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dd80c254a2
Added postActivate() to the target interface, for outputting any target specific info after activation.
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Removed the logging of the generic target ID from the TargetController
2024-07-23 21:36:07 +01:00
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6cdbfbe950
Massive refactor to accommodate RISC-V targets
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- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
2024-07-23 21:14:22 +01:00
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cc33eea712
RISC-V target ID verification upon activation
2023-12-17 18:43:16 +00:00
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66cbd89051
- Refactored AVR8 constructor, moving TDF construction to the TargetControllerComponent
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- The `TargetControllerComponent` now resolves the target via the new generated mapping approach
- Added `TargetDescriptionFile` derived class
- Removed obsolete JSON map processing code
- Other bits of refactoring and tidying
2023-12-17 18:40:52 +00:00
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d6c3f8044a
Tidying
2023-12-08 23:04:13 +00:00
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f4b30dbdf6
Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface
2023-12-08 23:04:04 +00:00
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eab1688b1a
Memory access commands should be LSB
2023-12-02 14:00:06 +00:00
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c792f92493
Corrected hart discovery bug
2023-12-02 13:59:18 +00:00
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c962c5e4ca
Tidying
2023-11-26 15:58:28 +00:00
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17a72bf231
Implemented RiscV::writeMemory()
2023-11-26 15:58:18 +00:00
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ddcb122137
Tidying
2023-11-25 23:19:38 +00:00
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d88b828bad
Implemented RiscV::reset()
2023-11-25 21:19:57 +00:00
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35fef9b41b
Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency
2023-11-25 19:39:34 +00:00
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9743e9a719
Use post-increment function to increment address when reading memory in RiscV::readMemory()
2023-11-25 19:36:11 +00:00
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32ea3cb960
Implemented RiscV::readMemory()
2023-11-25 19:09:53 +00:00
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eda6fe0c7f
Enable/disable debug module on activation/deactivation of RISC-V targets
2023-11-25 19:08:40 +00:00
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fa13bc2a99
Implemented RISC-V register reading/writing (only 32-bit registers are supported, for now)
2023-11-25 07:45:31 +00:00
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73b1328f9f
RISC-V general purpose register descriptors
2023-11-24 15:19:52 +00:00
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fad19ce114
Implemented RiscV::getStackPointer()
2023-11-24 15:19:07 +00:00
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3908ad6848
Switched to using underlying RegisterNumber type for RISC-V register numbers
2023-11-23 23:31:13 +00:00
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c0531a00da
Implemented RISC-V setProgramCounter()
2023-11-23 19:44:08 +00:00
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ba32e9baf9
Tidying
2023-11-23 17:53:50 +00:00
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5d552e4e7c
Implemented RiscV getProgramCounter()
2023-11-23 16:42:02 +00:00
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86d3709e46
Tidying
2023-11-23 16:35:09 +00:00
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db7d735d68
Implemented RISC-V stepping
2023-11-23 16:34:35 +00:00
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257c316369
RISC-V register access
2023-11-23 16:32:53 +00:00
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522187382a
RISC-V abstract commands
2023-11-23 15:21:46 +00:00
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776ce3c44d
Tidying
2023-11-23 13:53:12 +00:00
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c1c9a0ceeb
RISC-V hart selection
2023-11-23 12:56:26 +00:00
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ad1261ebc8
Implemented RiscV::getState()
2023-11-22 00:53:51 +00:00
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fc1fd22499
Made a start with RISC-V target implementation
2023-11-22 00:38:40 +00:00
