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ddcb122137
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Tidying
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2023-11-25 23:19:38 +00:00 |
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d88b828bad
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Implemented RiscV::reset()
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2023-11-25 21:19:57 +00:00 |
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35fef9b41b
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Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency
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2023-11-25 19:39:34 +00:00 |
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9743e9a719
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Use post-increment function to increment address when reading memory in RiscV::readMemory()
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2023-11-25 19:36:11 +00:00 |
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32ea3cb960
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Implemented RiscV::readMemory()
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2023-11-25 19:09:53 +00:00 |
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eda6fe0c7f
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Enable/disable debug module on activation/deactivation of RISC-V targets
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2023-11-25 19:08:40 +00:00 |
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fa13bc2a99
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Implemented RISC-V register reading/writing (only 32-bit registers are supported, for now)
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2023-11-25 07:45:31 +00:00 |
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73b1328f9f
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RISC-V general purpose register descriptors
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2023-11-24 15:19:52 +00:00 |
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fad19ce114
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Implemented RiscV::getStackPointer()
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2023-11-24 15:19:07 +00:00 |
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3908ad6848
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Switched to using underlying RegisterNumber type for RISC-V register numbers
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2023-11-23 23:31:13 +00:00 |
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c0531a00da
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Implemented RISC-V setProgramCounter()
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2023-11-23 19:44:08 +00:00 |
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ba32e9baf9
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Tidying
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2023-11-23 17:53:50 +00:00 |
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5d552e4e7c
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Implemented RiscV getProgramCounter()
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2023-11-23 16:42:02 +00:00 |
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86d3709e46
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Tidying
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2023-11-23 16:35:09 +00:00 |
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db7d735d68
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Implemented RISC-V stepping
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2023-11-23 16:34:35 +00:00 |
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257c316369
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RISC-V register access
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2023-11-23 16:32:53 +00:00 |
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522187382a
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RISC-V abstract commands
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2023-11-23 15:21:46 +00:00 |
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776ce3c44d
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Tidying
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2023-11-23 13:53:12 +00:00 |
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c1c9a0ceeb
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RISC-V hart selection
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2023-11-23 12:56:26 +00:00 |
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ad1261ebc8
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Implemented RiscV::getState()
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2023-11-22 00:53:51 +00:00 |
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fc1fd22499
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Made a start with RISC-V target implementation
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2023-11-22 00:38:40 +00:00 |
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