doryan/BloomPatched
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60 Commits

Author SHA1 Message Date
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cbfbd9f4b8 Applied debug-interface-specific access restrictions for memory and registers 2024-12-07 16:43:16 +00:00
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33ed399337 WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying 2024-12-05 23:09:01 +00:00
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966244a01a Tidying 2024-11-29 01:53:01 +00:00
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1d4def228b Tidying 2024-11-29 01:19:58 +00:00
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265e60c1b7 Fixed bug in RISC-V ISA string parsing 2024-11-29 01:13:12 +00:00
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49cf2e5e9a Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base. 2024-11-29 01:06:44 +00:00
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8e86cfb152 Tidying 2024-11-28 21:49:03 +00:00
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899cbc92c4 Made default value of reserveSteppingBreakpoint target config param vary across targets 2024-11-24 19:33:28 +00:00
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7c647caa67 Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity 2024-11-24 19:32:00 +00:00
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d8131080ec Implemented memory access via program buffer, in RISC-V debug translator 
- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator
 2024-11-23 20:14:47 +00:00
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4147af618b Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias) 2024-11-16 21:49:49 +00:00
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eebba986b5 RISC-V GDB server 2024-11-16 20:43:22 +00:00
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26f4f8f90e Tidying 2024-11-16 20:06:55 +00:00
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07283a2dc7 Flash programming support for WCH-LinkE tool 2024-11-16 20:05:26 +00:00
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de02bf318c Corrected HW breakpoint count bug in WchRiscV target 2024-11-06 20:06:55 +00:00
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52171734d8 New WchRiscV target class 2024-10-12 23:16:16 +01:00
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9cfc171255 Added description member to TargetPeripheralDescriptor 2024-10-08 21:26:03 +01:00
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248c51acc8 Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints. 2024-10-07 20:02:39 +01:00
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d71083c3f9 Tidying 2024-10-06 18:10:02 +01:00
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ecd0f5b054 First pass at RISC-V hardware breakpoints (Trigger module) 2024-10-06 17:54:08 +01:00
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4f9bb0ac3e Target variant keys 2024-08-19 19:43:02 +01:00
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c662e946ca Updated application to code to accomodate changes to TDF format (new pad elements and changes to variant elements) 2024-08-16 23:02:35 +01:00
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3f88e2022c Refactored descriptor ID generation and added IDs to peripherals, register groups and registers 2024-07-25 19:03:26 +01:00
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dd80c254a2 Added postActivate() to the target interface, for outputting any target specific info after activation. 
Removed the logging of the generic target ID from the TargetController
 2024-07-23 21:36:07 +01:00
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6cdbfbe950 Massive refactor to accommodate RISC-V targets 
- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
 2024-07-23 21:14:22 +01:00
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ed54b0e726 Tidying 2024-03-29 16:31:14 +00:00
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75d5124265 Moved TargetRegisterDescriptor struct to separate file 2024-03-09 17:16:29 +00:00
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cc33eea712 RISC-V target ID verification upon activation 2023-12-17 18:43:16 +00:00
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66cbd89051 - Refactored AVR8 constructor, moving TDF construction to the TargetControllerComponent 
- The `TargetControllerComponent` now resolves the target via the new generated mapping approach
- Added `TargetDescriptionFile` derived class
- Removed obsolete JSON map processing code
- Other bits of refactoring and tidying
 2023-12-17 18:40:52 +00:00
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d6c3f8044a Tidying 2023-12-08 23:04:13 +00:00
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f4b30dbdf6 Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface 2023-12-08 23:04:04 +00:00
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eab1688b1a Memory access commands should be LSB 2023-12-02 14:00:06 +00:00
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c792f92493 Corrected hart discovery bug 2023-12-02 13:59:18 +00:00
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c962c5e4ca Tidying 2023-11-26 15:58:28 +00:00
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17a72bf231 Implemented RiscV::writeMemory() 2023-11-26 15:58:18 +00:00
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ddcb122137 Tidying 2023-11-25 23:19:38 +00:00
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d88b828bad Implemented RiscV::reset() 2023-11-25 21:19:57 +00:00
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35fef9b41b Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency 2023-11-25 19:39:34 +00:00
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9743e9a719 Use post-increment function to increment address when reading memory in RiscV::readMemory() 2023-11-25 19:36:11 +00:00
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32ea3cb960 Implemented RiscV::readMemory() 2023-11-25 19:09:53 +00:00
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eda6fe0c7f Enable/disable debug module on activation/deactivation of RISC-V targets 2023-11-25 19:08:40 +00:00
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fa13bc2a99 Implemented RISC-V register reading/writing (only 32-bit registers are supported, for now) 2023-11-25 07:45:31 +00:00
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2fc639fb14 Tidying 2023-11-25 07:44:50 +00:00
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73b1328f9f RISC-V general purpose register descriptors 2023-11-24 15:19:52 +00:00
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fad19ce114 Implemented RiscV::getStackPointer() 2023-11-24 15:19:07 +00:00
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3908ad6848 Switched to using underlying RegisterNumber type for RISC-V register numbers 2023-11-23 23:31:13 +00:00
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c0531a00da Implemented RISC-V setProgramCounter() 2023-11-23 19:44:08 +00:00
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ba32e9baf9 Tidying 2023-11-23 17:53:50 +00:00
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5d552e4e7c Implemented RiscV getProgramCounter() 2023-11-23 16:42:02 +00:00
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86d3709e46 Tidying 2023-11-23 16:35:09 +00:00