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899cbc92c4
Made default value of reserveSteppingBreakpoint target config param vary across targets
2024-11-24 19:33:28 +00:00
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7c647caa67
Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity
2024-11-24 19:32:00 +00:00
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d8131080ec
Implemented memory access via program buffer, in RISC-V debug translator
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- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator
2024-11-23 20:14:47 +00:00
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f6819d35de
Tidying
2024-11-17 16:15:13 +00:00
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c14aab0fc4
Fixed dangling reference bug that was resulting in invalid mapped_io segment in EDBG session object.
2024-11-17 13:13:15 +00:00
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3009cdd951
Tidying
2024-11-16 21:50:04 +00:00
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4147af618b
Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)
2024-11-16 21:49:49 +00:00
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eebba986b5
RISC-V GDB server
2024-11-16 20:43:22 +00:00
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26f4f8f90e
Tidying
2024-11-16 20:06:55 +00:00
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07283a2dc7
Flash programming support for WCH-LinkE tool
2024-11-16 20:05:26 +00:00
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de02bf318c
Corrected HW breakpoint count bug in WchRiscV target
2024-11-06 20:06:55 +00:00
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7662dec100
Tidying
2024-11-06 20:05:59 +00:00
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f0b7f3193c
Corrected string->int conversion bug in TargetPinDescriptor.
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The `numericPosition` member should really be removed. Will revisit later.
2024-10-27 00:28:41 +01:00
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1bb2214721
Tidying
2024-10-18 00:02:00 +01:00
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9c1385a048
Deleted TDF documentation (don't have the capacity to maintain it ATM)
2024-10-18 00:01:21 +01:00
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52171734d8
New WchRiscV target class
2024-10-12 23:16:16 +01:00
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5c896bb2ca
Support for property groups in variant elements, in TDFs
2024-10-12 16:25:11 +01:00
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4eeeaf7fa6
Reordered pads in AVR8 TDFs
2024-10-12 00:03:49 +01:00
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9cfc171255
Added description member to TargetPeripheralDescriptor
2024-10-08 21:26:03 +01:00
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9e4d10ae91
Tidying
2024-10-07 20:03:19 +01:00
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248c51acc8
Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.
2024-10-07 20:02:39 +01:00
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607a344107
Made TargetMemoryCache use TargetMemorySegmentDescriptor, as the base memory descriptor (instead of TargetMemoryAddressSpaceDescriptor).
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Basing the memory cache on address spaces will result in large amounts of memory being unnecessarily reserved for large address spaces.
2024-10-07 00:14:39 +01:00
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d71083c3f9
Tidying
2024-10-06 18:10:02 +01:00
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ecd0f5b054
First pass at RISC-V hardware breakpoints (Trigger module)
2024-10-06 17:54:08 +01:00
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7fc1145d4b
Moved reserveSteppingBreakpoint AVR8 config param to more generic TargetConfig struct
2024-10-06 17:09:06 +01:00
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675b375da7
Removed non-alphanumeric characters from keys in TDFs
2024-10-05 02:18:20 +01:00
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12ca84735f
Renamed USB pad keys in TDFs
2024-10-05 02:07:24 +01:00
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d906f2f426
Added alternative flag to Signal element in TDFs
2024-10-04 23:45:16 +01:00
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5b2b73eb9f
Renamed SCK ISP signal to SCLK, for consistency
2024-10-03 23:39:38 +01:00
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ca498c64c2
Added SDI physical interface
2024-10-03 22:56:13 +01:00
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af865d09e5
Added Signal elements to PhysicalInterface elements in TDFs
2024-10-03 22:45:24 +01:00
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e522261991
Replaced group attribute with name attribute in Signal TDF element
2024-09-15 15:27:08 +01:00
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df06757124
Activate target before calling Target::targetDescriptor()
2024-09-07 13:07:40 +01:00
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cb9059c691
Tidying
2024-08-26 12:42:04 +01:00
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4f9bb0ac3e
Target variant keys
2024-08-19 19:43:02 +01:00
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2f6238e360
Tidying
2024-08-17 12:44:01 +01:00
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c662e946ca
Updated application to code to accomodate changes to TDF format (new pad elements and changes to variant elements)
2024-08-16 23:02:35 +01:00
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8ba29c258d
TDF and TDF script changes (application changes pending):
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- Added new `pad` element to TDFs
- Refactored `pin` and `signal` elements to accommodate new `pad` element
- Improved validation of signal-to-pad relation in TDF validation script
- Added key attribute to `variant` element
- Removed `package` attribute from `variant` element
2024-08-13 22:17:49 +01:00
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e4552581bf
Made resolving of pin type case-insensitive
2024-08-13 19:55:37 +01:00
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f1c82ecd28
Made key and name attributes optional in register-group-instance TDF elements
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Also removed the attribute from all instances of the element, where it wasn't necessary.
2024-08-13 19:54:05 +01:00
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f3e2a5c8a5
Tidying AVR TDFs
2024-08-01 19:27:16 +01:00
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8246c03d29
Removed reserved bit fields from AVR TDFs
2024-07-30 20:47:18 +01:00
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3f88e2022c
Refactored descriptor ID generation and added IDs to peripherals, register groups and registers
2024-07-25 19:03:26 +01:00
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dd80c254a2
Added postActivate() to the target interface, for outputting any target specific info after activation.
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Removed the logging of the generic target ID from the TargetController
2024-07-23 21:36:07 +01:00
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6cdbfbe950
Massive refactor to accommodate RISC-V targets
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- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
2024-07-23 21:14:22 +01:00
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9026601a2d
Corrected xoscsel bit field mask in XMEGA TDFs
2024-07-08 00:19:02 +01:00
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4bb309a179
Refactored physical interfaces in TDFs and TDF scripts
2024-07-06 01:33:19 +01:00
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48eeec67cc
Corrected production and user signature modules in some AVR8 XMEGA and ATMEGA TDFs - they contained descriptions of registers that do not exist on those targets
2024-06-05 19:32:19 +01:00
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081d1e0bcd
Added executable flag to memory segments in TDFs
2024-04-29 20:25:36 +01:00
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8324d30742
Added address space for the register file, in AVR8 targets, where the register file is not located in the data address space
2024-04-04 22:48:55 +01:00
