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674b11575d
Tidying
2024-12-24 19:58:48 +00:00
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28e0a6d9e4
Renaming and other tidying
2024-12-21 13:51:00 +00:00
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79b7457c89
GPIO pad state access and manipulation for WCH RISC-V targets
2024-12-21 02:10:31 +00:00
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d485263c6d
Enabled memory inspection for boot segment of WCH RISC-V targets
2024-12-19 23:47:24 +00:00
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36abea6ce1
Tidying
2024-12-16 21:38:09 +00:00
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9486cc0163
Help text for target driver passthrough commands
2024-12-16 21:37:24 +00:00
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40859201e4
Target driver passthrough commands
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Added `pm` commands to manage the program mode of WCH targets
2024-12-15 17:32:58 +00:00
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1392cda74f
Adding boot/user mode switching functionality for WCH RISC-V targets
2024-12-15 02:47:39 +00:00
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4ff7c76621
New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors
2024-12-15 00:40:54 +00:00
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6dd8f0453e
Block memory writes to read-only selected program memory segments
2024-12-15 00:33:48 +00:00
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9e5d69dee4
Tidying
2024-12-14 16:17:54 +00:00
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2580cecb26
Handle mapped program memory segment aliasing properly, on WCH RISC-V targets
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- Added `program_segment_key` target config param, to allow the user to specify the desired program memory segment
- Added the ability to resolve the currently aliased segment, by means of probing the mapped segment
- Added program counter transformation, when the mapped segment is aliasing a foreign segment
- Other bites of tidying
2024-12-14 02:09:25 +00:00
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cbfbd9f4b8
Applied debug-interface-specific access restrictions for memory and registers
2024-12-07 16:43:16 +00:00
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33ed399337
WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying
2024-12-05 23:09:01 +00:00
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966244a01a
Tidying
2024-11-29 01:53:01 +00:00
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1d4def228b
Tidying
2024-11-29 01:19:58 +00:00
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265e60c1b7
Fixed bug in RISC-V ISA string parsing
2024-11-29 01:13:12 +00:00
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49cf2e5e9a
Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.
2024-11-29 01:06:44 +00:00
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8e86cfb152
Tidying
2024-11-28 21:49:03 +00:00
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899cbc92c4
Made default value of reserveSteppingBreakpoint target config param vary across targets
2024-11-24 19:33:28 +00:00
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7c647caa67
Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity
2024-11-24 19:32:00 +00:00
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d8131080ec
Implemented memory access via program buffer, in RISC-V debug translator
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- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator
2024-11-23 20:14:47 +00:00
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4147af618b
Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)
2024-11-16 21:49:49 +00:00
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eebba986b5
RISC-V GDB server
2024-11-16 20:43:22 +00:00
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26f4f8f90e
Tidying
2024-11-16 20:06:55 +00:00
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07283a2dc7
Flash programming support for WCH-LinkE tool
2024-11-16 20:05:26 +00:00
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de02bf318c
Corrected HW breakpoint count bug in WchRiscV target
2024-11-06 20:06:55 +00:00
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52171734d8
New WchRiscV target class
2024-10-12 23:16:16 +01:00
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9cfc171255
Added description member to TargetPeripheralDescriptor
2024-10-08 21:26:03 +01:00
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248c51acc8
Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.
2024-10-07 20:02:39 +01:00
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d71083c3f9
Tidying
2024-10-06 18:10:02 +01:00
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ecd0f5b054
First pass at RISC-V hardware breakpoints (Trigger module)
2024-10-06 17:54:08 +01:00
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4f9bb0ac3e
Target variant keys
2024-08-19 19:43:02 +01:00
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c662e946ca
Updated application to code to accomodate changes to TDF format (new pad elements and changes to variant elements)
2024-08-16 23:02:35 +01:00
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3f88e2022c
Refactored descriptor ID generation and added IDs to peripherals, register groups and registers
2024-07-25 19:03:26 +01:00
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dd80c254a2
Added postActivate() to the target interface, for outputting any target specific info after activation.
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Removed the logging of the generic target ID from the TargetController
2024-07-23 21:36:07 +01:00
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6cdbfbe950
Massive refactor to accommodate RISC-V targets
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- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
2024-07-23 21:14:22 +01:00
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ed54b0e726
Tidying
2024-03-29 16:31:14 +00:00
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75d5124265
Moved TargetRegisterDescriptor struct to separate file
2024-03-09 17:16:29 +00:00
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cc33eea712
RISC-V target ID verification upon activation
2023-12-17 18:43:16 +00:00
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66cbd89051
- Refactored AVR8 constructor, moving TDF construction to the TargetControllerComponent
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- The `TargetControllerComponent` now resolves the target via the new generated mapping approach
- Added `TargetDescriptionFile` derived class
- Removed obsolete JSON map processing code
- Other bits of refactoring and tidying
2023-12-17 18:40:52 +00:00
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d6c3f8044a
Tidying
2023-12-08 23:04:13 +00:00
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f4b30dbdf6
Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface
2023-12-08 23:04:04 +00:00
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eab1688b1a
Memory access commands should be LSB
2023-12-02 14:00:06 +00:00
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c792f92493
Corrected hart discovery bug
2023-12-02 13:59:18 +00:00
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c962c5e4ca
Tidying
2023-11-26 15:58:28 +00:00
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17a72bf231
Implemented RiscV::writeMemory()
2023-11-26 15:58:18 +00:00
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ddcb122137
Tidying
2023-11-25 23:19:38 +00:00
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d88b828bad
Implemented RiscV::reset()
2023-11-25 21:19:57 +00:00
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35fef9b41b
Moved abstract command construction outside of loop. Didn't need to be there. Improved efficiency
2023-11-25 19:39:34 +00:00
