Nav 1392cda74f Adding boot/user mode switching functionality for WCH RISC-V targets

2024-12-15 02:47:39 +00:00

..

Exceptions

Handle mapped program memory segment aliasing properly, on WCH RISC-V targets

2024-12-14 02:09:25 +00:00

Opcodes

WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying

2024-12-05 23:09:01 +00:00

Wch

Adding boot/user mode switching functionality for WCH RISC-V targets

2024-12-15 02:47:39 +00:00

IsaDescriptor.cpp

Tidying

2024-11-29 01:53:01 +00:00

IsaDescriptor.hpp

Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.

2024-11-29 01:06:44 +00:00

ProgramBreakpoint.hpp

WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying

2024-12-05 23:09:01 +00:00

RiscV.cpp

New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors

2024-12-15 00:40:54 +00:00

RiscV.hpp

New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors

2024-12-15 00:40:54 +00:00

RiscVTargetConfig.cpp

Massive refactor to accommodate RISC-V targets

2024-07-23 21:14:22 +01:00

RiscVTargetConfig.hpp

Massive refactor to accommodate RISC-V targets

2024-07-23 21:14:22 +01:00

TargetDescriptionFile.cpp

Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.

2024-11-29 01:06:44 +00:00

TargetDescriptionFile.hpp

Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.

2024-11-29 01:06:44 +00:00