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cbfbd9f4b8
Applied debug-interface-specific access restrictions for memory and registers
2024-12-07 16:43:16 +00:00
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33ed399337
WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying
2024-12-05 23:09:01 +00:00
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899cbc92c4
Made default value of reserveSteppingBreakpoint target config param vary across targets
2024-11-24 19:33:28 +00:00
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4147af618b
Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)
2024-11-16 21:49:49 +00:00
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9cfc171255
Added description member to TargetPeripheralDescriptor
2024-10-08 21:26:03 +01:00
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d71083c3f9
Tidying
2024-10-06 18:10:02 +01:00
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4f9bb0ac3e
Target variant keys
2024-08-19 19:43:02 +01:00
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2f6238e360
Tidying
2024-08-17 12:44:01 +01:00
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c662e946ca
Updated application to code to accomodate changes to TDF format (new pad elements and changes to variant elements)
2024-08-16 23:02:35 +01:00
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3f88e2022c
Refactored descriptor ID generation and added IDs to peripherals, register groups and registers
2024-07-25 19:03:26 +01:00
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dd80c254a2
Added postActivate() to the target interface, for outputting any target specific info after activation.
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Removed the logging of the generic target ID from the TargetController
2024-07-23 21:36:07 +01:00
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6cdbfbe950
Massive refactor to accommodate RISC-V targets
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- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
2024-07-23 21:14:22 +01:00
