doryan/BloomPatched
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4147af618b7b0141705821284dae75ebf3e57a35
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16 Commits

Author SHA1 Message Date
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4147af618b Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias) 2024-11-16 21:49:49 +00:00
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a7ee6cbae2 Refactored page alignment code in EDBG and RISC-V debug translator driver 2024-11-16 19:55:34 +00:00
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72d0c28d08 Fixed bug in assertion in RISC-V debug translator 2024-10-20 00:44:09 +01:00
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a65be393be Tidying 2024-10-19 23:11:22 +01:00
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00d6f5fb71 Corrected bug in RISC-V debug translator where a reset wasn't always keeping the target halted 2024-10-19 14:22:12 +01:00
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348ec19c1b Tidying RISC-V register structs 
- Removed unnecessary bit fields
- Added default values to members
- Removed all user-defined constructors to make the structs aggregate, replacing the from-value constructor with a `fromValue()` status member function.
- Made use of designated initialisation
- Changed unscoped enums to scoped
- Other small bits of tidying
 2024-10-16 21:22:16 +01:00
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17b90e3c08 Tidying 2024-10-12 23:37:13 +01:00
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9e4d10ae91 Tidying 2024-10-07 20:03:19 +01:00
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248c51acc8 Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints. 2024-10-07 20:02:39 +01:00
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418db1df99 Added config struct for RISC-V debug translator implementation, and WCH debug tools. 
Also some tidying in the `DebugToolConfig` struct
 2024-10-06 23:32:36 +01:00
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d71083c3f9 Tidying 2024-10-06 18:10:02 +01:00
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6c67424af9 On RISC-V activation, clear any triggers that were left over from a previous debug session 2024-10-06 18:06:58 +01:00
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ecd0f5b054 First pass at RISC-V hardware breakpoints (Trigger module) 2024-10-06 17:54:08 +01:00
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ecf0bd8919 Added try member functions for RISC-V abstract commands and register access 2024-09-04 00:15:46 +01:00
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914153077e Corrected memory address/size alignment in EDBG and RISC-V drivers 2024-08-30 19:59:59 +01:00
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6cdbfbe950 Massive refactor to accommodate RISC-V targets 
- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
 2024-07-23 21:14:22 +01:00