doryan/BloomPatched
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129e54dd2d1e8e845fb452c9a7e9669278fb48ca
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17 Commits

Author SHA1 Message Date
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dd80c254a2 Added postActivate() to the target interface, for outputting any target specific info after activation. 
Removed the logging of the generic target ID from the TargetController
 2024-07-23 21:36:07 +01:00
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6cdbfbe950 Massive refactor to accommodate RISC-V targets 
- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
 2024-07-23 21:14:22 +01:00
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66cbd89051 - Refactored AVR8 constructor, moving TDF construction to the TargetControllerComponent 
- The `TargetControllerComponent` now resolves the target via the new generated mapping approach
- Added `TargetDescriptionFile` derived class
- Removed obsolete JSON map processing code
- Other bits of refactoring and tidying
 2023-12-17 18:40:52 +00:00
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f4b30dbdf6 Added RiscVProgramInterface for RISC-V debug tools that are unable to program RISC-V targets via the debug interface 2023-12-08 23:04:04 +00:00
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17a72bf231 Implemented RiscV::writeMemory() 2023-11-26 15:58:18 +00:00
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ddcb122137 Tidying 2023-11-25 23:19:38 +00:00
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eda6fe0c7f Enable/disable debug module on activation/deactivation of RISC-V targets 2023-11-25 19:08:40 +00:00
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2fc639fb14 Tidying 2023-11-25 07:44:50 +00:00
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73b1328f9f RISC-V general purpose register descriptors 2023-11-24 15:19:52 +00:00
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3908ad6848 Switched to using underlying RegisterNumber type for RISC-V register numbers 2023-11-23 23:31:13 +00:00
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86d3709e46 Tidying 2023-11-23 16:35:09 +00:00
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db7d735d68 Implemented RISC-V stepping 2023-11-23 16:34:35 +00:00
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257c316369 RISC-V register access 2023-11-23 16:32:53 +00:00
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522187382a RISC-V abstract commands 2023-11-23 15:21:46 +00:00
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776ce3c44d Tidying 2023-11-23 13:53:12 +00:00
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c1c9a0ceeb RISC-V hart selection 2023-11-23 12:56:26 +00:00
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fc1fd22499 Made a start with RISC-V target implementation 2023-11-22 00:38:40 +00:00