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Memory access commands should be LSB

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2023-12-02 14:00:06 +00:00
parent c792f92493
commit eab1688b1a
1 changed files with 7 additions and 7 deletions
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14
src/Targets/RiscV/RiscV.cpp
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@@ -341,10 +341,10 @@ namespace Targets::RiscV
this->executeAbstractCommand(command); this->executeAbstractCommand(command);
const auto data = this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0); const auto data = this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0);
output.emplace_back(static_cast<unsigned char>(data >> 24));
output.emplace_back(static_cast<unsigned char>(data >> 16));
output.emplace_back(static_cast<unsigned char>(data >> 8));
output.emplace_back(static_cast<unsigned char>(data)); output.emplace_back(static_cast<unsigned char>(data));
output.emplace_back(static_cast<unsigned char>(data >> 8));
output.emplace_back(static_cast<unsigned char>(data >> 16));
output.emplace_back(static_cast<unsigned char>(data >> 24));
} }
return output; return output;
@@ -410,10 +410,10 @@ namespace Targets::RiscV
this->riscVDebugInterface->writeDebugModuleRegister( this->riscVDebugInterface->writeDebugModuleRegister(
RegisterAddress::ABSTRACT_DATA_0, RegisterAddress::ABSTRACT_DATA_0,
static_cast<RegisterValue>( static_cast<RegisterValue>(
(buffer[offset] << 24) (buffer[offset + 3] << 24)
| (buffer[offset + 1] << 16) | (buffer[offset + 2] << 16)
| (buffer[offset + 2] << 8) | (buffer[offset + 1] << 8)
| (buffer[offset + 3]) | (buffer[offset])
) )
); );