This commit is contained in:
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2024-10-06 18:10:02 +01:00
parent 23056bcac5
commit d71083c3f9
4 changed files with 20 additions and 17 deletions

View File

@@ -97,6 +97,8 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
this->reset(); this->reset();
this->triggerDescriptorsByIndex = this->discoverTriggers(); this->triggerDescriptorsByIndex = this->discoverTriggers();
Logger::debug("Discovered RISC-V triggers: " + std::to_string(this->triggerDescriptorsByIndex.size()));
if (!this->triggerDescriptorsByIndex.empty()) { if (!this->triggerDescriptorsByIndex.empty()) {
// Clear any left-over triggers from the previous debug session // Clear any left-over triggers from the previous debug session
this->clearAllBreakpoints(); this->clearAllBreakpoints();
@@ -288,6 +290,7 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
} }
void DebugTranslator::clearAllBreakpoints() { void DebugTranslator::clearAllBreakpoints() {
// To ensure that any untracked breakpoints are cleared, we clear all triggers on the target.
for (const auto [triggerIndex, triggerDescriptor] : this->triggerDescriptorsByIndex) { for (const auto [triggerIndex, triggerDescriptor] : this->triggerDescriptorsByIndex) {
this->clearTrigger(triggerDescriptor); this->clearTrigger(triggerDescriptor);
} }
@@ -789,7 +792,7 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
void DebugTranslator::clearTrigger(const TriggerModule::TriggerDescriptor& triggerDescriptor) { void DebugTranslator::clearTrigger(const TriggerModule::TriggerDescriptor& triggerDescriptor) {
using TriggerModule::TriggerType; using TriggerModule::TriggerType;
Logger::debug("Clearing trigger " + std::to_string(triggerDescriptor.index)); // TODO: keep this, but reword it Logger::debug("Clearing RISC-V trigger " + std::to_string(triggerDescriptor.index));
if (triggerDescriptor.supportedTypes.contains(TriggerType::MATCH_CONTROL)) { if (triggerDescriptor.supportedTypes.contains(TriggerType::MATCH_CONTROL)) {
using TriggerModule::Registers::MatchControl; using TriggerModule::Registers::MatchControl;

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@@ -23,7 +23,7 @@ namespace Targets::Microchip::Avr8
using namespace Exceptions; using namespace Exceptions;
Avr8::Avr8(const TargetConfig& targetConfig, TargetDescriptionFile&& targetDescriptionFile) Avr8::Avr8(const TargetConfig& targetConfig, TargetDescriptionFile&& targetDescriptionFile)
: targetConfig(Avr8TargetConfig(targetConfig)) : targetConfig(Avr8TargetConfig{targetConfig})
, targetDescriptionFile(std::move(targetDescriptionFile)) , targetDescriptionFile(std::move(targetDescriptionFile))
, dataAddressSpaceDescriptor(this->targetDescriptionFile.getDataAddressSpaceDescriptor()) , dataAddressSpaceDescriptor(this->targetDescriptionFile.getDataAddressSpaceDescriptor())
, fuseAddressSpaceDescriptor(this->targetDescriptionFile.getFuseAddressSpaceDescriptor()) , fuseAddressSpaceDescriptor(this->targetDescriptionFile.getFuseAddressSpaceDescriptor())

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@@ -47,7 +47,7 @@ namespace Targets::Microchip::Avr8
stream << std::setw(2) << static_cast<unsigned int>(this->byteOne); stream << std::setw(2) << static_cast<unsigned int>(this->byteOne);
stream << std::setw(2) << static_cast<unsigned int>(this->byteTwo); stream << std::setw(2) << static_cast<unsigned int>(this->byteTwo);
return "0x" + stream.str(); return "0x" + Services::StringService::asciiToUpper(stream.str());
} }
bool operator == (const TargetSignature& signature) const { bool operator == (const TargetSignature& signature) const {

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@@ -18,7 +18,7 @@ namespace Targets::RiscV
const TargetConfig& targetConfig, const TargetConfig& targetConfig,
TargetDescriptionFile&& targetDescriptionFile TargetDescriptionFile&& targetDescriptionFile
) )
: targetConfig(RiscVTargetConfig(targetConfig)) : targetConfig(RiscVTargetConfig{targetConfig})
, targetDescriptionFile(std::move(targetDescriptionFile)) , targetDescriptionFile(std::move(targetDescriptionFile))
, cpuRegisterAddressSpaceDescriptor(RiscV::generateCpuRegisterAddressSpaceDescriptor()) , cpuRegisterAddressSpaceDescriptor(RiscV::generateCpuRegisterAddressSpaceDescriptor())
, csrMemorySegmentDescriptor(this->cpuRegisterAddressSpaceDescriptor.getMemorySegmentDescriptor("cs_registers")) , csrMemorySegmentDescriptor(this->cpuRegisterAddressSpaceDescriptor.getMemorySegmentDescriptor("cs_registers"))
@@ -62,10 +62,10 @@ namespace Targets::RiscV
const auto deviceId = this->riscVIdInterface->getDeviceId(); const auto deviceId = this->riscVIdInterface->getDeviceId();
const auto tdfDeviceId = this->targetDescriptionFile.getTargetId(); const auto tdfDeviceId = this->targetDescriptionFile.getTargetId();
if (deviceId != tdfDeviceId) { if (deviceId != tdfDeviceId) {
throw Exceptions::InvalidConfig( throw Exceptions::InvalidConfig{
"RISC-V target ID mismatch - expected " + tdfDeviceId + " but got " + deviceId + "RISC-V target ID mismatch - expected " + tdfDeviceId + " but got " + deviceId +
". Please check target configuration." ". Please check target configuration."
); };
} }
} }
@@ -170,9 +170,9 @@ namespace Targets::RiscV
!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress) !this->csrMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress) && !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
) { ) {
throw Exceptions::Exception( throw Exceptions::Exception{
"Cannot access CPU register \"" + descriptor->key + "\" - unknown memory segment" "Cannot access CPU register \"" + descriptor->key + "\" - unknown memory segment"
); };
} }
cpuRegisterDescriptors.emplace_back(descriptor); cpuRegisterDescriptors.emplace_back(descriptor);
@@ -180,9 +180,9 @@ namespace Targets::RiscV
} }
if (descriptor->addressSpaceId != this->sysAddressSpaceDescriptor.id) { if (descriptor->addressSpaceId != this->sysAddressSpaceDescriptor.id) {
throw Exceptions::Exception( throw Exceptions::Exception{
"Cannot access register \"" + descriptor->key + "\" - unknown address space" "Cannot access register \"" + descriptor->key + "\" - unknown address space"
); };
} }
auto value = this->riscVDebugInterface->readMemory( auto value = this->riscVDebugInterface->readMemory(
@@ -217,7 +217,7 @@ namespace Targets::RiscV
!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress) !this->csrMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress) && !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
) { ) {
throw Exceptions::Exception("Cannot access CPU register - unknown memory segment"); throw Exceptions::Exception{"Cannot access CPU register - unknown memory segment"};
} }
this->riscVDebugInterface->writeCpuRegisters({pair}); this->riscVDebugInterface->writeCpuRegisters({pair});
@@ -225,9 +225,9 @@ namespace Targets::RiscV
} }
if (descriptor.addressSpaceId != this->sysAddressSpaceDescriptor.id) { if (descriptor.addressSpaceId != this->sysAddressSpaceDescriptor.id) {
throw Exceptions::Exception( throw Exceptions::Exception{
"Cannot access register \"" + descriptor.key + "\" - unknown address space" "Cannot access register \"" + descriptor.key + "\" - unknown address space"
); };
} }
auto value = pair.second; auto value = pair.second;
@@ -397,16 +397,16 @@ namespace Targets::RiscV
); );
if (segmentDescriptors.empty()) { if (segmentDescriptors.empty()) {
throw Exceptions::Exception( throw Exceptions::Exception{
"Cannot access system register \"" + regDescriptor.key + "\" - unknown memory segment" "Cannot access system register \"" + regDescriptor.key + "\" - unknown memory segment"
); };
} }
if (segmentDescriptors.size() != 1) { if (segmentDescriptors.size() != 1) {
throw Exceptions::Exception( throw Exceptions::Exception{
"Cannot access system register \"" + regDescriptor.key "Cannot access system register \"" + regDescriptor.key
+ "\" - register spans multiple memory segments" + "\" - register spans multiple memory segments"
); };
} }
return *(segmentDescriptors.front()); return *(segmentDescriptors.front());