Tidying
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@@ -97,6 +97,8 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
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this->reset();
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this->reset();
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this->triggerDescriptorsByIndex = this->discoverTriggers();
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this->triggerDescriptorsByIndex = this->discoverTriggers();
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Logger::debug("Discovered RISC-V triggers: " + std::to_string(this->triggerDescriptorsByIndex.size()));
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if (!this->triggerDescriptorsByIndex.empty()) {
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if (!this->triggerDescriptorsByIndex.empty()) {
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// Clear any left-over triggers from the previous debug session
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// Clear any left-over triggers from the previous debug session
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this->clearAllBreakpoints();
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this->clearAllBreakpoints();
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@@ -288,6 +290,7 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
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}
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}
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void DebugTranslator::clearAllBreakpoints() {
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void DebugTranslator::clearAllBreakpoints() {
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// To ensure that any untracked breakpoints are cleared, we clear all triggers on the target.
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for (const auto [triggerIndex, triggerDescriptor] : this->triggerDescriptorsByIndex) {
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for (const auto [triggerIndex, triggerDescriptor] : this->triggerDescriptorsByIndex) {
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this->clearTrigger(triggerDescriptor);
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this->clearTrigger(triggerDescriptor);
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}
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}
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@@ -789,7 +792,7 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
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void DebugTranslator::clearTrigger(const TriggerModule::TriggerDescriptor& triggerDescriptor) {
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void DebugTranslator::clearTrigger(const TriggerModule::TriggerDescriptor& triggerDescriptor) {
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using TriggerModule::TriggerType;
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using TriggerModule::TriggerType;
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Logger::debug("Clearing trigger " + std::to_string(triggerDescriptor.index)); // TODO: keep this, but reword it
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Logger::debug("Clearing RISC-V trigger " + std::to_string(triggerDescriptor.index));
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if (triggerDescriptor.supportedTypes.contains(TriggerType::MATCH_CONTROL)) {
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if (triggerDescriptor.supportedTypes.contains(TriggerType::MATCH_CONTROL)) {
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using TriggerModule::Registers::MatchControl;
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using TriggerModule::Registers::MatchControl;
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@@ -23,7 +23,7 @@ namespace Targets::Microchip::Avr8
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using namespace Exceptions;
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using namespace Exceptions;
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Avr8::Avr8(const TargetConfig& targetConfig, TargetDescriptionFile&& targetDescriptionFile)
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Avr8::Avr8(const TargetConfig& targetConfig, TargetDescriptionFile&& targetDescriptionFile)
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: targetConfig(Avr8TargetConfig(targetConfig))
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: targetConfig(Avr8TargetConfig{targetConfig})
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, targetDescriptionFile(std::move(targetDescriptionFile))
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, targetDescriptionFile(std::move(targetDescriptionFile))
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, dataAddressSpaceDescriptor(this->targetDescriptionFile.getDataAddressSpaceDescriptor())
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, dataAddressSpaceDescriptor(this->targetDescriptionFile.getDataAddressSpaceDescriptor())
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, fuseAddressSpaceDescriptor(this->targetDescriptionFile.getFuseAddressSpaceDescriptor())
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, fuseAddressSpaceDescriptor(this->targetDescriptionFile.getFuseAddressSpaceDescriptor())
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@@ -47,7 +47,7 @@ namespace Targets::Microchip::Avr8
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stream << std::setw(2) << static_cast<unsigned int>(this->byteOne);
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stream << std::setw(2) << static_cast<unsigned int>(this->byteOne);
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stream << std::setw(2) << static_cast<unsigned int>(this->byteTwo);
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stream << std::setw(2) << static_cast<unsigned int>(this->byteTwo);
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return "0x" + stream.str();
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return "0x" + Services::StringService::asciiToUpper(stream.str());
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}
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}
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bool operator == (const TargetSignature& signature) const {
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bool operator == (const TargetSignature& signature) const {
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@@ -18,7 +18,7 @@ namespace Targets::RiscV
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const TargetConfig& targetConfig,
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const TargetConfig& targetConfig,
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TargetDescriptionFile&& targetDescriptionFile
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TargetDescriptionFile&& targetDescriptionFile
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)
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)
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: targetConfig(RiscVTargetConfig(targetConfig))
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: targetConfig(RiscVTargetConfig{targetConfig})
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, targetDescriptionFile(std::move(targetDescriptionFile))
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, targetDescriptionFile(std::move(targetDescriptionFile))
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, cpuRegisterAddressSpaceDescriptor(RiscV::generateCpuRegisterAddressSpaceDescriptor())
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, cpuRegisterAddressSpaceDescriptor(RiscV::generateCpuRegisterAddressSpaceDescriptor())
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, csrMemorySegmentDescriptor(this->cpuRegisterAddressSpaceDescriptor.getMemorySegmentDescriptor("cs_registers"))
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, csrMemorySegmentDescriptor(this->cpuRegisterAddressSpaceDescriptor.getMemorySegmentDescriptor("cs_registers"))
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@@ -62,10 +62,10 @@ namespace Targets::RiscV
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const auto deviceId = this->riscVIdInterface->getDeviceId();
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const auto deviceId = this->riscVIdInterface->getDeviceId();
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const auto tdfDeviceId = this->targetDescriptionFile.getTargetId();
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const auto tdfDeviceId = this->targetDescriptionFile.getTargetId();
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if (deviceId != tdfDeviceId) {
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if (deviceId != tdfDeviceId) {
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throw Exceptions::InvalidConfig(
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throw Exceptions::InvalidConfig{
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"RISC-V target ID mismatch - expected " + tdfDeviceId + " but got " + deviceId +
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"RISC-V target ID mismatch - expected " + tdfDeviceId + " but got " + deviceId +
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". Please check target configuration."
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". Please check target configuration."
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);
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};
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}
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}
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}
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}
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@@ -170,9 +170,9 @@ namespace Targets::RiscV
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!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
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!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
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&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
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&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress)
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) {
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) {
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throw Exceptions::Exception(
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throw Exceptions::Exception{
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"Cannot access CPU register \"" + descriptor->key + "\" - unknown memory segment"
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"Cannot access CPU register \"" + descriptor->key + "\" - unknown memory segment"
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);
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};
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}
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}
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cpuRegisterDescriptors.emplace_back(descriptor);
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cpuRegisterDescriptors.emplace_back(descriptor);
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@@ -180,9 +180,9 @@ namespace Targets::RiscV
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}
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}
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if (descriptor->addressSpaceId != this->sysAddressSpaceDescriptor.id) {
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if (descriptor->addressSpaceId != this->sysAddressSpaceDescriptor.id) {
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throw Exceptions::Exception(
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throw Exceptions::Exception{
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"Cannot access register \"" + descriptor->key + "\" - unknown address space"
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"Cannot access register \"" + descriptor->key + "\" - unknown address space"
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);
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};
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}
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}
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auto value = this->riscVDebugInterface->readMemory(
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auto value = this->riscVDebugInterface->readMemory(
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@@ -217,7 +217,7 @@ namespace Targets::RiscV
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!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
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!this->csrMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
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&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
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&& !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor.startAddress)
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) {
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) {
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throw Exceptions::Exception("Cannot access CPU register - unknown memory segment");
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throw Exceptions::Exception{"Cannot access CPU register - unknown memory segment"};
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}
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}
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this->riscVDebugInterface->writeCpuRegisters({pair});
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this->riscVDebugInterface->writeCpuRegisters({pair});
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@@ -225,9 +225,9 @@ namespace Targets::RiscV
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}
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}
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if (descriptor.addressSpaceId != this->sysAddressSpaceDescriptor.id) {
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if (descriptor.addressSpaceId != this->sysAddressSpaceDescriptor.id) {
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throw Exceptions::Exception(
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throw Exceptions::Exception{
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"Cannot access register \"" + descriptor.key + "\" - unknown address space"
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"Cannot access register \"" + descriptor.key + "\" - unknown address space"
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);
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};
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}
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}
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auto value = pair.second;
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auto value = pair.second;
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@@ -397,16 +397,16 @@ namespace Targets::RiscV
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);
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);
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if (segmentDescriptors.empty()) {
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if (segmentDescriptors.empty()) {
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throw Exceptions::Exception(
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throw Exceptions::Exception{
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"Cannot access system register \"" + regDescriptor.key + "\" - unknown memory segment"
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"Cannot access system register \"" + regDescriptor.key + "\" - unknown memory segment"
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);
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};
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}
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}
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if (segmentDescriptors.size() != 1) {
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if (segmentDescriptors.size() != 1) {
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throw Exceptions::Exception(
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throw Exceptions::Exception{
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"Cannot access system register \"" + regDescriptor.key
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"Cannot access system register \"" + regDescriptor.key
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+ "\" - register spans multiple memory segments"
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+ "\" - register spans multiple memory segments"
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);
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};
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}
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}
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return *(segmentDescriptors.front());
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return *(segmentDescriptors.front());
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