This commit is contained in:
Nav
2023-11-23 17:46:32 +00:00
parent 5d552e4e7c
commit ba32e9baf9
3 changed files with 31 additions and 9 deletions

View File

@@ -3,6 +3,8 @@
#include <cstdint> #include <cstdint>
#include "src/Targets/RiscV/DebugModule/DebugModule.hpp" #include "src/Targets/RiscV/DebugModule/DebugModule.hpp"
#include "src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp"
#include "src/Targets/RiscV/TargetParameters.hpp" #include "src/Targets/RiscV/TargetParameters.hpp"
namespace DebugToolDrivers::TargetInterfaces::RiscV namespace DebugToolDrivers::TargetInterfaces::RiscV
@@ -63,6 +65,12 @@ namespace DebugToolDrivers::TargetInterfaces::RiscV
Targets::RiscV::DebugModule::RegisterAddress address Targets::RiscV::DebugModule::RegisterAddress address
) = 0; ) = 0;
Targets::RiscV::DebugModule::RegisterValue readDebugModuleRegister(
Targets::RiscV::DebugModule::Registers::RegisterAddress address
) {
return this->readDebugModuleRegister(static_cast<Targets::RiscV::DebugModule::RegisterAddress>(address));
};
/** /**
* Should write a value to a debug module register. * Should write a value to a debug module register.
* *
@@ -76,5 +84,15 @@ namespace DebugToolDrivers::TargetInterfaces::RiscV
Targets::RiscV::DebugModule::RegisterAddress address, Targets::RiscV::DebugModule::RegisterAddress address,
Targets::RiscV::DebugModule::RegisterValue value Targets::RiscV::DebugModule::RegisterValue value
) = 0; ) = 0;
void writeDebugModuleRegister(
Targets::RiscV::DebugModule::Registers::RegisterAddress address,
Targets::RiscV::DebugModule::RegisterValue value
) {
return this->writeDebugModuleRegister(
static_cast<Targets::RiscV::DebugModule::RegisterAddress>(address),
value
);
};
}; };
} }

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@@ -2,9 +2,11 @@
#include <cstdint> #include <cstdint>
#include "src/Targets/RiscV/DebugModule/DebugModule.hpp"
namespace Targets::RiscV::DebugModule::Registers namespace Targets::RiscV::DebugModule::Registers
{ {
enum RegisterAddresses: std::uint8_t enum class RegisterAddress: ::Targets::RiscV::DebugModule::RegisterAddress
{ {
ABSTRACT_DATA_0 = 0x04, ABSTRACT_DATA_0 = 0x04,
CONTROL_REGISTER = 0x10, CONTROL_REGISTER = 0x10,

View File

@@ -18,7 +18,7 @@ namespace Targets::RiscV
using Registers::RegisterNumber; using Registers::RegisterNumber;
using Registers::DebugControlStatusRegister; using Registers::DebugControlStatusRegister;
using DebugModule::Registers::RegisterAddresses; using DebugModule::Registers::RegisterAddress;
using DebugModule::Registers::ControlRegister; using DebugModule::Registers::ControlRegister;
using DebugModule::Registers::StatusRegister; using DebugModule::Registers::StatusRegister;
using DebugModule::Registers::AbstractControlStatusRegister; using DebugModule::Registers::AbstractControlStatusRegister;
@@ -301,17 +301,19 @@ namespace Targets::RiscV
ControlRegister RiscV::readDebugModuleControlRegister() { ControlRegister RiscV::readDebugModuleControlRegister() {
return ControlRegister( return ControlRegister(
this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::CONTROL_REGISTER) this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::CONTROL_REGISTER)
); );
} }
StatusRegister RiscV::readDebugModuleStatusRegister() { StatusRegister RiscV::readDebugModuleStatusRegister() {
return StatusRegister(this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::STATUS_REGISTER)); return StatusRegister(
this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::STATUS_REGISTER)
);
} }
AbstractControlStatusRegister RiscV::readDebugModuleAbstractControlStatusRegister() { AbstractControlStatusRegister RiscV::readDebugModuleAbstractControlStatusRegister() {
return AbstractControlStatusRegister( return AbstractControlStatusRegister(
this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::ABSTRACT_CONTROL_STATUS_REGISTER) this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_CONTROL_STATUS_REGISTER)
); );
} }
@@ -335,7 +337,7 @@ namespace Targets::RiscV
this->executeAbstractCommand(command); this->executeAbstractCommand(command);
return this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::ABSTRACT_DATA_0); return this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0);
} }
void RiscV::writeRegister(Registers::RegisterNumber number, RegisterValue value) { void RiscV::writeRegister(Registers::RegisterNumber number, RegisterValue value) {
@@ -352,13 +354,13 @@ namespace Targets::RiscV
RegisterAccessControlField::RegisterSize::SIZE_32 RegisterAccessControlField::RegisterSize::SIZE_32
).value(); ).value();
this->riscVDebugInterface->writeDebugModuleRegister(RegisterAddresses::ABSTRACT_DATA_0, value); this->riscVDebugInterface->writeDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0, value);
this->executeAbstractCommand(command); this->executeAbstractCommand(command);
} }
void RiscV::writeDebugModuleControlRegister(const DebugModule::Registers::ControlRegister& controlRegister) { void RiscV::writeDebugModuleControlRegister(const DebugModule::Registers::ControlRegister& controlRegister) {
this->riscVDebugInterface->writeDebugModuleRegister( this->riscVDebugInterface->writeDebugModuleRegister(
RegisterAddresses::CONTROL_REGISTER, RegisterAddress::CONTROL_REGISTER,
controlRegister.value() controlRegister.value()
); );
} }
@@ -371,7 +373,7 @@ namespace Targets::RiscV
const DebugModule::Registers::AbstractCommandRegister& abstractCommandRegister const DebugModule::Registers::AbstractCommandRegister& abstractCommandRegister
) { ) {
this->riscVDebugInterface->writeDebugModuleRegister( this->riscVDebugInterface->writeDebugModuleRegister(
RegisterAddresses::ABSTRACT_COMMAND_REGISTER, RegisterAddress::ABSTRACT_COMMAND_REGISTER,
abstractCommandRegister.value() abstractCommandRegister.value()
); );