From ba32e9baf95e432cf1a074dbc8f939a944a44cba Mon Sep 17 00:00:00 2001
From: Nav <nav@navnav.me>
Date: Thu, 23 Nov 2023 17:46:32 +0000
Subject: [PATCH] Tidying

---
 .../RiscV/RiscVDebugInterface.hpp              | 18 ++++++++++++++++++
 .../Registers/RegisterAddresses.hpp            |  4 +++-
 src/Targets/RiscV/RiscV.cpp                    | 18 ++++++++++--------
 3 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/src/DebugToolDrivers/TargetInterfaces/RiscV/RiscVDebugInterface.hpp b/src/DebugToolDrivers/TargetInterfaces/RiscV/RiscVDebugInterface.hpp
index 189f056f..0a5682a8 100644
--- a/src/DebugToolDrivers/TargetInterfaces/RiscV/RiscVDebugInterface.hpp
+++ b/src/DebugToolDrivers/TargetInterfaces/RiscV/RiscVDebugInterface.hpp
@@ -3,6 +3,8 @@
 #include <cstdint>
 
 #include "src/Targets/RiscV/DebugModule/DebugModule.hpp"
+#include "src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp"
+
 #include "src/Targets/RiscV/TargetParameters.hpp"
 
 namespace DebugToolDrivers::TargetInterfaces::RiscV
@@ -63,6 +65,12 @@ namespace DebugToolDrivers::TargetInterfaces::RiscV
             Targets::RiscV::DebugModule::RegisterAddress address
         ) = 0;
 
+        Targets::RiscV::DebugModule::RegisterValue readDebugModuleRegister(
+            Targets::RiscV::DebugModule::Registers::RegisterAddress address
+        ) {
+            return this->readDebugModuleRegister(static_cast<Targets::RiscV::DebugModule::RegisterAddress>(address));
+        };
+
         /**
          * Should write a value to a debug module register.
          *
@@ -76,5 +84,15 @@ namespace DebugToolDrivers::TargetInterfaces::RiscV
             Targets::RiscV::DebugModule::RegisterAddress address,
             Targets::RiscV::DebugModule::RegisterValue value
         ) = 0;
+
+        void writeDebugModuleRegister(
+            Targets::RiscV::DebugModule::Registers::RegisterAddress address,
+            Targets::RiscV::DebugModule::RegisterValue value
+        ) {
+            return this->writeDebugModuleRegister(
+                static_cast<Targets::RiscV::DebugModule::RegisterAddress>(address),
+                value
+            );
+        };
     };
 }
diff --git a/src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp b/src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp
index 225cfcd8..f03cf233 100644
--- a/src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp
+++ b/src/Targets/RiscV/DebugModule/Registers/RegisterAddresses.hpp
@@ -2,9 +2,11 @@
 
 #include <cstdint>
 
+#include "src/Targets/RiscV/DebugModule/DebugModule.hpp"
+
 namespace Targets::RiscV::DebugModule::Registers
 {
-    enum RegisterAddresses: std::uint8_t
+    enum class RegisterAddress: ::Targets::RiscV::DebugModule::RegisterAddress
     {
         ABSTRACT_DATA_0 = 0x04,
         CONTROL_REGISTER = 0x10,
diff --git a/src/Targets/RiscV/RiscV.cpp b/src/Targets/RiscV/RiscV.cpp
index 32eb1bfd..17deda0f 100644
--- a/src/Targets/RiscV/RiscV.cpp
+++ b/src/Targets/RiscV/RiscV.cpp
@@ -18,7 +18,7 @@ namespace Targets::RiscV
     using Registers::RegisterNumber;
     using Registers::DebugControlStatusRegister;
 
-    using DebugModule::Registers::RegisterAddresses;
+    using DebugModule::Registers::RegisterAddress;
     using DebugModule::Registers::ControlRegister;
     using DebugModule::Registers::StatusRegister;
     using DebugModule::Registers::AbstractControlStatusRegister;
@@ -301,17 +301,19 @@ namespace Targets::RiscV
 
     ControlRegister RiscV::readDebugModuleControlRegister() {
         return ControlRegister(
-            this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::CONTROL_REGISTER)
+            this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::CONTROL_REGISTER)
         );
     }
 
     StatusRegister RiscV::readDebugModuleStatusRegister() {
-        return StatusRegister(this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::STATUS_REGISTER));
+        return StatusRegister(
+            this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::STATUS_REGISTER)
+        );
     }
 
     AbstractControlStatusRegister RiscV::readDebugModuleAbstractControlStatusRegister() {
         return AbstractControlStatusRegister(
-            this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::ABSTRACT_CONTROL_STATUS_REGISTER)
+            this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_CONTROL_STATUS_REGISTER)
         );
     }
 
@@ -335,7 +337,7 @@ namespace Targets::RiscV
 
         this->executeAbstractCommand(command);
 
-        return this->riscVDebugInterface->readDebugModuleRegister(RegisterAddresses::ABSTRACT_DATA_0);
+        return this->riscVDebugInterface->readDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0);
     }
 
     void RiscV::writeRegister(Registers::RegisterNumber number, RegisterValue value) {
@@ -352,13 +354,13 @@ namespace Targets::RiscV
             RegisterAccessControlField::RegisterSize::SIZE_32
         ).value();
 
-        this->riscVDebugInterface->writeDebugModuleRegister(RegisterAddresses::ABSTRACT_DATA_0, value);
+        this->riscVDebugInterface->writeDebugModuleRegister(RegisterAddress::ABSTRACT_DATA_0, value);
         this->executeAbstractCommand(command);
     }
 
     void RiscV::writeDebugModuleControlRegister(const DebugModule::Registers::ControlRegister& controlRegister) {
         this->riscVDebugInterface->writeDebugModuleRegister(
-            RegisterAddresses::CONTROL_REGISTER,
+            RegisterAddress::CONTROL_REGISTER,
             controlRegister.value()
         );
     }
@@ -371,7 +373,7 @@ namespace Targets::RiscV
         const DebugModule::Registers::AbstractCommandRegister& abstractCommandRegister
     ) {
         this->riscVDebugInterface->writeDebugModuleRegister(
-            RegisterAddresses::ABSTRACT_COMMAND_REGISTER,
+            RegisterAddress::ABSTRACT_COMMAND_REGISTER,
             abstractCommandRegister.value()
         );