Tidied caption attributes in AVR8 TDFs
This commit is contained in:
@@ -376,10 +376,10 @@
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
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<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
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<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
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values="ANALOG_ADC_AUTO_TRIGGER2"/>
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@@ -578,7 +578,7 @@
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</register>
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<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
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mask="0xFF"/>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
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<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
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@@ -378,10 +378,10 @@
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
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<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
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<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
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values="ANALOG_ADC_AUTO_TRIGGER2"/>
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@@ -507,7 +507,7 @@
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</register>
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<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
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mask="0xFF"/>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
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<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
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@@ -518,7 +518,7 @@
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x20" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x20" size="2" mask="0xFFFF"/>
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<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x22" size="1">
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<bitfield caption="" mask="0x80" name="VDEN"/>
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<bitfield caption="" mask="0x40" name="VDPD"/>
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@@ -646,12 +646,12 @@
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<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
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<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
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</register>
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x6E" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x6C" size="2"
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x6E" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x6C" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x6A" size="2"
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x6A" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x68" size="2"
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x68" size="2"
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mask="0xFFFF"/>
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<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x67" size="1">
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<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
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@@ -687,7 +687,7 @@
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mask="0xFF"/>
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<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x38" size="1"
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mask="0xFF"/>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x3B" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x3B" size="1">
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<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
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@@ -879,7 +879,7 @@
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<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS0"/>
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<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE0"/>
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</register>
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<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x41" size="2" mask="0x0FFF"/>
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<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x41" size="2" mask="0x0FFF"/>
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</register-group>
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<register-group caption="USART" name="USART1">
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<register caption="USART I/O Data Register" name="UDR1" offset="0x73" size="1" mask="0xFF" ocd-rw=""/>
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@@ -915,7 +915,7 @@
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<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS1"/>
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<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE1"/>
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</register>
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<register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x74" size="2" mask="0x0FFF"/>
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<register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x74" size="2" mask="0x0FFF"/>
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</register-group>
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<value-group caption="" name="COMM_UPM_PARITY_MODE">
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<value caption="Disabled" name="VAL_0x00" value="0x00"/>
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@@ -660,12 +660,12 @@
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<bitfield caption="Timer/Counter1 Output Compare U-pin Enable for Channel A" mask="0x01"
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name="OC1AU"/>
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</register>
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
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<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
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mask="0xFFFF"/>
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</register-group>
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<value-group caption="" name="CLK_SEL_3BIT_EXT">
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@@ -705,7 +705,7 @@
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</module>
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<module caption="EEPROM" name="EEPROM">
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<register-group caption="EEPROM" name="EEPROM">
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<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
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<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
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<register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
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<register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
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<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
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@@ -757,15 +757,15 @@
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<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
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<bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
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<register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
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ocd-rw="R">
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<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
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<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
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<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)"
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@@ -877,7 +877,7 @@
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<bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
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</register>
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<register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x68" size="1">
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<bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
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<bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
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</register>
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<register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
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<bitfield caption="Pin Change Interrupt Flags" mask="0x03" name="PCIF"/>
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@@ -929,7 +929,7 @@
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<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
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<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
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</register>
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<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
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<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
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<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
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<bitfield caption="BOD Sleep" mask="0x40" name="BODS"/>
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<bitfield caption="BOD Sleep Enable" mask="0x20" name="BODSE"/>
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@@ -499,7 +499,7 @@
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mask="0xFF"/>
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<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
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mask="0xFF"/>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
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@@ -554,12 +554,12 @@
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<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
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<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
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</register>
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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mask="0xFFFF"/>
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</register-group>
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<value-group caption="" name="CLK_SEL_3BIT_EXT">
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@@ -505,7 +505,7 @@
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mask="0xFF"/>
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<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
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mask="0xFF"/>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
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@@ -560,12 +560,12 @@
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<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
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<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
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</register>
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
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<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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mask="0xFFFF"/>
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</register-group>
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<value-group caption="" name="CLK_SEL_3BIT_EXT">
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@@ -479,10 +479,10 @@
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
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<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
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<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
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<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
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@@ -566,7 +566,7 @@
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</module>
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<module caption="EEPROM" name="EEPROM">
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<register-group caption="EEPROM" name="EEPROM">
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<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
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<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
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<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
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<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
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<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
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@@ -621,7 +621,7 @@
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<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
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<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
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</register>
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
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<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
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<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
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<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
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@@ -685,12 +685,12 @@
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<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
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<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
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</register>
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
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<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
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<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
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mask="0xFFFF"/>
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
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mask="0xFFFF"/>
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</register-group>
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<value-group caption="" name="CLK_SEL_3BIT_EXT">
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@@ -545,10 +545,10 @@
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<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
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<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
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<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
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values="ANALOG_ADC_PRESCALER"/>
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</register>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
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<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
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<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
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<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
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@@ -639,7 +639,7 @@
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</module>
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<module caption="EEPROM" name="EEPROM">
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<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -694,7 +694,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -758,12 +758,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -546,10 +546,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Input Polarity Mode" mask="0x20" name="IPR"/>
|
||||
@@ -637,7 +637,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -691,7 +691,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x08" name="OCF0B"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
|
||||
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
||||
|
||||
@@ -575,7 +575,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -678,7 +678,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -735,7 +735,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
|
||||
@@ -511,7 +511,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -614,7 +614,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -671,7 +671,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
|
||||
@@ -505,7 +505,7 @@
|
||||
mask="0xFF"/>
|
||||
<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
|
||||
mask="0xFF"/>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
||||
@@ -560,12 +560,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -522,7 +522,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -739,10 +739,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Boost Regulator Status Bit" mask="0x80" name="BVRON"/>
|
||||
<bitfield caption="Analog Comparator Multiplexer Enable" mask="0x40" name="ACME"/>
|
||||
|
||||
@@ -479,10 +479,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
|
||||
@@ -566,7 +566,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -621,7 +621,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -685,12 +685,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -596,7 +596,7 @@
|
||||
<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS1"/>
|
||||
<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE1"/>
|
||||
</register>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x91" size="2" mask="0x0FFF"/>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x91" size="2" mask="0x0FFF"/>
|
||||
</register-group>
|
||||
<register-group caption="USART" name="USART0">
|
||||
<register caption="USART I/O Data Register" name="UDR0" offset="0x80" size="1" mask="0xFF" ocd-rw=""/>
|
||||
@@ -632,7 +632,7 @@
|
||||
<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS0"/>
|
||||
<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE0"/>
|
||||
</register>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x81" size="2" mask="0x0FFF"/>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x81" size="2" mask="0x0FFF"/>
|
||||
<register caption="Remap Port Pins" name="REMAP" offset="0x65" size="1">
|
||||
<bitfield caption="USART0 Pin Mapping" mask="0x01" name="U0MAP"/>
|
||||
</register>
|
||||
@@ -731,7 +731,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x24" size="1">
|
||||
<bitfield caption="" mask="0x08" name="ADLAR"/>
|
||||
<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
|
||||
@@ -826,7 +826,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -874,12 +874,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -917,12 +917,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC2A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC2B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
|
||||
<register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
|
||||
<register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
|
||||
<register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -955,7 +955,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
|
||||
@@ -543,10 +543,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
|
||||
@@ -637,7 +637,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -692,7 +692,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -756,12 +756,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -575,7 +575,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -678,7 +678,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -735,7 +735,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
@@ -889,7 +889,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
|
||||
<bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
|
||||
|
||||
@@ -507,7 +507,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -610,7 +610,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -667,7 +667,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
@@ -821,7 +821,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="BOD Sleep" mask="0x80" name="BODS"/>
|
||||
<bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
|
||||
|
||||
@@ -528,12 +528,12 @@
|
||||
<bitfield caption="" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -786,14 +786,14 @@
|
||||
<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
|
||||
<bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1">
|
||||
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
|
||||
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
|
||||
@@ -888,7 +888,7 @@
|
||||
<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1"
|
||||
mask="0xFF"/>
|
||||
<register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
|
||||
<bitfield caption="Clear Timer on Compare Match" mask="0x08" name="CTC0"/>
|
||||
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
|
||||
</register>
|
||||
|
||||
@@ -618,7 +618,7 @@
|
||||
<bitfield caption="" mask="0x08" name="WGM02"/>
|
||||
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
|
||||
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
||||
@@ -685,12 +685,12 @@
|
||||
<bitfield caption="" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -753,7 +753,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
|
||||
<bitfield caption="" mask="0x08" name="ADLAR"/>
|
||||
<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
|
||||
@@ -997,7 +997,7 @@
|
||||
<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS"/>
|
||||
<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE"/>
|
||||
</register>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR" offset="0xC4" size="2" mask="0x0FFF"/>
|
||||
<register caption="USART Baud Rate Register Bytes" name="UBRR" offset="0xC4" size="2" mask="0x0FFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="COMM_USART_MODE">
|
||||
<value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
|
||||
|
||||
@@ -479,10 +479,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
|
||||
@@ -566,7 +566,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -621,7 +621,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -685,12 +685,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -731,7 +731,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x24" size="1">
|
||||
<bitfield caption="" mask="0x08" name="ADLAR"/>
|
||||
<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
|
||||
@@ -826,7 +826,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -874,12 +874,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -917,12 +917,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC2A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC2B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
|
||||
<register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
|
||||
<register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
|
||||
<register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -955,7 +955,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
|
||||
@@ -539,10 +539,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
|
||||
@@ -633,7 +633,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -688,7 +688,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
|
||||
<bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
|
||||
@@ -752,12 +752,12 @@
|
||||
<bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
|
||||
@@ -528,10 +528,10 @@
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Input Polarity Mode" mask="0x20" name="IPR"/>
|
||||
@@ -619,7 +619,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -673,7 +673,7 @@
|
||||
<bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x08" name="OCF0B"/>
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
|
||||
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
|
||||
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
|
||||
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
||||
@@ -805,7 +805,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
|
||||
<bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
|
||||
|
||||
@@ -577,7 +577,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -680,7 +680,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -737,7 +737,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
@@ -918,7 +918,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
|
||||
<bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
|
||||
|
||||
@@ -509,7 +509,7 @@
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
|
||||
<bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
|
||||
<bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
|
||||
@@ -612,7 +612,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -669,7 +669,7 @@
|
||||
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
|
||||
<bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
|
||||
<bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
|
||||
<bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
|
||||
<bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
|
||||
@@ -850,7 +850,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="BOD Sleep" mask="0x80" name="BODS"/>
|
||||
<bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
|
||||
|
||||
@@ -587,7 +587,7 @@
|
||||
<bitfield caption="Enable External Clock Input" mask="0x40" name="EXCLK"/>
|
||||
<bitfield caption="Asynchronous Timer/Counter0" mask="0x20" name="AS0"/>
|
||||
<bitfield caption="Timer/Counter0 Update Busy" mask="0x10" name="TCN0UB"/>
|
||||
<bitfield caption="Output Compare Register 0A Update Busy" mask="0x08" name="OCR0AUB"/>
|
||||
<bitfield caption="Output Compare Register 0A Update Busy" mask="0x08" name="OCR0AUB"/>
|
||||
<bitfield caption="Timer/Counter0 Control Register A Update Busy" mask="0x02" name="TCR0AUB"/>
|
||||
<bitfield caption="Timer/Counter0 Control Register B Update Busy" mask="0x01" name="TCR0BUB"/>
|
||||
</register>
|
||||
@@ -659,12 +659,12 @@
|
||||
<bitfield caption="Timer/Counter1 Output Compare U-pin Enable for Channel A" mask="0x01"
|
||||
name="OC1AU"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
mask="0xFFFF"/>
|
||||
</register-group>
|
||||
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
||||
@@ -704,7 +704,7 @@
|
||||
</module>
|
||||
<module caption="EEPROM" name="EEPROM">
|
||||
<register-group caption="EEPROM" name="EEPROM">
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
|
||||
<register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
|
||||
<register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
|
||||
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
||||
@@ -756,15 +756,15 @@
|
||||
<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
|
||||
<bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
|
||||
ocd-rw="R">
|
||||
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
|
||||
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)"
|
||||
@@ -876,7 +876,7 @@
|
||||
<bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
|
||||
</register>
|
||||
<register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x68" size="1">
|
||||
<bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
|
||||
<bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
|
||||
</register>
|
||||
<register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
|
||||
<bitfield caption="Pin Change Interrupt Flags" mask="0x03" name="PCIF"/>
|
||||
@@ -928,7 +928,7 @@
|
||||
<bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
|
||||
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
||||
</register>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
|
||||
<register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
|
||||
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
||||
<bitfield caption="BOD Sleep" mask="0x40" name="BODS"/>
|
||||
<bitfield caption="BOD Sleep Enable" mask="0x20" name="BODSE"/>
|
||||
|
||||
@@ -528,12 +528,12 @@
|
||||
<bitfield caption="" mask="0x80" name="FOC1A"/>
|
||||
<bitfield caption="" mask="0x40" name="FOC1B"/>
|
||||
</register>
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
||||
mask="0xFFFF"/>
|
||||
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
||||
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
||||
@@ -694,14 +694,14 @@
|
||||
<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
|
||||
<bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
|
||||
</register>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
||||
<register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1">
|
||||
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
|
||||
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
||||
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
||||
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
||||
values="ANALOG_ADC_PRESCALER"/>
|
||||
</register>
|
||||
<register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
|
||||
@@ -796,7 +796,7 @@
|
||||
<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1"
|
||||
mask="0xFF"/>
|
||||
<register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
|
||||
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
|
||||
<bitfield caption="Clear Timer on Compare Match" mask="0x08" name="CTC0"/>
|
||||
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
|
||||
</register>
|
||||
|
||||
Reference in New Issue
Block a user