From 8b74b3684259b55adf6a0425f20ce5e632211c24 Mon Sep 17 00:00:00 2001
From: Nav <nav@navnav.me>
Date: Fri, 17 Sep 2021 22:44:36 +0100
Subject: [PATCH] Tidied caption attributes in AVR8 TDFs

---
 .../AVR8/MEGA/AT90CAN128.xml                  | 24 ++++----
 .../AVR8/MEGA/AT90CAN32.xml                   | 24 ++++----
 .../AVR8/MEGA/AT90CAN64.xml                   | 22 ++++----
 .../AVR8/MEGA/AT90PWM1.xml                    | 16 +++---
 .../AVR8/MEGA/AT90PWM161.xml                  | 18 +++---
 .../AVR8/MEGA/AT90PWM216.xml                  |  8 +--
 .../AVR8/MEGA/AT90PWM2B.xml                   |  8 +--
 .../AVR8/MEGA/AT90PWM316.xml                  | 16 +++---
 .../AVR8/MEGA/AT90PWM3B.xml                   | 16 +++---
 .../AVR8/MEGA/AT90PWM81.xml                   |  8 +--
 .../AVR8/MEGA/AT90USB1286.xml                 | 26 ++++-----
 .../AVR8/MEGA/AT90USB1287.xml                 | 26 ++++-----
 .../AVR8/MEGA/AT90USB162.xml                  | 14 ++---
 .../AVR8/MEGA/AT90USB646.xml                  | 28 +++++-----
 .../AVR8/MEGA/AT90USB647.xml                  | 28 +++++-----
 .../AVR8/MEGA/AT90USB82.xml                   | 14 ++---
 .../AVR8/MEGA/ATMEGA128.xml                   | 28 +++++-----
 .../AVR8/MEGA/ATMEGA1280.xml                  | 56 +++++++++----------
 .../AVR8/MEGA/ATMEGA1281.xml                  | 52 ++++++++---------
 .../AVR8/MEGA/ATMEGA1284.xml                  | 28 +++++-----
 .../AVR8/MEGA/ATMEGA1284RFR2.xml              | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA128A.xml                  | 28 +++++-----
 .../AVR8/MEGA/ATMEGA128RFA1.xml               | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA128RFR2.xml               | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA16.xml                    | 12 ++--
 .../AVR8/MEGA/ATMEGA162.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA164A.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA164P.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA164PA.xml                 | 18 +++---
 .../AVR8/MEGA/ATMEGA165A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA165P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA165PA.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA168.xml                   | 20 +++----
 .../AVR8/MEGA/ATMEGA168A.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA168P.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA168PA.xml                 | 20 +++----
 .../AVR8/MEGA/ATMEGA168PB.xml                 | 18 +++---
 .../AVR8/MEGA/ATMEGA169A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA169P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA169PA.xml                 |  2 +-
 .../AVR8/MEGA/ATMEGA16M1.xml                  | 14 ++---
 .../AVR8/MEGA/ATMEGA16U2.xml                  |  2 +-
 .../AVR8/MEGA/ATMEGA16U4.xml                  | 12 ++--
 .../AVR8/MEGA/ATMEGA2560.xml                  | 54 +++++++++---------
 .../AVR8/MEGA/ATMEGA2561.xml                  | 52 ++++++++---------
 .../AVR8/MEGA/ATMEGA2564RFR2.xml              | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA256RFR2.xml               | 52 ++++++++---------
 .../AVR8/MEGA/ATMEGA32.xml                    | 14 ++---
 .../AVR8/MEGA/ATMEGA324A.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA324P.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA324PA.xml                 |  8 +--
 .../AVR8/MEGA/ATMEGA324PB.xml                 | 20 +++----
 .../AVR8/MEGA/ATMEGA325.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA3250.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA3250A.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA3250P.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA3250PA.xml                | 16 +++---
 .../AVR8/MEGA/ATMEGA325A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA325P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA325PA.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA328.xml                   |  6 +-
 .../AVR8/MEGA/ATMEGA328P.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA329.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA3290.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA3290A.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA3290P.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA3290PA.xml                | 16 +++---
 .../AVR8/MEGA/ATMEGA329A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA329P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA329PA.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA32A.xml                   | 14 ++---
 .../AVR8/MEGA/ATMEGA32C1.xml                  | 14 ++---
 .../AVR8/MEGA/ATMEGA32M1.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA32U2.xml                  | 14 ++---
 .../AVR8/MEGA/ATMEGA32U4.xml                  | 28 +++++-----
 .../AVR8/MEGA/ATMEGA406.xml                   |  6 +-
 .../AVR8/MEGA/ATMEGA48.xml                    | 16 +++---
 .../AVR8/MEGA/ATMEGA48A.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA48P.xml                   | 18 +++---
 .../AVR8/MEGA/ATMEGA48PA.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA48PB.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA64.xml                    | 28 +++++-----
 .../AVR8/MEGA/ATMEGA640.xml                   | 54 +++++++++---------
 .../AVR8/MEGA/ATMEGA644.xml                   | 18 +++---
 .../AVR8/MEGA/ATMEGA644A.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA644P.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA644PA.xml                 | 20 +++----
 .../AVR8/MEGA/ATMEGA644RFR2.xml               | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA645.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA6450.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA6450A.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA6450P.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA645A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA645P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA649.xml                   | 16 +++---
 .../AVR8/MEGA/ATMEGA6490.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA6490A.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA6490P.xml                 | 16 +++---
 .../AVR8/MEGA/ATMEGA649A.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA649P.xml                  | 16 +++---
 .../AVR8/MEGA/ATMEGA64A.xml                   | 28 +++++-----
 .../AVR8/MEGA/ATMEGA64C1.xml                  | 24 ++++----
 .../AVR8/MEGA/ATMEGA64M1.xml                  | 18 +++---
 .../AVR8/MEGA/ATMEGA64RFR2.xml                | 50 ++++++++---------
 .../AVR8/MEGA/ATMEGA88.xml                    | 20 +++----
 .../AVR8/MEGA/ATMEGA88A.xml                   | 20 +++----
 .../AVR8/MEGA/ATMEGA88P.xml                   | 20 +++----
 .../AVR8/MEGA/ATMEGA88PA.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA88PB.xml                  | 20 +++----
 .../AVR8/MEGA/ATMEGA8U2.xml                   | 14 ++---
 .../AVR8/TINY/ATTINY13.xml                    |  6 +-
 .../AVR8/TINY/ATTINY13A.xml                   |  6 +-
 .../AVR8/TINY/ATTINY1634.xml                  | 16 +++---
 .../AVR8/TINY/ATTINY167.xml                   | 20 +++----
 .../AVR8/TINY/ATTINY2313.xml                  | 10 ++--
 .../AVR8/TINY/ATTINY2313A.xml                 | 10 ++--
 .../AVR8/TINY/ATTINY24.xml                    | 16 +++---
 .../AVR8/TINY/ATTINY24A.xml                   | 16 +++---
 .../AVR8/TINY/ATTINY25.xml                    |  8 +--
 .../AVR8/TINY/ATTINY261.xml                   |  6 +-
 .../AVR8/TINY/ATTINY261A.xml                  |  6 +-
 .../AVR8/TINY/ATTINY4313.xml                  | 10 ++--
 .../AVR8/TINY/ATTINY43U.xml                   |  6 +-
 .../AVR8/TINY/ATTINY44.xml                    | 16 +++---
 .../AVR8/TINY/ATTINY441.xml                   | 26 ++++-----
 .../AVR8/TINY/ATTINY44A.xml                   | 16 +++---
 .../AVR8/TINY/ATTINY461.xml                   |  8 +--
 .../AVR8/TINY/ATTINY461A.xml                  |  8 +--
 .../AVR8/TINY/ATTINY48.xml                    | 16 +++---
 .../AVR8/TINY/ATTINY828.xml                   | 14 ++---
 .../AVR8/TINY/ATTINY84.xml                    | 16 +++---
 .../AVR8/TINY/ATTINY841.xml                   | 22 ++++----
 .../AVR8/TINY/ATTINY84A.xml                   | 16 +++---
 .../AVR8/TINY/ATTINY85.xml                    | 10 ++--
 .../AVR8/TINY/ATTINY861.xml                   |  8 +--
 .../AVR8/TINY/ATTINY861A.xml                  |  8 +--
 .../AVR8/TINY/ATTINY87.xml                    | 22 ++++----
 .../AVR8/TINY/ATTINY88.xml                    | 16 +++---
 .../AVR8/XMEGA/ATXMEGA128A1.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA128A1U.xml              |  4 +-
 .../AVR8/XMEGA/ATXMEGA128A3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA128A3U.xml              |  4 +-
 .../AVR8/XMEGA/ATXMEGA128A4U.xml              |  4 +-
 .../AVR8/XMEGA/ATXMEGA128B1.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA128B3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA128C3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA128D3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA128D4.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA16A4.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA16A4U.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA16C4.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA16D4.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA16E5.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA192A3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA192A3U.xml              |  4 +-
 .../AVR8/XMEGA/ATXMEGA192C3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA192D3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA256A3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA256A3B.xml              |  2 +-
 .../AVR8/XMEGA/ATXMEGA256A3BU.xml             |  4 +-
 .../AVR8/XMEGA/ATXMEGA256A3U.xml              |  4 +-
 .../AVR8/XMEGA/ATXMEGA256C3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA256D3.xml               |  2 +-
 .../AVR8/XMEGA/ATXMEGA32A4.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA32A4U.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA32C3.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA32C4.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA32D3.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA32D4.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA32E5.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA384C3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA384D3.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA64A1.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA64A1U.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA64A3.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA64A3U.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA64A4U.xml               |  4 +-
 .../AVR8/XMEGA/ATXMEGA64B1.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA64B3.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA64C3.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA64D3.xml                |  2 +-
 .../AVR8/XMEGA/ATXMEGA64D4.xml                |  4 +-
 .../AVR8/XMEGA/ATXMEGA8E5.xml                 |  4 +-
 183 files changed, 1409 insertions(+), 1409 deletions(-)

diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
index e3297035..27e65a7a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
@@ -1118,14 +1118,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1165,14 +1165,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1286,10 +1286,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
index bd4a587b..468e84c4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
@@ -1094,14 +1094,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1141,14 +1141,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1262,10 +1262,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
index bf5c8c8f..3a5f728e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
@@ -1096,14 +1096,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1143,14 +1143,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1267,7 +1267,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
index 8db275ea..621db936 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
@@ -858,7 +858,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -935,11 +935,11 @@
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter1 Output Compare A Register" mask="0xFFFF" name="OCR1A"/>
                 </register>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter1 Output Compare B Register" mask="0xFFFF" name="OCR1B"/>
                 </register>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter Input Capture" mask="0xFFFF" name="ICR1"/>
                 </register>
@@ -972,9 +972,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1" mask="0x9F">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Start Conversion" mask="0x10" name="ADASCR"/>
@@ -1125,20 +1125,20 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bit" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
index 6684e5b9..acc5924d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
@@ -655,9 +655,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x4C" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x27" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Noise Canceller Disable" mask="0x40" name="ADNCDIS"/>
@@ -718,28 +718,28 @@
                 <register caption="Analog Comparator3 Control Register" name="AC3CON" offset="0x7F" size="1">
                     <bitfield caption="Analog Comparator3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"/>
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"/>
                     <bitfield caption="Analog Comparator 3 Alternate Output Enable" mask="0x08" name="AC3OEA"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x7D" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
                 </register>
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x7E" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x20" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
@@ -879,7 +879,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="None Volatile Busy Memory Busy" mask="0x80" name="NVMBSY"/>
@@ -1053,8 +1053,8 @@
                     <bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
                               values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x5A" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x5A" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x8C" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
index 54b9114c..570103db 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
@@ -621,13 +621,13 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bit" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0xAE" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -635,14 +635,14 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
index efd070a8..de5d9bd0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
@@ -640,13 +640,13 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bit" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0xAE" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -654,14 +654,14 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
index f8f19e79..f4338752 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
@@ -667,13 +667,13 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bit" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0xAE" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -681,14 +681,14 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
@@ -839,7 +839,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -920,7 +920,7 @@
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter1 Output Compare B Register" mask="0xFFFF" name="OCR1B"/>
                 </register>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -951,9 +951,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1" mask="0x8F">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Source Selection 3" mask="0x08" name="ADTS3"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
index ed72b59a..bccf4123 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
@@ -664,13 +664,13 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bit" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0xAE" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -678,14 +678,14 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
@@ -836,7 +836,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -909,10 +909,10 @@
                 <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF">
                     <bitfield caption="Timer/Counter1" mask="0xFFFF" name="TCNT1"/>
                 </register>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2">
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2">
                     <bitfield caption="Timer/Counter1 Output Compare A" mask="0xFFFF" name="OCR1A"/>
                 </register>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2">
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2">
                     <bitfield caption="Timer/Counter1 Output Compare B" mask="0xFFFF" name="OCR1B"/>
                 </register>
                 <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
@@ -948,7 +948,7 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
                 <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
                     <bitfield caption="ADC Data Register" mask="0xFFFF" name="ADC"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
index 33381cc7..9e1c8109 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
@@ -719,28 +719,28 @@
                 <register caption="Analog Comparator3 Control Register" name="AC3CON" offset="0x7F" size="1">
                     <bitfield caption="Analog Comparator3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"/>
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"/>
                     <bitfield caption="Analog Comparator 3 Alternate Output Enable" mask="0x08" name="AC3OEA"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x7D" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
                 </register>
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x7E" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x20" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
                     <bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
index 8e270eb5..bac35344 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
@@ -880,7 +880,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1029,7 +1029,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1139,14 +1139,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1186,14 +1186,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1296,7 +1296,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
index 50b58687..2e37d7c8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
@@ -889,7 +889,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1184,7 +1184,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1294,14 +1294,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1341,14 +1341,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1451,7 +1451,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
index fbfad2ee..dcb4af31 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
@@ -620,7 +620,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -674,14 +674,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -996,7 +996,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
         </module>
         <module caption="Watchdog Timer" name="WDT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
index ded3137b..2a296234 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
@@ -886,7 +886,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1181,7 +1181,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1291,14 +1291,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1338,14 +1338,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1445,10 +1445,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
index e4b3713a..a192ea71 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
@@ -886,7 +886,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1181,7 +1181,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1291,14 +1291,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1338,14 +1338,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1445,10 +1445,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
index 958ab252..90b2d8dc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
@@ -619,7 +619,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -673,14 +673,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -995,7 +995,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
         </module>
         <module caption="Watchdog Timer" name="WDT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
index 1c7cee85..062528ff 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
@@ -1051,7 +1051,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x0FFF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x0FFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1191,14 +1191,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x78" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x78" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -1241,14 +1241,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x86" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x86" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x84" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x84" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output compare Register C  Bytes" name="OCR3C" offset="0x82" size="2"
+                <register caption="Timer/Counter3 Output compare Register C Bytes" name="OCR3C" offset="0x82" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x80" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x80" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -1329,13 +1329,13 @@
                 <register caption="The ADC Control and Status register" name="ADCSRA" offset="0x26" size="1" ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Free Running Select" mask="0x20" name="ADFR"/>
+                    <bitfield caption="ADC Free Running Select" mask="0x20" name="ADFR"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="ANALOG_ADC_V_REF2">
                 <value caption="AREF, Internal Vref turned off" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
index 6b698afc..90c3f152 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
@@ -894,7 +894,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -925,7 +925,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART2">
                 <register caption="USART I/O Data Register" name="UDR2" offset="0xD6" size="1" mask="0xFF" ocd-rw=""/>
@@ -956,7 +956,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ2"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL2"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART3">
                 <register caption="USART I/O Data Register" name="UDR3" offset="0x136" size="1" mask="0xFF" ocd-rw=""/>
@@ -988,7 +988,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ3"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL3"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR3" offset="0x134" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR3" offset="0x134" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -1137,7 +1137,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1289,14 +1289,14 @@
                     <bitfield caption="Force Output Compare 5B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare 5C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1336,14 +1336,14 @@
                     <bitfield caption="Force Output Compare 4B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare 4C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1383,14 +1383,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1430,14 +1430,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1667,15 +1667,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF6"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
index 098e5e6e..773200af 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
@@ -782,7 +782,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -813,7 +813,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -942,7 +942,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1076,14 +1076,14 @@
                     <bitfield caption="Force Output Compare 5B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare 5C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1123,14 +1123,14 @@
                     <bitfield caption="Force Output Compare 4B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare 4C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1170,14 +1170,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1217,14 +1217,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1345,15 +1345,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF6"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
index e8707f41..016f52b1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
@@ -749,7 +749,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -780,7 +780,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -833,7 +833,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -899,12 +899,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -938,12 +938,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC3A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -1077,15 +1077,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
index e9aa0b95..6318e7fb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
@@ -710,7 +710,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -743,7 +743,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1177,14 +1177,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1229,14 +1229,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1281,14 +1281,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1333,14 +1333,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2375,7 +2375,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="Reserved" mask="0xC0" name="Res"/>
@@ -2487,14 +2487,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
index aff55ae2..adfd9a04 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
@@ -1030,7 +1030,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x0FFF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x0FFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1170,14 +1170,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x78" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x78" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -1220,14 +1220,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x86" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x86" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x84" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x84" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output compare Register C  Bytes" name="OCR3C" offset="0x82" size="2"
+                <register caption="Timer/Counter3 Output compare Register C Bytes" name="OCR3C" offset="0x82" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x80" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x80" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -1308,13 +1308,13 @@
                 <register caption="The ADC Control and Status register" name="ADCSRA" offset="0x26" size="1" ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Free Running Select" mask="0x20" name="ADFR"/>
+                    <bitfield caption="ADC Free Running Select" mask="0x20" name="ADFR"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="ANALOG_ADC_V_REF2">
                 <value caption="AREF, Internal Vref turned off" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
index 4de25932..56071757 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
@@ -644,7 +644,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -677,7 +677,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1115,14 +1115,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1167,14 +1167,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1219,14 +1219,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1271,14 +1271,14 @@
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                     <bitfield caption="Reserved" mask="0x1F" name="Res"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2064,7 +2064,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="Reserved" mask="0xC0" name="Res"/>
@@ -2174,14 +2174,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
index a67acf22..150575e5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
@@ -714,7 +714,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -747,7 +747,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1174,14 +1174,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1225,14 +1225,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1276,14 +1276,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1327,14 +1327,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2360,7 +2360,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE2"/>
@@ -2471,14 +2471,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
index a4649291..91e92630 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
@@ -704,12 +704,12 @@
                     <bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
                               values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -755,7 +755,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1021,7 +1021,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="Special Function IO Register" name="SFIOR" offset="0x50" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0xE0" name="ADTS"/>
                 </register>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
index 4b83d06e..9028cd15 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
@@ -599,12 +599,12 @@
                     <bitfield caption="Pulse Width Modulator Select Bits" mask="0x18" name="WGM1" lsb="2"/>
                     <bitfield caption="Clock Select1 bits" mask="0x07" name="CS1" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -636,12 +636,12 @@
                     <bitfield caption="Pulse Width Modulator Select Bits" mask="0x18" name="WGM3" lsb="2"/>
                     <bitfield caption="Clock Select3 bits" mask="0x07" name="CS3" values="CLK_SEL_3BIT_SWAPPED"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x86" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x86" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counte3 Output Compare Register B  Bytes" name="OCR3B" offset="0x84" size="2"
+                <register caption="Timer/Counte3 Output Compare Register B Bytes" name="OCR3B" offset="0x84" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x80" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x80" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
index 84d81afc..782aeaeb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
@@ -741,7 +741,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -772,7 +772,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -825,7 +825,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1015,15 +1015,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1159,12 +1159,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
index 8056a3cd..30247038 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
@@ -782,7 +782,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -835,7 +835,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1025,15 +1025,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1169,12 +1169,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
index e61c0b5f..7aae2811 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
@@ -747,7 +747,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -831,7 +831,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1021,15 +1021,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1165,12 +1165,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
index e24a4b41..9a880516 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
@@ -618,12 +618,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -723,7 +723,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -878,10 +878,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -957,7 +957,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
index a1d9b637..db6cd829 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
@@ -618,12 +618,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -723,7 +723,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -907,10 +907,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -986,7 +986,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
index 27e19db4..b708e58c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
@@ -618,12 +618,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -723,7 +723,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -878,10 +878,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -957,7 +957,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
index b3040595..498f8ecc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
@@ -660,7 +660,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -743,12 +743,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -830,15 +830,15 @@
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX"
                               values="ADC_MUX_SINGLE_NO_TEMP"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -950,7 +950,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1161,7 +1161,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
index 574f91e1..c296ecc7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
@@ -656,7 +656,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -739,12 +739,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -825,15 +825,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -946,7 +946,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1072,7 +1072,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
index 67093276..6a24e918 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
@@ -660,7 +660,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSRnB" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -743,12 +743,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -829,15 +829,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -950,7 +950,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1076,7 +1076,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
index 5d9e5a55..a51424fb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
@@ -662,7 +662,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -745,12 +745,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -831,15 +831,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -952,7 +952,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1078,7 +1078,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
index 7a4ed269..73f3214c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
@@ -761,12 +761,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -847,15 +847,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -976,7 +976,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1102,7 +1102,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
index 3b8b449e..b63b044a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
@@ -737,12 +737,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -842,7 +842,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1100,10 +1100,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1179,7 +1179,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
index 6281364f..e7eda24f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
@@ -739,12 +739,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -844,7 +844,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1131,10 +1131,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1210,7 +1210,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
index aead03d5..0feba858 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
@@ -741,7 +741,7 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF">
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF">
                     <bitfield caption="Timer/Counter1 bits" mask="0xFFFF" name="TCNT1"/>
                 </register>
                 <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
index 956b3742..0ccc69e5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
@@ -817,14 +817,14 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0x94" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bits" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bits" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator Clock Select" mask="0x08" name="ACCKSEL"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x95" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -832,21 +832,21 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x96" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator 3 Control Register" name="AC3CON" offset="0x97" size="1">
                     <bitfield caption="Analog Comparator 3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
@@ -1005,7 +1005,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode for Channel A" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode for Channel B" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1122,7 +1122,7 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
                 <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
                     <bitfield caption="ADC Data bits" mask="0xFFFF" name="ADC"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
index 53fb4523..143238e8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
@@ -685,7 +685,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
index ed53b254..64614ef4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
@@ -780,7 +780,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -853,7 +853,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -992,7 +992,7 @@
                 <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF">
                     <bitfield caption="Timer/Counter3 bits" mask="0xFFFF" name="TCNT3"/>
                 </register>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter3 Output Compare A bits" mask="0xFFFF" name="OCR3A"/>
                 </register>
@@ -1004,7 +1004,7 @@
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter3 Output Compare C bits" mask="0xFFFF" name="OCR3C"/>
                 </register>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF">
                     <bitfield caption="Timer/Counter3 Input Capture bits" mask="0xFFFF" name="ICR3"/>
                 </register>
@@ -1197,10 +1197,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
                     <bitfield caption="ADC Data Bits" mask="0x03FF" name="ADC"/>
                 </register>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
index a771c4ae..5e2595f3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
@@ -894,7 +894,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -925,7 +925,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART2">
                 <register caption="USART I/O Data Register" name="UDR2" offset="0xD6" size="1" mask="0xFF" ocd-rw=""/>
@@ -956,7 +956,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ2"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL2"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART3">
                 <register caption="USART I/O Data Register" name="UDR3" offset="0x136" size="1" mask="0xFF" ocd-rw=""/>
@@ -1137,7 +1137,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1289,14 +1289,14 @@
                     <bitfield caption="Force Output Compare 5B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare 5C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1336,14 +1336,14 @@
                     <bitfield caption="Force Output Compare 4B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare 4C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1383,14 +1383,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1430,14 +1430,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1667,15 +1667,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF6"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
index 7cf99304..041cafc6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
@@ -782,7 +782,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -813,7 +813,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -942,7 +942,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1094,14 +1094,14 @@
                     <bitfield caption="Force Output Compare 5B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare 5C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1141,14 +1141,14 @@
                     <bitfield caption="Force Output Compare 4B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare 4C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1188,14 +1188,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1235,14 +1235,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1472,15 +1472,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF6"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
index 2f665a65..296e2474 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
@@ -717,7 +717,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -750,7 +750,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1177,14 +1177,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1228,14 +1228,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1279,14 +1279,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1330,14 +1330,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2365,7 +2365,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE2"/>
@@ -2476,14 +2476,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
index 706b541f..65b68207 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
@@ -90,7 +90,7 @@
                 </instance>
             </module>
             <module name="PORT">
-                <instance name="MISSING_PORTA" caption="I/O Port" >
+                <instance name="MISSING_PORTA" caption="I/O Port">
                     <register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
                                     caption="I/O Port"/>
                 </instance>
@@ -721,7 +721,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -754,7 +754,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1181,14 +1181,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1232,14 +1232,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1283,14 +1283,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1334,14 +1334,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2367,7 +2367,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE2"/>
@@ -2478,14 +2478,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
index 3ced0d2f..17853003 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
@@ -267,7 +267,7 @@
         </peripherals>
         <interrupts>
             <interrupt index="0" name="RESET"
-                       caption="External Pin, Power-on Reset, Brown-out Reset  and Watchdog Reset"/>
+                       caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
             <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
             <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
             <interrupt index="3" name="INT2" caption="External Interrupt Request 2"/>
@@ -647,7 +647,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -813,12 +813,12 @@
                     <bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
                               values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -955,7 +955,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="Special Function IO Register" name="SFIOR" offset="0x50" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0xE0" name="ADTS"/>
                 </register>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
index bbb25113..ad225c25 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
@@ -739,7 +739,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -770,7 +770,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -823,7 +823,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1013,15 +1013,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1157,12 +1157,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
index 0b5e2bef..c44e3645 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
@@ -784,7 +784,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -837,7 +837,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1027,15 +1027,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1171,12 +1171,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
index 5963c7e6..c5ebbaa4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
@@ -835,7 +835,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1031,17 +1031,17 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
                     <bitfield caption="ADC Data bits" mask="0x03FF" name="ADC"/>
                 </register>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
index 6a263b5a..0ecbb93f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
@@ -886,7 +886,7 @@
                     <bitfield caption="Start Frame Detect Flag" mask="0x40" name="RXS"/>
                     <bitfield caption="Start Frame Detection Enable" mask="0x20" name="SFDE"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -922,7 +922,7 @@
                     <bitfield caption="Start Frame Detect Flag" mask="0x40" name="RXS"/>
                     <bitfield caption="Start Frame Detection Enable" mask="0x20" name="SFDE"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART2">
                 <register caption="USART I/O Data Register" name="UDR2" offset="0xD6" size="1" mask="0xFF" ocd-rw=""/>
@@ -958,7 +958,7 @@
                     <bitfield caption="Start Frame Detect Flag" mask="0x40" name="RXS"/>
                     <bitfield caption="Start Frame Detection Enable" mask="0x20" name="SFDE"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -1192,14 +1192,14 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1" ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1336,12 +1336,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
index 844b9392..855dd71e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -664,7 +664,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -792,7 +792,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -900,12 +900,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
index 283025f9..282bda2a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
@@ -647,12 +647,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -752,7 +752,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1024,10 +1024,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1103,7 +1103,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
index 7e46c20a..8ed33f98 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
@@ -647,12 +647,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -752,7 +752,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1024,10 +1024,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1103,7 +1103,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
index c5ea67ec..ea5fee07 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
@@ -647,12 +647,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -752,7 +752,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1026,10 +1026,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1105,7 +1105,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
index 5107d7ec..1db427e0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
@@ -647,12 +647,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -752,7 +752,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -944,10 +944,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1023,7 +1023,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
index c7e86d6b..44cda4a3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -664,7 +664,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -792,7 +792,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -900,12 +900,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
index 97770c8c..af6a02eb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -664,7 +664,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -792,7 +792,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -900,12 +900,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
index b6d6d76a..0608d5aa 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -664,7 +664,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -788,7 +788,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -896,12 +896,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
index aac95f46..1bd81c08 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
@@ -855,10 +855,10 @@
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -976,7 +976,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
index ade6fec0..3a18bb81 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
@@ -745,12 +745,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -831,15 +831,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -952,7 +952,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1162,7 +1162,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
index 5a0d122f..a7ce5687 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
@@ -735,12 +735,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -840,7 +840,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1176,10 +1176,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1255,7 +1255,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
index 0b937400..61490f43 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
@@ -653,12 +653,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -758,7 +758,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1114,10 +1114,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1193,7 +1193,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
index f73fd4b1..a0398e3a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
@@ -653,12 +653,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -758,7 +758,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1114,10 +1114,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1193,7 +1193,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
index 79629c30..139efa9f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
@@ -653,12 +653,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -758,7 +758,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1149,10 +1149,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1228,7 +1228,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
index ffc9a20f..169b9b4d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
@@ -653,12 +653,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -758,7 +758,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -950,10 +950,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1029,7 +1029,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
index b422c575..e6246e1c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
@@ -735,12 +735,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -840,7 +840,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1353,10 +1353,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1432,7 +1432,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
index 139ba22a..58a8f77b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
@@ -739,12 +739,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -844,7 +844,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1042,10 +1042,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1121,7 +1121,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
index 787072ae..e1c9c022 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
@@ -735,12 +735,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -840,7 +840,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1355,10 +1355,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -1434,7 +1434,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
index 33d0afb6..39b9d9bb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
@@ -250,7 +250,7 @@
         </peripherals>
         <interrupts>
             <interrupt index="0" name="RESET"
-                       caption="External Pin, Power-on Reset, Brown-out Reset  and Watchdog Reset"/>
+                       caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
             <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
             <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
             <interrupt index="3" name="INT2" caption="External Interrupt Request 2"/>
@@ -618,7 +618,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x03FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x03FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -784,12 +784,12 @@
                     <bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
                               values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -926,7 +926,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="Special Function IO Register" name="SFIOR" offset="0x50" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0xE0" name="ADTS"/>
                 </register>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
index 3dc94ac8..546dac02 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
@@ -800,14 +800,14 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0x94" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bits" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bits" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator Clock Select" mask="0x08" name="ACCKSEL"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x95" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -815,21 +815,21 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x96" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator 3 Control Register" name="AC3CON" offset="0x97" size="1">
                     <bitfield caption="Analog Comparator 3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
@@ -988,7 +988,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1104,7 +1104,7 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
                 <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
                     <bitfield caption="ADC Data bits" mask="0x03FF" name="ADC"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
index d2bfbdde..55da2c06 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
@@ -803,14 +803,14 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0x94" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bits" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bits" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator Clock Select" mask="0x08" name="ACCKSEL"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x95" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -818,21 +818,21 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x96" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator 3 Control Register" name="AC3CON" offset="0x97" size="1">
                     <bitfield caption="Analog Comparator 3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
@@ -991,7 +991,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode for Channel A" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode for Channel B" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1057,7 +1057,7 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Output Compare Register A" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Output Compare Register B" name="OCR1B" offset="0x8A" size="2"
@@ -1094,9 +1094,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="Current Source Enable" mask="0x40" name="ISRCEN"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
index 67e3436a..8d56c66b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
@@ -673,7 +673,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -727,14 +727,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1053,7 +1053,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
         </module>
         <module caption="Watchdog Timer" name="WDT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
index f6ea2cc1..9261cb33 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
@@ -776,7 +776,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -839,7 +839,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -963,14 +963,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1010,14 +1010,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1149,10 +1149,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x20" name="MUX5"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
index d700c1f5..9f331ccc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
@@ -324,7 +324,7 @@
                 <register caption="The VADC multiplexer Selection Register" name="VADMUX" offset="0x7C" size="1">
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="VADMUX"/>
                 </register>
-                <register caption="VADC Data Register  Bytes" name="VADC" offset="0x78" size="2" mask="0x0FFF"/>
+                <register caption="VADC Data Register Bytes" name="VADC" offset="0x78" size="2" mask="0x0FFF"/>
                 <register caption="The VADC Control and Status register" name="VADCSR" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="VADC Enable" mask="0x08" name="VADEN"/>
@@ -374,7 +374,7 @@
                     <bitfield caption="Clear Timer/Counter on Compare Match" mask="0x08" name="CTC1"/>
                     <bitfield caption="Clock Select1 bits" mask="0x07" name="CS1" values="CLK_SEL_3BIT"/>
                 </register>
-                <register caption="Timer Counter 1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer Counter 1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
                 <register caption="Output Compare Register 1A Low byte" name="OCR1AL" offset="0x88" size="1"
                           mask="0xFF"/>
                 <register caption="Output Compare Register 1A High byte" name="OCR1AH" offset="0x89" size="1"
@@ -843,7 +843,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
index 6f229dae..307b1ea1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
@@ -722,12 +722,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -809,15 +809,15 @@
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX"
                               values="ADC_MUX_SINGLE_NO_TEMP"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -929,7 +929,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
index 3ab640a1..717397e2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
@@ -710,12 +710,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -796,15 +796,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -917,7 +917,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
index edc1ee10..891d945e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
@@ -635,7 +635,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -718,12 +718,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -804,15 +804,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -925,7 +925,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
index 3e5c2203..f49d460f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
@@ -635,7 +635,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -718,12 +718,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -804,15 +804,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -925,7 +925,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
index e0653f90..df808f72 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
@@ -732,12 +732,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -818,15 +818,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -947,7 +947,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
index e2114baf..de736a5c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
@@ -754,15 +754,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x26" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x8E" size="1">
@@ -1093,7 +1093,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1233,14 +1233,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x78" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x78" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -1283,14 +1283,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x86" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x86" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x84" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x84" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output compare Register C  Bytes" name="OCR3C" offset="0x82" size="2"
+                <register caption="Timer/Counter3 Output compare Register C Bytes" name="OCR3C" offset="0x82" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x80" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x80" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
index 63858640..e949bcc1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
@@ -894,7 +894,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -925,7 +925,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART2">
                 <register caption="USART I/O Data Register" name="UDR2" offset="0xD6" size="1" mask="0xFF" ocd-rw=""/>
@@ -956,7 +956,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ2"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL2"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR2" offset="0xD4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART3">
                 <register caption="USART I/O Data Register" name="UDR3" offset="0x136" size="1" mask="0xFF" ocd-rw=""/>
@@ -1137,7 +1137,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1289,14 +1289,14 @@
                     <bitfield caption="Force Output Compare 5B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare 5C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1336,14 +1336,14 @@
                     <bitfield caption="Force Output Compare 4B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare 4C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1383,14 +1383,14 @@
                     <bitfield caption="Force Output Compare 3B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare 3C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1430,14 +1430,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1660,15 +1660,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF6"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
index 5a79f72c..0956d154 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
@@ -730,7 +730,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -783,7 +783,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -973,15 +973,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1117,12 +1117,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
index cb8e1d07..56f2fa22 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
@@ -737,7 +737,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -768,7 +768,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -821,7 +821,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1011,15 +1011,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1155,12 +1155,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
index 7cbf380a..e8e5103e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
@@ -755,7 +755,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -786,7 +786,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -839,7 +839,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1029,15 +1029,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1173,12 +1173,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
index 2b991589..877283f8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
@@ -741,7 +741,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -772,7 +772,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
@@ -825,7 +825,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1015,15 +1015,15 @@
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"
                               values="ADC_MUX_DIFF"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -1159,12 +1159,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
index 9c9370d4..2d7e9f5b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
@@ -710,7 +710,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -743,7 +743,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1170,14 +1170,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1221,14 +1221,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1272,14 +1272,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1323,14 +1323,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2357,7 +2357,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE2"/>
@@ -2468,14 +2468,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
index c4611413..42b1d63a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -800,7 +800,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -957,12 +957,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1054,7 +1054,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
index b905d30b..ea504392 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
@@ -599,10 +599,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -748,7 +748,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -851,7 +851,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1018,12 +1018,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
index 9f517148..40bd4f39 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
@@ -599,10 +599,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -748,7 +748,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -851,7 +851,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1018,12 +1018,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
index 958e2353..464bdb01 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
@@ -599,10 +599,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -748,7 +748,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -851,7 +851,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1018,12 +1018,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
index 00e697ca..26760b93 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -801,7 +801,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -958,12 +958,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1055,7 +1055,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
index 18c3ffa9..0f41d3e0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
@@ -570,10 +570,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -803,7 +803,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -960,12 +960,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1057,7 +1057,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
index 8ed13b7c..0d1345ea 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
@@ -687,10 +687,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -836,7 +836,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -1041,7 +1041,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1149,12 +1149,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
index 06838ff9..fcce7e7e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
@@ -605,10 +605,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -754,7 +754,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -858,7 +858,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -976,12 +976,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
index 88228f3f..93405269 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
@@ -605,10 +605,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -754,7 +754,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -858,7 +858,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -976,12 +976,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
index 57aabff2..c536158d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
@@ -605,10 +605,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -754,7 +754,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -858,7 +858,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -976,12 +976,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
index 94a68b89..85624617 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
@@ -683,10 +683,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -832,7 +832,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -1037,7 +1037,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1145,12 +1145,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
index c4d64780..0fcfd1c8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
@@ -683,10 +683,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"/>
                 </register>
@@ -832,7 +832,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
@@ -1037,7 +1037,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1145,12 +1145,12 @@
                     <bitfield caption="Force Output Compare 1A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
index a8fc6b3e..27b228c4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
@@ -746,15 +746,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x26" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x8E" size="1">
@@ -1085,7 +1085,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Read/Write Access  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x07FF"/>
+                <register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x3E" size="2" mask="0x07FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
@@ -1225,14 +1225,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1C" offset="0x78" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1C" offset="0x78" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x46" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x46" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <register-group caption="Timer/Counter, 16-bit" name="TC3">
@@ -1275,14 +1275,14 @@
                     <bitfield caption="Force Output Compare for channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x86" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x88" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x86" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x84" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x84" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output compare Register C  Bytes" name="OCR3C" offset="0x82" size="2"
+                <register caption="Timer/Counter3 Output compare Register C Bytes" name="OCR3C" offset="0x82" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x80" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x80" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
index 3bcbd34c..995f8f9e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
@@ -774,14 +774,14 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0x94" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bits" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bits" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator Clock Select" mask="0x08" name="ACCKSEL"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x95" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -789,21 +789,21 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x96" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator 3 Control Register" name="AC3CON" offset="0x97" size="1">
                     <bitfield caption="Analog Comparator 3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
@@ -963,7 +963,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1029,12 +1029,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -1066,9 +1066,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="Current Source Enable" mask="0x40" name="ISRCEN"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
index a0f4a85c..3195a443 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
@@ -803,14 +803,14 @@
                 <register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0x94" size="1">
                     <bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
-                    <bitfield caption="Analog Comparator 0  Interrupt Select Bits" mask="0x30" name="AC0IS"/>
+                    <bitfield caption="Analog Comparator 0 Interrupt Select Bits" mask="0x30" name="AC0IS"/>
                     <bitfield caption="Analog Comparator Clock Select" mask="0x08" name="ACCKSEL"/>
                     <bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
                 </register>
                 <register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0x95" size="1">
                     <bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Select Bit" mask="0x30" name="AC1IS"
+                    <bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
                     <bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
@@ -818,21 +818,21 @@
                 <register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0x96" size="1">
                     <bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
-                    <bitfield caption="Analog Comparator 2  Interrupt Select Bit" mask="0x30" name="AC2IS"
+                    <bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
                 </register>
                 <register caption="Analog Comparator 3 Control Register" name="AC3CON" offset="0x97" size="1">
                     <bitfield caption="Analog Comparator 3 Enable Bit" mask="0x80" name="AC3EN"/>
                     <bitfield caption="Analog Comparator 3 Interrupt Enable Bit" mask="0x40" name="AC3IE"/>
-                    <bitfield caption="Analog Comparator 3  Interrupt Select Bit" mask="0x30" name="AC3IS"
+                    <bitfield caption="Analog Comparator 3 Interrupt Select Bit" mask="0x30" name="AC3IS"
                               values="ANALOG_COMP_INTERRUPT"/>
                     <bitfield caption="Analog Comparator 3 Multiplexer Register" mask="0x07" name="AC3M"/>
                 </register>
                 <register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
                     <bitfield caption="Analog Comparator 3 Interrupt Flag Bit" mask="0x80" name="AC3IF"/>
                     <bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
-                    <bitfield caption="Analog Comparator 1  Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
+                    <bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
                     <bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
                     <bitfield caption="Analog Comparator 3 Output Bit" mask="0x08" name="AC3O"/>
                     <bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
@@ -991,7 +991,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode for Channel A" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode for Channel B" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1057,7 +1057,7 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Output Compare Register A" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Output Compare Register B" name="OCR1B" offset="0x8A" size="2"
@@ -1094,9 +1094,9 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"/>
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
                     <bitfield caption="Current Source Enable" mask="0x40" name="ISRCEN"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
index 29e419ff..23b9ced3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
@@ -714,7 +714,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART0 Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
+                <register caption="USART0 Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0xFFFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART1 I/O Data Register" name="UDR1" offset="0xCE" size="1" mask="0xFF" ocd-rw=""/>
@@ -747,7 +747,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ1" values="USART_CHAR_SIZE_BITF"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL1" values="USART_CLK_POLARITY_BITF"/>
                 </register>
-                <register caption="USART1 Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
+                <register caption="USART1 Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT_MEGARF">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -1166,14 +1166,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC5B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC5C"/>
                 </register>
-                <register caption="Timer/Counter5  Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register A  Bytes" name="OCR5A" offset="0x128" size="2"
+                <register caption="Timer/Counter5 Bytes" name="TCNT5" offset="0x124" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter5 Output Compare Register A Bytes" name="OCR5A" offset="0x128" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register B  Bytes" name="OCR5B" offset="0x12A" size="2"
+                <register caption="Timer/Counter5 Output Compare Register B Bytes" name="OCR5B" offset="0x12A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Output Compare Register C  Bytes" name="OCR5C" offset="0x12C" size="2"
+                <register caption="Timer/Counter5 Output Compare Register C Bytes" name="OCR5C" offset="0x12C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter5 Input Capture Register  Bytes" name="ICR5" offset="0x126" size="2"
+                <register caption="Timer/Counter5 Input Capture Register Bytes" name="ICR5" offset="0x126" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter5 Interrupt Mask Register" name="TIMSK5" offset="0x73" size="1">
                     <bitfield caption="Timer/Counter5 Input Capture Interrupt Enable" mask="0x20" name="ICIE5"/>
@@ -1216,14 +1216,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC4B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC4C"/>
                 </register>
-                <register caption="Timer/Counter4  Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register A  Bytes" name="OCR4A" offset="0xA8" size="2"
+                <register caption="Timer/Counter4 Bytes" name="TCNT4" offset="0xA4" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter4 Output Compare Register A Bytes" name="OCR4A" offset="0xA8" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register B  Bytes" name="OCR4B" offset="0xAA" size="2"
+                <register caption="Timer/Counter4 Output Compare Register B Bytes" name="OCR4B" offset="0xAA" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Output Compare Register C  Bytes" name="OCR4C" offset="0xAC" size="2"
+                <register caption="Timer/Counter4 Output Compare Register C Bytes" name="OCR4C" offset="0xAC" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter4 Input Capture Register  Bytes" name="ICR4" offset="0xA6" size="2"
+                <register caption="Timer/Counter4 Input Capture Register Bytes" name="ICR4" offset="0xA6" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter4 Interrupt Mask Register" name="TIMSK4" offset="0x72" size="1">
                     <bitfield caption="Timer/Counter4 Input Capture Interrupt Enable" mask="0x20" name="ICIE4"/>
@@ -1266,14 +1266,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC3B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC3C"/>
                 </register>
-                <register caption="Timer/Counter3  Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register A  Bytes" name="OCR3A" offset="0x98" size="2"
+                <register caption="Timer/Counter3 Bytes" name="TCNT3" offset="0x94" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter3 Output Compare Register A Bytes" name="OCR3A" offset="0x98" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register B  Bytes" name="OCR3B" offset="0x9A" size="2"
+                <register caption="Timer/Counter3 Output Compare Register B Bytes" name="OCR3B" offset="0x9A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Output Compare Register C  Bytes" name="OCR3C" offset="0x9C" size="2"
+                <register caption="Timer/Counter3 Output Compare Register C Bytes" name="OCR3C" offset="0x9C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter3 Input Capture Register  Bytes" name="ICR3" offset="0x96" size="2"
+                <register caption="Timer/Counter3 Input Capture Register Bytes" name="ICR3" offset="0x96" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter3 Interrupt Mask Register" name="TIMSK3" offset="0x71" size="1">
                     <bitfield caption="Timer/Counter3 Input Capture Interrupt Enable" mask="0x20" name="ICIE3"/>
@@ -1316,14 +1316,14 @@
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare for Channel C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -2342,7 +2342,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0xFFFF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE2"/>
@@ -2451,14 +2451,14 @@
                     <bitfield caption="ADC Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status Register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
index a0bb574f..f6725bc9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
@@ -660,7 +660,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -743,12 +743,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -830,15 +830,15 @@
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX"
                               values="ADC_MUX_SINGLE_NO_TEMP"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -950,7 +950,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1161,7 +1161,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
index 4fc0e286..f26e1a60 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
@@ -656,7 +656,7 @@
                     <bitfield caption="Character Size" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -739,12 +739,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -825,15 +825,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -946,7 +946,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1072,7 +1072,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
index 6d6f7bfa..e2679e11 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
@@ -660,7 +660,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -743,12 +743,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -829,15 +829,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -950,7 +950,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1076,7 +1076,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
index 4f97b802..9fc3e4ce 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
@@ -664,7 +664,7 @@
                     <bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
                     <bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -747,12 +747,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -833,15 +833,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -954,7 +954,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1080,7 +1080,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
index a1f1153b..0bc39024 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
@@ -678,7 +678,7 @@
                     <bitfield caption="RX Start" mask="0x40" name="RXS"/>
                     <bitfield caption="Start Frame Detection Enable" mask="0x20" name="SFDE"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE_2BIT">
                 <value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -761,12 +761,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -847,15 +847,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -976,7 +976,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -1102,7 +1102,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
index c25b7991..5bd00e3e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
@@ -673,7 +673,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -727,14 +727,14 @@
                     <bitfield caption="Force Output Compare 1B" mask="0x40" name="FOC1B"/>
                     <bitfield caption="Force Output Compare 1C" mask="0x20" name="FOC1C"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register C  Bytes" name="OCR1C" offset="0x8C" size="2"
+                <register caption="Timer/Counter1 Output Compare Register C Bytes" name="OCR1C" offset="0x8C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="Timer/Counter1 Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
                     <bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
@@ -1053,7 +1053,7 @@
                     <bitfield caption="CTS Enable" mask="0x02" name="CTSEN"/>
                     <bitfield caption="RTS Enable" mask="0x01" name="RTSEN"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0xCC" size="2" mask="0x0FFF"/>
             </register-group>
         </module>
         <module caption="Watchdog Timer" name="WDT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
index 4e19fb7d..ca3b2865 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
@@ -376,10 +376,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
                               values="ANALOG_ADC_AUTO_TRIGGER2"/>
@@ -578,7 +578,7 @@
                 </register>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x4F" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
index 68196805..f34cb8d8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
@@ -378,10 +378,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
                               values="ANALOG_ADC_AUTO_TRIGGER2"/>
@@ -507,7 +507,7 @@
                 </register>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x4F" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4F" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
index 80750c09..35d610b5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
@@ -518,7 +518,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x20" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x20" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x22" size="1">
                     <bitfield caption="" mask="0x80" name="VDEN"/>
                     <bitfield caption="" mask="0x40" name="VDPD"/>
@@ -646,12 +646,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x6E" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x6C" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x6E" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x6C" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x6A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x6A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x68" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x68" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x67" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -687,7 +687,7 @@
                           mask="0xFF"/>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x38" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x3B" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x3B" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -879,7 +879,7 @@
                     <bitfield caption="USART RX Start Flag" mask="0x40" name="RXS0"/>
                     <bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0x41" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x41" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART1">
                 <register caption="USART I/O Data Register" name="UDR1" offset="0x73" size="1" mask="0xFF" ocd-rw=""/>
@@ -915,7 +915,7 @@
                     <bitfield caption="USART RX Start Flag" mask="0x40" name="RXS1"/>
                     <bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0x74" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x74" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_UPM_PARITY_MODE">
                 <value caption="Disabled" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
index eaaa213a..d3fcfebb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
@@ -660,12 +660,12 @@
                     <bitfield caption="Timer/Counter1 Output Compare U-pin Enable for Channel A" mask="0x01"
                               name="OC1AU"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -705,7 +705,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -757,15 +757,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)"
@@ -877,7 +877,7 @@
                     <bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
                 </register>
                 <register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x68" size="1">
-                    <bitfield caption="Pin Change Interrupt Enable  on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
+                    <bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
                 </register>
                 <register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
                     <bitfield caption="Pin Change Interrupt Flags" mask="0x03" name="PCIF"/>
@@ -929,7 +929,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="BOD Sleep" mask="0x40" name="BODS"/>
                     <bitfield caption="BOD Sleep Enable" mask="0x20" name="BODSE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
index 3e610bd6..bcdcd1cc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
@@ -499,7 +499,7 @@
                           mask="0xFF"/>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -554,12 +554,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
index 2284c05e..a9bb37d3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
@@ -505,7 +505,7 @@
                           mask="0xFF"/>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -560,12 +560,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
index 49f3aa39..9cfe1783 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
@@ -479,10 +479,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -566,7 +566,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -621,7 +621,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -685,12 +685,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
index e1c6f8d7..38ebd099 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
@@ -545,10 +545,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -639,7 +639,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -694,7 +694,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -758,12 +758,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
index e0ef0480..220a16c9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
@@ -546,10 +546,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Input Polarity Mode" mask="0x20" name="IPR"/>
@@ -637,7 +637,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -691,7 +691,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x08" name="OCF0B"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x4A" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
index a060e4e8..4a39ccd5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
@@ -575,7 +575,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -678,7 +678,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -735,7 +735,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
index 9f780e82..f904a2c7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
@@ -511,7 +511,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -614,7 +614,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -671,7 +671,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
index 6f00ac47..b1c3c38a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
@@ -505,7 +505,7 @@
                           mask="0xFF"/>
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x56" size="1"
                           mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -560,12 +560,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
index de3fa446..a98fdfce 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
@@ -522,7 +522,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -739,10 +739,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Boost Regulator Status Bit" mask="0x80" name="BVRON"/>
                     <bitfield caption="Analog Comparator Multiplexer Enable" mask="0x40" name="ACME"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
index f45d09f4..94c57ca8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
@@ -479,10 +479,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -566,7 +566,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -621,7 +621,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -685,12 +685,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
index 0cb282c0..e4d5bb21 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
@@ -596,7 +596,7 @@
                     <bitfield caption="USART RX Start Flag" mask="0x40" name="RXS1"/>
                     <bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE1"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR1" offset="0x91" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR1" offset="0x91" size="2" mask="0x0FFF"/>
             </register-group>
             <register-group caption="USART" name="USART0">
                 <register caption="USART I/O Data Register" name="UDR0" offset="0x80" size="1" mask="0xFF" ocd-rw=""/>
@@ -632,7 +632,7 @@
                     <bitfield caption="USART RX Start Flag" mask="0x40" name="RXS0"/>
                     <bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE0"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR0" offset="0x81" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0x81" size="2" mask="0x0FFF"/>
                 <register caption="Remap Port Pins" name="REMAP" offset="0x65" size="1">
                     <bitfield caption="USART0 Pin Mapping" mask="0x01" name="U0MAP"/>
                 </register>
@@ -731,7 +731,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x24" size="1">
                     <bitfield caption="" mask="0x08" name="ADLAR"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
@@ -826,7 +826,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -874,12 +874,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -917,12 +917,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC2A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC2B"/>
                 </register>
-                <register caption="Timer/Counter2  Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Output Compare Register A  Bytes" name="OCR2A" offset="0xC4" size="2"
+                <register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Output Compare Register B  Bytes" name="OCR2B" offset="0xC2" size="2"
+                <register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Input Capture Register  Bytes" name="ICR2" offset="0xC0" size="2"
+                <register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -955,7 +955,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
index fa3be70f..c62e8bb8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
@@ -543,10 +543,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -637,7 +637,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -692,7 +692,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -756,12 +756,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
index 9163da39..756cb238 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
@@ -575,7 +575,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -678,7 +678,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -735,7 +735,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
@@ -889,7 +889,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
                     <bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
index a7787d78..daff701b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
@@ -507,7 +507,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -610,7 +610,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -667,7 +667,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
@@ -821,7 +821,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x01FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="BOD Sleep" mask="0x80" name="BODS"/>
                     <bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
index 9f0afa70..f0766cdf 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
@@ -528,12 +528,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -786,14 +786,14 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -888,7 +888,7 @@
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1"
                           mask="0xFF"/>
                 <register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x45" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
                     <bitfield caption="Clear Timer on Compare Match" mask="0x08" name="CTC0"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
index c3594b54..e3d6d671 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
@@ -618,7 +618,7 @@
                     <bitfield caption="" mask="0x08" name="WGM02"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x44" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -685,12 +685,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -753,7 +753,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
                     <bitfield caption="" mask="0x08" name="ADLAR"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
@@ -997,7 +997,7 @@
                     <bitfield caption="USART RX Start Flag" mask="0x40" name="RXS"/>
                     <bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE"/>
                 </register>
-                <register caption="USART Baud Rate Register  Bytes" name="UBRR" offset="0xC4" size="2" mask="0x0FFF"/>
+                <register caption="USART Baud Rate Register Bytes" name="UBRR" offset="0xC4" size="2" mask="0x0FFF"/>
             </register-group>
             <value-group caption="" name="COMM_USART_MODE">
                 <value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
index 63779722..3df9df6c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
@@ -479,10 +479,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -566,7 +566,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -621,7 +621,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -685,12 +685,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
index 0d367ec6..19be6d3f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
@@ -731,7 +731,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x26" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x24" size="1">
                     <bitfield caption="" mask="0x08" name="ADLAR"/>
                     <bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
@@ -826,7 +826,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -874,12 +874,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -917,12 +917,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC2A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC2B"/>
                 </register>
-                <register caption="Timer/Counter2  Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Output Compare Register A  Bytes" name="OCR2A" offset="0xC4" size="2"
+                <register caption="Timer/Counter2 Bytes" name="TCNT2" offset="0xC6" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter2 Output Compare Register A Bytes" name="OCR2A" offset="0xC4" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Output Compare Register B  Bytes" name="OCR2B" offset="0xC2" size="2"
+                <register caption="Timer/Counter2 Output Compare Register B Bytes" name="OCR2B" offset="0xC2" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter2 Input Capture Register  Bytes" name="ICR2" offset="0xC0" size="2"
+                <register caption="Timer/Counter2 Input Capture Register Bytes" name="ICR2" offset="0xC0" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -955,7 +955,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
index 88f3275d..43477895 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
@@ -539,10 +539,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="ADC Left Adjust Result" mask="0x10" name="ADLAR"/>
@@ -633,7 +633,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -688,7 +688,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag A" mask="0x02" name="OCF0A"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x50" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x50" size="1">
                     <bitfield caption="Compare Match Output A Mode bits" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Match Output B Mode bits" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode bits" mask="0x03" name="WGM0"/>
@@ -752,12 +752,12 @@
                     <bitfield caption="Force Output Compare for Channel A" mask="0x80" name="FOC1A"/>
                     <bitfield caption="Force Output Compare for Channel B" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x4A" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x4C" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x4A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x48" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x48" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x44" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x44" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
index 30080f31..2be13dcf 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
@@ -528,10 +528,10 @@
                     <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Input Polarity Mode" mask="0x20" name="IPR"/>
@@ -619,7 +619,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -673,7 +673,7 @@
                     <bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x08" name="OCF0B"/>
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x4A" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x4A" size="1">
                     <bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
                     <bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
                     <bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
@@ -805,7 +805,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
                     <bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
index a79b700f..da89541e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
@@ -577,7 +577,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -680,7 +680,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -737,7 +737,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
@@ -918,7 +918,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
                     <bitfield caption="Sleep Enable" mask="0x20" name="SE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
index 9cd439a0..304c2047 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
@@ -509,7 +509,7 @@
                     <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x24" size="2" mask="0xFFFF"/>
                 <register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x23" size="1">
                     <bitfield caption="Bipolar Input Mode" mask="0x80" name="BIN"/>
                     <bitfield caption="Gain Select" mask="0x40" name="GSEL"/>
@@ -612,7 +612,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x3E" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x3D" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3C" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -669,7 +669,7 @@
                     <bitfield caption="Timer/Counter0 Overflow Flag" mask="0x02" name="TOV0"/>
                     <bitfield caption="Timer/Counter0 Input Capture Flag" mask="0x01" name="ICF0"/>
                 </register>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x35" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x35" size="1">
                     <bitfield caption="Timer/Counter 0 Width" mask="0x80" name="TCW0"/>
                     <bitfield caption="Input Capture Mode Enable" mask="0x40" name="ICEN0"/>
                     <bitfield caption="Input Capture Noice Canceler" mask="0x20" name="ICNC0"/>
@@ -850,7 +850,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x03FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="BOD Sleep" mask="0x80" name="BODS"/>
                     <bitfield caption="Pull-up Disable" mask="0x40" name="PUD"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
index 408acf77..9eb46966 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
@@ -587,7 +587,7 @@
                     <bitfield caption="Enable External Clock Input" mask="0x40" name="EXCLK"/>
                     <bitfield caption="Asynchronous Timer/Counter0" mask="0x20" name="AS0"/>
                     <bitfield caption="Timer/Counter0 Update Busy" mask="0x10" name="TCN0UB"/>
-                    <bitfield caption="Output Compare Register 0A  Update Busy" mask="0x08" name="OCR0AUB"/>
+                    <bitfield caption="Output Compare Register 0A Update Busy" mask="0x08" name="OCR0AUB"/>
                     <bitfield caption="Timer/Counter0 Control Register A Update Busy" mask="0x02" name="TCR0AUB"/>
                     <bitfield caption="Timer/Counter0 Control Register B Update Busy" mask="0x01" name="TCR0BUB"/>
                 </register>
@@ -659,12 +659,12 @@
                     <bitfield caption="Timer/Counter1 Output Compare U-pin Enable for Channel A" mask="0x01"
                               name="OC1AU"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register A  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register A Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register B  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register B Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
             </register-group>
             <value-group caption="" name="CLK_SEL_3BIT_EXT">
@@ -704,7 +704,7 @@
         </module>
         <module caption="EEPROM" name="EEPROM">
             <register-group caption="EEPROM" name="EEPROM">
-                <register caption="EEPROM Address Register  Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
+                <register caption="EEPROM Address Register Bytes" name="EEAR" offset="0x41" size="2" mask="0x01FF"/>
                 <register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
                 <register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
                     <bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
@@ -756,15 +756,15 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x1F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
                           ocd-rw="R">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)"
@@ -876,7 +876,7 @@
                     <bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
                 </register>
                 <register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x68" size="1">
-                    <bitfield caption="Pin Change Interrupt Enable  on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
+                    <bitfield caption="Pin Change Interrupt Enable on any PCINT14..8 pin" mask="0x03" name="PCIE"/>
                 </register>
                 <register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
                     <bitfield caption="Pin Change Interrupt Flags" mask="0x03" name="PCIF"/>
@@ -928,7 +928,7 @@
                     <bitfield caption="Power Reduction USI" mask="0x02" name="PRUSI"/>
                     <bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
                 </register>
-                <register caption="Stack Pointer  Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
+                <register caption="Stack Pointer Bytes" name="SP" offset="0x5D" size="2" mask="0x07FF"/>
                 <register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
                     <bitfield caption="BOD Sleep" mask="0x40" name="BODS"/>
                     <bitfield caption="BOD Sleep Enable" mask="0x20" name="BODSE"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
index dc4da540..b54e7c2e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
@@ -528,12 +528,12 @@
                     <bitfield caption="" mask="0x80" name="FOC1A"/>
                     <bitfield caption="" mask="0x40" name="FOC1B"/>
                 </register>
-                <register caption="Timer/Counter1  Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1A" offset="0x88" size="2"
+                <register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Output Compare Register  Bytes" name="OCR1B" offset="0x8A" size="2"
+                <register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
                           mask="0xFFFF"/>
-                <register caption="Timer/Counter1 Input Capture Register  Bytes" name="ICR1" offset="0x86" size="2"
+                <register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
                           mask="0xFFFF"/>
                 <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
                     <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -694,14 +694,14 @@
                     <bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
                     <bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
                 </register>
-                <register caption="ADC Data Register  Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
+                <register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
                 <register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1">
                     <bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
                     <bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
-                    <bitfield caption="ADC  Auto Trigger Enable" mask="0x20" name="ADATE"/>
+                    <bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
                     <bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
                     <bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
-                    <bitfield caption="ADC  Prescaler Select Bits" mask="0x07" name="ADPS"
+                    <bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
                               values="ANALOG_ADC_PRESCALER"/>
                 </register>
                 <register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -796,7 +796,7 @@
                 <register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1"
                           mask="0xFF"/>
                 <register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
-                <register caption="Timer/Counter  Control Register A" name="TCCR0A" offset="0x45" size="1">
+                <register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x45" size="1">
                     <bitfield caption="Clear Timer on Compare Match" mask="0x08" name="CTC0"/>
                     <bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
                 </register>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
index 7cf693a9..fe08196d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
@@ -2505,7 +2505,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
index 936e1d26..0c6c4f21 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
@@ -3015,7 +3015,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -3099,7 +3099,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
index 678eac6f..1859c24d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
@@ -2263,7 +2263,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
index 02bcceca..219ac7d1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
@@ -2672,7 +2672,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2756,7 +2756,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
index e4116d37..2a707772 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
@@ -2504,7 +2504,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2588,7 +2588,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
index b864d25c..3971d041 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
@@ -2267,7 +2267,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2351,7 +2351,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
index d95e321a..c9b2891b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
@@ -2138,7 +2138,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAB" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2222,7 +2222,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
index fec59e1b..722e07d6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
@@ -2029,7 +2029,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2113,7 +2113,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
index cfbd7c19..2478daf1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
@@ -2039,7 +2039,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
index 594bac86..70f6078a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
@@ -1782,7 +1782,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -1866,7 +1866,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
index af3ada38..00b00385 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
@@ -2201,7 +2201,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
index 2b2d2e80..9adab1f7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
@@ -2494,7 +2494,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2578,7 +2578,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
index 78f140fc..4f125eb4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
@@ -1985,7 +1985,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2069,7 +2069,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
index 342f01e5..4bc8c8c6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
@@ -1961,7 +1961,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
index 0010c43b..0a44bd05 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
@@ -2325,7 +2325,7 @@
         </module>
         <module name="TC" id="I3007" version="XMEGAE" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 4" name="TC4" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
@@ -2476,7 +2476,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 5" name="TC5" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
index b38196bb..060b3fed 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
@@ -2263,7 +2263,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
index 24cd8f27..a8b49716 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
@@ -2672,7 +2672,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2756,7 +2756,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
index 69222579..86761969 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
@@ -1852,7 +1852,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -1936,7 +1936,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
index 8b9323de..c79161f8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
@@ -2039,7 +2039,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
index 90ae638c..942f5a6b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
@@ -2264,7 +2264,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
index 5a238454..2495cdec 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
@@ -2247,7 +2247,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
index 89abc159..8fa2ce30 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
@@ -2609,7 +2609,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2693,7 +2693,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
index 9657ed1a..d10a534c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
@@ -2672,7 +2672,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2756,7 +2756,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
index 79b37f49..187aa873 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
@@ -2029,7 +2029,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2113,7 +2113,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
index 292c1703..f06db63f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
@@ -2036,7 +2036,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
index 137d0425..8296597d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
@@ -2201,7 +2201,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
index 150bd2a8..0d859927 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
@@ -2495,7 +2495,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2579,7 +2579,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
index a0a507f4..fab0bf1c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
@@ -2029,7 +2029,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2113,7 +2113,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
index 8d76e8f6..90126399 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
@@ -1985,7 +1985,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2069,7 +2069,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
index 89a3afe3..8e37b6ae 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
@@ -2038,7 +2038,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
index dedce95a..5d6c4c4f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
@@ -1961,7 +1961,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
index fcb57a59..3d44148a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
@@ -2325,7 +2325,7 @@
         </module>
         <module name="TC" id="I3007" version="XMEGAE" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 4" name="TC4" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
@@ -2476,7 +2476,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 5" name="TC5" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
index 91b97e4e..3b5e887f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
@@ -2263,7 +2263,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2347,7 +2347,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
index b22ffc6f..8e0fb57f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
@@ -1865,7 +1865,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -1949,7 +1949,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
index 61db179b..74c167bd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
@@ -2505,7 +2505,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
index f2b22428..174857de 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
@@ -3015,7 +3015,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -3099,7 +3099,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
index 0b58ee77..af5366bb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
@@ -2263,7 +2263,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
index d87dbc01..6b124a1e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
@@ -2672,7 +2672,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2756,7 +2756,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
index 25ac1920..201980e1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
@@ -2504,7 +2504,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAAU" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2588,7 +2588,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
index f7e48618..5a1cb9c9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
@@ -2265,7 +2265,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAB" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2349,7 +2349,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
index 853e4a6c..22f55eb9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
@@ -2136,7 +2136,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAB" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2220,7 +2220,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
index 7e44b14f..f79caa8b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
@@ -2030,7 +2030,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -2114,7 +2114,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
index 77443dab..8d5e365a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
@@ -2039,7 +2039,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
index a5422600..09ef2371 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
@@ -1772,7 +1772,7 @@
         </module>
         <module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
@@ -1856,7 +1856,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
                 </register>
                 <register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
index 09afe391..215d3f77 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
@@ -2325,7 +2325,7 @@
         </module>
         <module name="TC" id="I3007" version="XMEGAE" caption="16-bit Timer/Counter With PWM">
             <register-group caption="16-bit Timer/Counter 4" name="TC4" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
@@ -2476,7 +2476,7 @@
                 <register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
             </register-group>
             <register-group caption="16-bit Timer/Counter 5" name="TC5" size="64">
-                <register caption="Control  Register A" name="CTRLA" offset="0x00" size="1">
+                <register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
                     <bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
                     <bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
                     <bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>