doryan/BloomPatched
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Tidied caption attributes in AVR8 TDFs

Browse Source
This commit is contained in:
Nav
2021-09-17 22:44:36 +01:00
parent 671e3dd51b
commit 8b74b36842
183 changed files with 1409 additions and 1409 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
View File

@@ -635,7 +635,7 @@
<bitfield caption="Character Size - together with UCSZ2 in UCSR0B" mask="0x06" name="UCSZ0"/>
<bitfield caption="Clock Polarity" mask="0x01" name="UCPOL0"/>
</register>
<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
<register caption="USART Baud Rate Register Bytes" name="UBRR0" offset="0xC4" size="2" mask="0x0FFF"/>
</register-group>
<value-group caption="" name="COMM_USART_MODE_2BIT">
<value caption="Asynchronous USART" name="VAL_0x00" value="0x00"/>
@@ -718,12 +718,12 @@
<bitfield caption="" mask="0x80" name="FOC1A"/>
<bitfield caption="" mask="0x40" name="FOC1B"/>
</register>
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
mask="0xFFFF"/>
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
mask="0xFFFF"/>
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
mask="0xFFFF"/>
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
@@ -804,15 +804,15 @@
<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
<bitfield caption="Analog Channel Selection Bits" mask="0x0F" name="MUX" values="ADC_MUX_SINGLE"/>
</register>
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
<register caption="The ADC Control and Status register A" name="ADCSRA" offset="0x7A" size="1"
ocd-rw="R">
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
values="ANALOG_ADC_PRESCALER"/>
</register>
<register caption="The ADC Control and Status register B" name="ADCSRB" offset="0x7B" size="1">
@@ -925,7 +925,7 @@
<bitfield caption="" mask="0x08" name="WGM02"/>
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
</register>
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>