RISC-V general purpose register descriptors

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2023-11-24 15:19:52 +00:00
parent fad19ce114
commit 73b1328f9f
4 changed files with 92 additions and 3 deletions

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@@ -26,7 +26,21 @@ namespace Targets::RiscV
RiscV::RiscV(const TargetConfig& targetConfig)
: name("CH32X035C8T6") // TODO: TDF
{}
, stackPointerRegisterDescriptor(
RiscVRegisterDescriptor(
TargetRegisterType::STACK_POINTER,
static_cast<RegisterNumber>(Registers::RegisterNumber::STACK_POINTER_X2),
4,
TargetMemoryType::OTHER,
"SP",
"CPU",
"Stack Pointer Register",
TargetRegisterAccess(true, true)
)
)
{
this->loadRegisterDescriptors();
}
bool RiscV::supportsDebugTool(DebugTool* debugTool) {
return debugTool->getRiscVDebugInterface() != nullptr;
@@ -90,7 +104,7 @@ namespace Targets::RiscV
)
}
},
{},
{this->registerDescriptorsById.begin(), this->registerDescriptorsById.end()},
BreakpointResources(0, 0, 0),
{},
TargetMemoryType::FLASH
@@ -258,6 +272,26 @@ namespace Targets::RiscV
return false;
}
void RiscV::loadRegisterDescriptors() {
for (std::uint8_t i = 0; i <= 31; i++) {
auto generalPurposeRegisterDescriptor = RiscVRegisterDescriptor(
TargetRegisterType::GENERAL_PURPOSE_REGISTER,
static_cast<RegisterNumber>(Registers::RegisterNumberBase::GPR) + i,
4,
TargetMemoryType::OTHER,
"x" + std::to_string(i),
"CPU General Purpose",
std::nullopt,
TargetRegisterAccess(true, true)
);
this->registerDescriptorsById.emplace(
generalPurposeRegisterDescriptor.id,
std::move(generalPurposeRegisterDescriptor)
);
}
}
std::set<DebugModule::HartIndex> RiscV::discoverHartIndices() {
auto hartIndices = std::set<DebugModule::HartIndex>();