RISC-V general purpose register descriptors
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@@ -26,7 +26,21 @@ namespace Targets::RiscV
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RiscV::RiscV(const TargetConfig& targetConfig)
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: name("CH32X035C8T6") // TODO: TDF
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{}
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, stackPointerRegisterDescriptor(
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RiscVRegisterDescriptor(
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TargetRegisterType::STACK_POINTER,
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static_cast<RegisterNumber>(Registers::RegisterNumber::STACK_POINTER_X2),
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4,
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TargetMemoryType::OTHER,
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"SP",
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"CPU",
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"Stack Pointer Register",
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TargetRegisterAccess(true, true)
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)
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)
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{
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this->loadRegisterDescriptors();
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}
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bool RiscV::supportsDebugTool(DebugTool* debugTool) {
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return debugTool->getRiscVDebugInterface() != nullptr;
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@@ -90,7 +104,7 @@ namespace Targets::RiscV
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)
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}
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},
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{},
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{this->registerDescriptorsById.begin(), this->registerDescriptorsById.end()},
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BreakpointResources(0, 0, 0),
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{},
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TargetMemoryType::FLASH
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@@ -258,6 +272,26 @@ namespace Targets::RiscV
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return false;
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}
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void RiscV::loadRegisterDescriptors() {
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for (std::uint8_t i = 0; i <= 31; i++) {
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auto generalPurposeRegisterDescriptor = RiscVRegisterDescriptor(
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TargetRegisterType::GENERAL_PURPOSE_REGISTER,
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static_cast<RegisterNumber>(Registers::RegisterNumberBase::GPR) + i,
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4,
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TargetMemoryType::OTHER,
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"x" + std::to_string(i),
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"CPU General Purpose",
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std::nullopt,
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TargetRegisterAccess(true, true)
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);
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this->registerDescriptorsById.emplace(
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generalPurposeRegisterDescriptor.id,
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std::move(generalPurposeRegisterDescriptor)
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);
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}
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}
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std::set<DebugModule::HartIndex> RiscV::discoverHartIndices() {
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auto hartIndices = std::set<DebugModule::HartIndex>();
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