Massive refactor to accommodate RISC-V targets

- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here

src/Targets/RiscV/RiscVTargetConfig.cpp

@@ -0,0 +1,8 @@
+#include "RiscVTargetConfig.hpp"
+
+namespace Targets::RiscV
+{
+    RiscVTargetConfig::RiscVTargetConfig(const TargetConfig& targetConfig)
+        : TargetConfig(targetConfig)
+    {}
+}