Nav 248c51acc8 Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.

2024-10-07 20:02:39 +01:00

..

DebugModule

Tidying RISC-V register structs

2024-09-04 00:13:55 +01:00

Registers

First pass at RISC-V hardware breakpoints (Trigger module)

2024-10-06 17:54:08 +01:00

TriggerModule

First pass at RISC-V hardware breakpoints (Trigger module)

2024-10-06 17:54:08 +01:00

DebugTranslator.cpp

Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.

2024-10-07 20:02:39 +01:00

DebugTranslator.hpp

Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.

2024-10-07 20:02:39 +01:00

DebugTranslatorConfig.cpp

Added config struct for RISC-V debug translator implementation, and WCH debug tools.

2024-10-06 23:32:36 +01:00

DebugTranslatorConfig.hpp

Added config struct for RISC-V debug translator implementation, and WCH debug tools.

2024-10-06 23:32:36 +01:00

DebugTransportModuleInterface.hpp

Massive refactor to accommodate RISC-V targets

2024-07-23 21:14:22 +01:00

RiscVGeneric.hpp

Massive refactor to accommodate RISC-V targets

2024-07-23 21:14:22 +01:00