Nav 00d6f5fb71 Corrected bug in RISC-V debug translator where a reset wasn't always keeping the target halted

2024-10-19 14:22:12 +01:00

..

DebugModule

Tidying RISC-V register structs

2024-10-16 21:22:16 +01:00

Registers

Tidying RISC-V register structs

2024-10-16 21:22:16 +01:00

TriggerModule

Tidying RISC-V register structs

2024-10-16 21:22:16 +01:00

DebugTranslator.cpp

Corrected bug in RISC-V debug translator where a reset wasn't always keeping the target halted

2024-10-19 14:22:12 +01:00

DebugTranslator.hpp

Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.

2024-10-07 20:02:39 +01:00

DebugTranslatorConfig.cpp

Tidying RISC-V register structs

2024-10-16 21:22:16 +01:00

DebugTranslatorConfig.hpp

Added config struct for RISC-V debug translator implementation, and WCH debug tools.

2024-10-06 23:32:36 +01:00

DebugTransportModuleInterface.hpp

Massive refactor to accommodate RISC-V targets

2024-07-23 21:14:22 +01:00

RiscVGeneric.hpp

Tidying RISC-V register structs

2024-10-16 21:22:16 +01:00