Nav
ef19ffe996
New wrb GDB monitor command, for writing to individual bit fields of target registers
2024-12-18 01:11:41 +00:00
Nav
36abea6ce1
Tidying
2024-12-16 21:38:09 +00:00
Nav
9486cc0163
Help text for target driver passthrough commands
2024-12-16 21:37:24 +00:00
Nav
40859201e4
Target driver passthrough commands
...
Added `pm` commands to manage the program mode of WCH targets
2024-12-15 17:32:58 +00:00
Nav
1392cda74f
Adding boot/user mode switching functionality for WCH RISC-V targets
2024-12-15 02:47:39 +00:00
Nav
4ff7c76621
New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors
2024-12-15 00:40:54 +00:00
Nav
6dd8f0453e
Block memory writes to read-only selected program memory segments
2024-12-15 00:33:48 +00:00
Nav
9e5d69dee4
Tidying
2024-12-14 16:17:54 +00:00
Nav
87ffc10306
Tidying
2024-12-14 02:10:02 +00:00
Nav
2580cecb26
Handle mapped program memory segment aliasing properly, on WCH RISC-V targets
...
- Added `program_segment_key` target config param, to allow the user to specify the desired program memory segment
- Added the ability to resolve the currently aliased segment, by means of probing the mapped segment
- Added program counter transformation, when the mapped segment is aliasing a foreign segment
- Other bites of tidying
2024-12-14 02:09:25 +00:00
Nav
cbfbd9f4b8
Applied debug-interface-specific access restrictions for memory and registers
2024-12-07 16:43:16 +00:00
Nav
289919f330
Tidying
2024-12-05 23:11:31 +00:00
Nav
33ed399337
WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying
2024-12-05 23:09:01 +00:00
Nav
966244a01a
Tidying
2024-11-29 01:53:01 +00:00
Nav
1d4def228b
Tidying
2024-11-29 01:19:58 +00:00
Nav
265e60c1b7
Fixed bug in RISC-V ISA string parsing
2024-11-29 01:13:12 +00:00
Nav
49cf2e5e9a
Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base.
2024-11-29 01:06:44 +00:00
Nav
8e86cfb152
Tidying
2024-11-28 21:49:03 +00:00
Nav
9c1b194af1
Changed all bloom.yaml config keys/values to use snake_casing
2024-11-28 21:44:04 +00:00
Nav
a63dd1b4ef
Corrected architecture string in AVR8 TDFs
2024-11-27 20:02:43 +00:00
Nav
899cbc92c4
Made default value of reserveSteppingBreakpoint target config param vary across targets
2024-11-24 19:33:28 +00:00
Nav
7c647caa67
Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity
2024-11-24 19:32:00 +00:00
Nav
d8131080ec
Implemented memory access via program buffer, in RISC-V debug translator
...
- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator
2024-11-23 20:14:47 +00:00
Nav
f6819d35de
Tidying
2024-11-17 16:15:13 +00:00
Nav
c14aab0fc4
Fixed dangling reference bug that was resulting in invalid mapped_io segment in EDBG session object.
2024-11-17 13:13:15 +00:00
Nav
3009cdd951
Tidying
2024-11-16 21:50:04 +00:00
Nav
4147af618b
Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)
2024-11-16 21:49:49 +00:00
Nav
eebba986b5
RISC-V GDB server
2024-11-16 20:43:22 +00:00
Nav
26f4f8f90e
Tidying
2024-11-16 20:06:55 +00:00
Nav
07283a2dc7
Flash programming support for WCH-LinkE tool
2024-11-16 20:05:26 +00:00
Nav
de02bf318c
Corrected HW breakpoint count bug in WchRiscV target
2024-11-06 20:06:55 +00:00
Nav
7662dec100
Tidying
2024-11-06 20:05:59 +00:00
Nav
f0b7f3193c
Corrected string->int conversion bug in TargetPinDescriptor.
...
The `numericPosition` member should really be removed. Will revisit later.
2024-10-27 00:28:41 +01:00
Nav
1bb2214721
Tidying
2024-10-18 00:02:00 +01:00
Nav
9c1385a048
Deleted TDF documentation (don't have the capacity to maintain it ATM)
2024-10-18 00:01:21 +01:00
Nav
52171734d8
New WchRiscV target class
2024-10-12 23:16:16 +01:00
Nav
5c896bb2ca
Support for property groups in variant elements, in TDFs
2024-10-12 16:25:11 +01:00
Nav
4eeeaf7fa6
Reordered pads in AVR8 TDFs
2024-10-12 00:03:49 +01:00
Nav
9cfc171255
Added description member to TargetPeripheralDescriptor
2024-10-08 21:26:03 +01:00
Nav
9e4d10ae91
Tidying
2024-10-07 20:03:19 +01:00
Nav
248c51acc8
Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.
2024-10-07 20:02:39 +01:00
Nav
607a344107
Made TargetMemoryCache use TargetMemorySegmentDescriptor, as the base memory descriptor (instead of TargetMemoryAddressSpaceDescriptor).
...
Basing the memory cache on address spaces will result in large amounts of memory being unnecessarily reserved for large address spaces.
2024-10-07 00:14:39 +01:00
Nav
d71083c3f9
Tidying
2024-10-06 18:10:02 +01:00
Nav
ecd0f5b054
First pass at RISC-V hardware breakpoints (Trigger module)
2024-10-06 17:54:08 +01:00
Nav
7fc1145d4b
Moved reserveSteppingBreakpoint AVR8 config param to more generic TargetConfig struct
2024-10-06 17:09:06 +01:00
Nav
675b375da7
Removed non-alphanumeric characters from keys in TDFs
2024-10-05 02:18:20 +01:00
Nav
12ca84735f
Renamed USB pad keys in TDFs
2024-10-05 02:07:24 +01:00
Nav
d906f2f426
Added alternative flag to Signal element in TDFs
2024-10-04 23:45:16 +01:00
Nav
5b2b73eb9f
Renamed SCK ISP signal to SCLK, for consistency
2024-10-03 23:39:38 +01:00
Nav
ca498c64c2
Added SDI physical interface
2024-10-03 22:56:13 +01:00
