4 Commits

Author	SHA1	Message	Date
Nav	cbfbd9f4b8	Applied debug-interface-specific access restrictions for memory and registers	2024-12-07 16:43:16 +00:00
Nav	33ed399337	WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying	2024-12-05 23:09:01 +00:00
Nav	4147af618b	Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)	2024-11-16 21:49:49 +00:00
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00