doryan/BloomPatched
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b46b4a77a1e323fb3ec7fb81e20634f66e923152
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435 Commits

Author SHA1 Message Date
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b46b4a77a1 Added missing GPR address space check in RiscV::writeRegisters() 2025-01-26 02:29:08 +00:00
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c64e34ed05 Removed invalid page sizes from memory segments in AVR8 TDFs 2025-01-22 22:43:43 +00:00
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1d0e1346de AVR8 EDBG driver changes: 
- Concealing pending software breakpoint operations
- Injecting active software breakpoints for memory types that filter them out
- Some tidying
 2025-01-19 14:45:15 +00:00
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3ae03b8981 Corrected address range in address space descriptor 2025-01-19 01:01:47 +00:00
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37377fb988 Tidying 2025-01-18 18:46:00 +00:00
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779e938746 Included RISC-V CSRs in WCH TDFs 2025-01-18 18:45:07 +00:00
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2a51f8af75 Consistent casing in directory names 2025-01-07 23:31:48 +00:00
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e98a73e687 - Additional target config options. 
- Some tidying
 2025-01-07 22:38:11 +00:00
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7605d5e3a0 Corrected memory segment type in recently added ATtiny TDFs 2025-01-06 22:33:07 +00:00
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b999c5382c Support for a number of AVRDU/EA/EB targets 2025-01-06 22:32:26 +00:00
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cc05c4c36b Added support for ATtiny3224/6/7 2025-01-05 23:49:07 +00:00
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ab49d10bef Tidying 2024-12-29 04:03:07 +00:00
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43bbd59c9e New TDF for WCH RISC-V CH32V003 2024-12-29 03:51:34 +00:00
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dfb1cd3e51 Corrections to CH32X035 TDF 2024-12-29 03:50:58 +00:00
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dbd2b87ebc TDF for the WCH RISC-V CH32X035 2024-12-28 01:07:30 +00:00
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4dc019e915 Moved RISC-V CSR and GPR address spaces to TDF. 
Some other bits of refactoring/tidying
 2024-12-27 03:41:39 +00:00
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7aeb2ddf08 Tidying 2024-12-24 20:11:47 +00:00
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674b11575d Tidying 2024-12-24 19:58:48 +00:00
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c288e0e838 Reused CPU peripheral for GPRs in AVR8 driver 2024-12-24 19:58:22 +00:00
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9b60bb5682 Updated memory segment access values for AVR flash segments 2024-12-24 19:38:04 +00:00
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7fe5b88dd8 Refactored Insight GUI to accommodate the many changes made to Bloom's internals 
Also lots of tidying.
 2024-12-24 18:27:59 +00:00
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28e0a6d9e4 Renaming and other tidying 2024-12-21 13:51:00 +00:00
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79b7457c89 GPIO pad state access and manipulation for WCH RISC-V targets 2024-12-21 02:10:31 +00:00
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d485263c6d Enabled memory inspection for boot segment of WCH RISC-V targets 2024-12-19 23:47:24 +00:00
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ef19ffe996 New wrb GDB monitor command, for writing to individual bit fields of target registers 2024-12-18 01:11:41 +00:00
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36abea6ce1 Tidying 2024-12-16 21:38:09 +00:00
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9486cc0163 Help text for target driver passthrough commands 2024-12-16 21:37:24 +00:00
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40859201e4 Target driver passthrough commands 
Added `pm` commands to manage the program mode of WCH targets
 2024-12-15 17:32:58 +00:00
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1392cda74f Adding boot/user mode switching functionality for WCH RISC-V targets 2024-12-15 02:47:39 +00:00
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4ff7c76621 New DynamicRegisterValue for inspecting and manipulating register bit fields, via bit field descriptors 2024-12-15 00:40:54 +00:00
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6dd8f0453e Block memory writes to read-only selected program memory segments 2024-12-15 00:33:48 +00:00
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9e5d69dee4 Tidying 2024-12-14 16:17:54 +00:00
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87ffc10306 Tidying 2024-12-14 02:10:02 +00:00
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2580cecb26 Handle mapped program memory segment aliasing properly, on WCH RISC-V targets 
- Added `program_segment_key` target config param, to allow the user to specify the desired program memory segment
- Added the ability to resolve the currently aliased segment, by means of probing the mapped segment
- Added program counter transformation, when the mapped segment is aliasing a foreign segment
- Other bites of tidying
 2024-12-14 02:09:25 +00:00
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cbfbd9f4b8 Applied debug-interface-specific access restrictions for memory and registers 2024-12-07 16:43:16 +00:00
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289919f330 Tidying 2024-12-05 23:11:31 +00:00
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33ed399337 WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying 2024-12-05 23:09:01 +00:00
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966244a01a Tidying 2024-11-29 01:53:01 +00:00
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1d4def228b Tidying 2024-11-29 01:19:58 +00:00
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265e60c1b7 Fixed bug in RISC-V ISA string parsing 2024-11-29 01:13:12 +00:00
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49cf2e5e9a Added RISC-V IsaDescriptor class, and adjusted RISC-V GPR count depending on ISA base. 2024-11-29 01:06:44 +00:00
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8e86cfb152 Tidying 2024-11-28 21:49:03 +00:00
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9c1b194af1 Changed all bloom.yaml config keys/values to use snake_casing 2024-11-28 21:44:04 +00:00
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a63dd1b4ef Corrected architecture string in AVR8 TDFs 2024-11-27 20:02:43 +00:00
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899cbc92c4 Made default value of reserveSteppingBreakpoint target config param vary across targets 2024-11-24 19:33:28 +00:00
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7c647caa67 Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity 2024-11-24 19:32:00 +00:00
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d8131080ec Implemented memory access via program buffer, in RISC-V debug translator 
- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator
 2024-11-23 20:14:47 +00:00
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f6819d35de Tidying 2024-11-17 16:15:13 +00:00
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c14aab0fc4 Fixed dangling reference bug that was resulting in invalid mapped_io segment in EDBG session object. 2024-11-17 13:13:15 +00:00
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3009cdd951 Tidying 2024-11-16 21:50:04 +00:00