3 Commits

Author	SHA1	Message	Date
Nav	d8131080ec	Implemented memory access via program buffer, in RISC-V debug translator ... - Support for multiple memory access strategies (abstract commands and program buffer) - Probing of memory access strategies - Included `preferredMemoryAccessStrategy` debug translator config param - Other bits of tidying in the RISC-V debug translator	2024-11-23 20:14:47 +00:00
Nav	348ec19c1b	Tidying RISC-V register structs ... - Removed unnecessary bit fields - Added default values to members - Removed all user-defined constructors to make the structs aggregate, replacing the from-value constructor with a `fromValue()` status member function. - Made use of designated initialisation - Changed unscoped enums to scoped - Other small bits of tidying	2024-10-16 21:22:16 +01:00
Nav	418db1df99	Added config struct for RISC-V debug translator implementation, and WCH debug tools. ... Also some tidying in the `DebugToolConfig` struct	2024-10-06 23:32:36 +01:00