3 Commits

Author	SHA1	Message	Date
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00
Nav	0ee769c872	Used TargetRegisterAccess object in place of a string for Register TDF struct	2024-03-20 21:12:00 +00:00
Nav	205ed1d55c	Updated TDF module, register group, register group reference, register and bit field extraction to align with new TDF format	2024-02-26 19:27:36 +00:00