6 Commits

Author	SHA1	Message	Date
Nav	6c67424af9	On RISC-V activation, clear any triggers that were left over from a previous debug session	2024-10-06 18:06:58 +01:00
Nav	ecd0f5b054	First pass at RISC-V hardware breakpoints (Trigger module)	2024-10-06 17:54:08 +01:00
Nav	ecf0bd8919	Added try member functions for RISC-V abstract commands and register access	2024-09-04 00:15:46 +01:00
Nav	2a01f727bf	Tidying RISC-V register structs	2024-09-04 00:13:55 +01:00
Nav	914153077e	Corrected memory address/size alignment in EDBG and RISC-V drivers	2024-08-30 19:59:59 +01:00
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00