5 Commits

Author	SHA1	Message	Date
Nav	ecd0f5b054	First pass at RISC-V hardware breakpoints (Trigger module)	2024-10-06 17:54:08 +01:00
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00
Nav	cc33eea712	RISC-V target ID verification upon activation	2023-12-17 18:43:16 +00:00
Nav	ba32e9baf9	Tidying	2023-11-23 17:53:50 +00:00
Nav	826da3e921	Initial pass at a RiscVDebugInterface and implementation (for WCH-Link debug tools)	2023-11-21 21:40:40 +00:00