2 Commits

Author	SHA1	Message	Date
Nav	914153077e	Corrected memory address/size alignment in EDBG and RISC-V drivers	2024-08-30 19:59:59 +01:00
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00