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33ed399337
WCH RISC-V software breakpoints, and a few other bits of refactoring/tidying
2024-12-05 23:09:01 +00:00
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7c647caa67
Refactored WCH-Link/RISC-V implementation to accommodate SW breakpoints and reduce complexity
2024-11-24 19:32:00 +00:00
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4147af618b
Move away from using const references of std::vector<unsigned char> for target memory buffers. Replaced with std::span<const unsigned char> (via TargetMemoryBufferSpan alias)
2024-11-16 21:49:49 +00:00
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248c51acc8
Renamed RiscVDebugInterface::clearAllBreakpoints() in preparation for separating HW breakpoints from SW breakpoints.
2024-10-07 20:02:39 +01:00
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ecd0f5b054
First pass at RISC-V hardware breakpoints (Trigger module)
2024-10-06 17:54:08 +01:00
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6cdbfbe950
Massive refactor to accommodate RISC-V targets
...
- Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR)
- Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website
- Added unit size property to address spaces
- Many other changes which I couldn't be bothered to describe here
2024-07-23 21:14:22 +01:00
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cc33eea712
RISC-V target ID verification upon activation
2023-12-17 18:43:16 +00:00
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ba32e9baf9
Tidying
2023-11-23 17:53:50 +00:00
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826da3e921
Initial pass at a RiscVDebugInterface and implementation (for WCH-Link debug tools)
2023-11-21 21:40:40 +00:00
