6 Commits

Author	SHA1	Message	Date
Nav	52171734d8	New WchRiscV target class	2024-10-12 23:16:16 +01:00
Nav	6cdbfbe950	Massive refactor to accommodate RISC-V targets ... - Refactored entire codebase (excluding the Insight component) to accommodate multiple target architectures (no longer specific to AVR) - Deleted 'generate SVD' GDB monitor command - I will eventually move this functionality to the Bloom website - Added unit size property to address spaces - Many other changes which I couldn't be bothered to describe here	2024-07-23 21:14:22 +01:00
Nav	fc1fd22499	Made a start with RISC-V target implementation	2023-11-22 00:38:40 +00:00
Nav	ba03833325	Lots of tidying ... - Removed generic `avr8` target - Simplified AVR8 target construction - Introduced register descriptor IDs - Simplified GDB register mappings - Simplified target interface contract - Other bits of tidying	2023-07-18 23:16:06 +01:00
Nav	7a28f93ee9	Tidying	2021-04-06 23:20:50 +01:00
Nav	a29c5e1fec	Initial commit	2021-04-04 21:04:12 +01:00