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Added try member functions for RISC-V abstract commands and register access

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2024-09-04 00:15:46 +01:00
parent 2a01f727bf
commit ecf0bd8919
2 changed files with 88 additions and 10 deletions
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15
src/DebugToolDrivers/Protocols/RiscVDebugSpec/DebugTranslator.hpp
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@@ -20,6 +20,9 @@
#include "DebugModule/Registers/AbstractControlStatusRegister.hpp"
#include "DebugModule/Registers/AbstractCommandRegister.hpp"
#include "src/Helpers/Expected.hpp"
namespace DebugToolDrivers::Protocols::RiscVDebugSpec
{
/**
@@ -92,12 +95,24 @@ namespace DebugToolDrivers::Protocols::RiscVDebugSpec
void enableDebugModule();
void disableDebugModule();
Expected<RegisterValue, DebugModule::AbstractCommandError> tryReadCpuRegister(RegisterNumber number);
Expected<RegisterValue, DebugModule::AbstractCommandError> tryReadCpuRegister(
Registers::CpuRegisterNumber number
);
RegisterValue readCpuRegister(RegisterNumber number);
RegisterValue readCpuRegister(Registers::CpuRegisterNumber number);
DebugModule::AbstractCommandError tryWriteCpuRegister(RegisterNumber number, RegisterValue value);
DebugModule::AbstractCommandError tryWriteCpuRegister(Registers::CpuRegisterNumber number, RegisterValue value);
void writeCpuRegister(RegisterNumber number, RegisterValue value);
void writeCpuRegister(Registers::CpuRegisterNumber number, RegisterValue value);
void writeDebugModuleControlRegister(const DebugModule::Registers::ControlRegister& controlRegister);
void writeDebugControlStatusRegister(const Registers::DebugControlStatusRegister& controlRegister);
DebugModule::AbstractCommandError tryExecuteAbstractCommand(
const DebugModule::Registers::AbstractCommandRegister& abstractCommandRegister
);
void executeAbstractCommand(const DebugModule::Registers::AbstractCommandRegister& abstractCommandRegister);
Targets::TargetMemoryAddress alignMemoryAddress(