Created new register type for port registers

This commit is contained in:
Nav
2021-09-12 23:25:59 +01:00
parent b81b51790e
commit dca5b362b3
3 changed files with 6 additions and 2 deletions

View File

@@ -485,7 +485,8 @@ void TargetDescriptionFile::loadTargetRegisterDescriptors() {
}
auto registerDescriptor = TargetRegisterDescriptor();
registerDescriptor.type = TargetRegisterType::OTHER;
registerDescriptor.type = moduleName == "port"
? TargetRegisterType::PORT_REGISTER : TargetRegisterType::OTHER;
registerDescriptor.memoryType = TargetMemoryType::RAM;
registerDescriptor.name = moduleRegisterName;
registerDescriptor.groupName = peripheralRegisterGroup.name;