Implemented memory access via program buffer, in RISC-V debug translator

- Support for multiple memory access strategies (abstract commands and program buffer)
- Probing of memory access strategies
- Included `preferredMemoryAccessStrategy` debug translator config param
- Other bits of tidying in the RISC-V debug translator

src/Targets/RiscV/Opcodes/Sw.hpp

@@ -0,0 +1,27 @@
+#pragma once
+
+#include <cstdint>
+#include <cassert>
+
+#include "Opcode.hpp"
+
+namespace Targets::RiscV::Opcodes
+{
+    struct Sw
+    {
+        GprNumber baseAddressRegister;
+        GprNumber valueRegister;
+        std::uint16_t addressOffset;
+
+        [[nodiscard]] constexpr Opcode opcode() const {
+            assert(this->addressOffset <= 0xFFF);
+
+            return Opcode{0x2023}
+                | static_cast<Opcode>(this->addressOffset & 0x1F) << 7
+                | static_cast<Opcode>(this->baseAddressRegister) << 15
+                | static_cast<Opcode>(this->valueRegister) << 20
+                | static_cast<Opcode>((this->addressOffset >> 5) & 0x7F) << 25
+            ;
+        }
+    };
+}