diff --git a/src/Targets/RiscV/RiscV.cpp b/src/Targets/RiscV/RiscV.cpp
index 9f33e46a..5f35f5c4 100644
--- a/src/Targets/RiscV/RiscV.cpp
+++ b/src/Targets/RiscV/RiscV.cpp
@@ -25,17 +25,16 @@ namespace Targets::RiscV
         , csrMemorySegmentDescriptor(this->csrAddressSpaceDescriptor.getMemorySegmentDescriptor("csr"))
         , gprAddressSpaceDescriptor(this->targetDescriptionFile.getGprAddressSpaceDescriptor())
         , gprMemorySegmentDescriptor(this->gprAddressSpaceDescriptor.getMemorySegmentDescriptor("gpr"))
-        , cpuPeripheralDescriptor(
-            RiscV::generateCpuPeripheralDescriptor(
+        , cpuPeripheralDescriptor(this->targetDescriptionFile.getTargetPeripheralDescriptor("cpu"))
+        , csrGroupDescriptor(this->cpuPeripheralDescriptor.getRegisterGroupDescriptor("csr"))
+        , gprGroupDescriptor(
+            RiscV::generateGeneralPurposeRegisterGroupDescriptor(
                 this->isaDescriptor,
-                this->csrAddressSpaceDescriptor,
                 this->gprAddressSpaceDescriptor,
-                this->csrMemorySegmentDescriptor,
-                this->gprMemorySegmentDescriptor
+                this->gprMemorySegmentDescriptor,
+                this->cpuPeripheralDescriptor
             )
         )
-        , csrGroupDescriptor(this->cpuPeripheralDescriptor.getRegisterGroupDescriptor("csr"))
-        , gprGroupDescriptor(this->cpuPeripheralDescriptor.getRegisterGroupDescriptor("gpr"))
         , pcRegisterDescriptor(this->csrGroupDescriptor.getRegisterDescriptor("dpc"))
         , spRegisterDescriptor(this->gprGroupDescriptor.getRegisterDescriptor("x2"))
         , sysAddressSpaceDescriptor(this->targetDescriptionFile.getSystemAddressSpaceDescriptor())
@@ -394,21 +393,12 @@ namespace Targets::RiscV
         return *(segmentDescriptors.front());
     }
 
-    TargetPeripheralDescriptor RiscV::generateCpuPeripheralDescriptor(
+    const TargetRegisterGroupDescriptor& RiscV::generateGeneralPurposeRegisterGroupDescriptor(
         const IsaDescriptor& isaDescriptor,
-        const TargetAddressSpaceDescriptor& csrAddressSpaceDescriptor,
         const TargetAddressSpaceDescriptor& gprAddressSpaceDescriptor,
-        const TargetMemorySegmentDescriptor& csrMemorySegmentDescriptor,
-        const TargetMemorySegmentDescriptor& gprMemorySegmentDescriptor
+        const TargetMemorySegmentDescriptor& gprMemorySegmentDescriptor,
+        TargetPeripheralDescriptor& cpuPeripheralDescriptor
     ) {
-        auto cpuPeripheralDescriptor = TargetPeripheralDescriptor{
-            "cpu",
-            "CPU",
-            "RISC-V GPRs and CSRs",
-            {},
-            {}
-        };
-
         auto& gprGroup = cpuPeripheralDescriptor.registerGroupDescriptorsByKey.emplace(
             "gpr",
             TargetRegisterGroupDescriptor{
@@ -443,275 +433,6 @@ namespace Targets::RiscV
             );
         }
 
-        auto& csrGroup = cpuPeripheralDescriptor.registerGroupDescriptorsByKey.emplace(
-            "csr",
-            TargetRegisterGroupDescriptor{
-                "csr",
-                "csr",
-                "CSR",
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                std::nullopt,
-                {},
-                {}
-            }
-        ).first->second;
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "marchid",
-            TargetRegisterDescriptor{
-                "marchid",
-                "MARCHID",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0xF12,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, false},
-                "Architecture ID",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mimpid",
-            TargetRegisterDescriptor{
-                "mimpid",
-                "MIMPID",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0xF13,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, false},
-                "Implementation ID",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mstatus",
-            TargetRegisterDescriptor{
-                "mstatus",
-                "MSTATUS",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x300,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine status",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "misa",
-            TargetRegisterDescriptor{
-                "misa",
-                "MISA",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x301,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "ISA and extensions",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mtvec",
-            TargetRegisterDescriptor{
-                "mtvec",
-                "MTVEC",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x305,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine trap-handler base address",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mcounteren",
-            TargetRegisterDescriptor{
-                "mcounteren",
-                "MCOUNTEREN",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x306,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine counter enable",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mscratch",
-            TargetRegisterDescriptor{
-                "mscratch",
-                "MSCRATCH",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x340,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Scratch register for machine trap handlers",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mepc",
-            TargetRegisterDescriptor{
-                "mepc",
-                "MEPC",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x341,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine exception program counter",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mcause",
-            TargetRegisterDescriptor{
-                "mcause",
-                "MCAUSE",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x342,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine trap cause",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mtval",
-            TargetRegisterDescriptor{
-                "mtval",
-                "MTVAL",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x343,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine bad address or instruction",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "mip",
-            TargetRegisterDescriptor{
-                "mip",
-                "MIP",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x344,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Machine interrupt pending",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "dcsr",
-            TargetRegisterDescriptor{
-                "dcsr",
-                "DCSR",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B0,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Debug control and status",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "dpc",
-            TargetRegisterDescriptor{
-                "dpc",
-                "DPC",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B1,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Debug program counter",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "dscratch0",
-            TargetRegisterDescriptor{
-                "dscratch0",
-                "DSCRATCH0",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B2,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Debug scratch 0",
-                {}
-            }
-        );
-
-        csrGroup.registerDescriptorsByKey.emplace(
-            "dscratch1",
-            TargetRegisterDescriptor{
-                "dscratch1",
-                "DSCRATCH1",
-                csrGroup.absoluteKey,
-                cpuPeripheralDescriptor.key,
-                csrAddressSpaceDescriptor.key,
-                csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B3,
-                4,
-                TargetRegisterType::OTHER,
-                TargetRegisterAccess{true, true},
-                "Debug scratch 1",
-                {}
-            }
-        );
-
-        return cpuPeripheralDescriptor;
+        return gprGroup;
     }
 }
diff --git a/src/Targets/RiscV/RiscV.hpp b/src/Targets/RiscV/RiscV.hpp
index b6a8e3d5..4fd09a25 100644
--- a/src/Targets/RiscV/RiscV.hpp
+++ b/src/Targets/RiscV/RiscV.hpp
@@ -126,12 +126,11 @@ namespace Targets::RiscV
             const TargetAddressSpaceDescriptor& addressSpaceDescriptor
         );
 
-        static TargetPeripheralDescriptor generateCpuPeripheralDescriptor(
+        static const TargetRegisterGroupDescriptor& generateGeneralPurposeRegisterGroupDescriptor(
             const IsaDescriptor& isaDescriptor,
-            const TargetAddressSpaceDescriptor& csrAddressSpaceDescriptor,
             const TargetAddressSpaceDescriptor& gprAddressSpaceDescriptor,
-            const TargetMemorySegmentDescriptor& csrMemorySegmentDescriptor,
-            const TargetMemorySegmentDescriptor& gprMemorySegmentDescriptor
+            const TargetMemorySegmentDescriptor& gprMemorySegmentDescriptor,
+            TargetPeripheralDescriptor& cpuPeripheralDescriptor
         );
     };
 }
diff --git a/src/Targets/RiscV/Wch/WchRiscV.cpp b/src/Targets/RiscV/Wch/WchRiscV.cpp
index 7ea06c24..6f926c32 100644
--- a/src/Targets/RiscV/Wch/WchRiscV.cpp
+++ b/src/Targets/RiscV/Wch/WchRiscV.cpp
@@ -135,6 +135,8 @@ namespace Targets::RiscV::Wch
             descriptor.breakpointResources.reservedHardwareBreakpoints = 1;
         }
 
+        // Replace the TDF CPU peripheral descriptor with the mutated copy (see RiscV base class)
+        descriptor.peripheralDescriptorsByKey.erase(this->cpuPeripheralDescriptor.key);
         descriptor.peripheralDescriptorsByKey.emplace(
             this->cpuPeripheralDescriptor.key,
             this->cpuPeripheralDescriptor.clone()
diff --git a/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32V003.xml b/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32V003.xml
index f94a36cb..dca7762a 100644
--- a/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32V003.xml
+++ b/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32V003.xml
@@ -196,8 +196,8 @@
         <peripheral key="extend" name="EXTEND" module-key="extend">
             <register-group-instance register-group-key="extend" address-space-key="system" offset="0x40023800"/>
         </peripheral>
-        <peripheral key="debug" name="DEBUG" module-key="debug">
-            <register-group-instance register-group-key="debug" address-space-key="csr" offset="0x000007C0"/>
+        <peripheral key="cpu" name="CPU" module-key="cpu">
+            <register-group-instance register-group-key="csr" address-space-key="csr" offset="0x00000300"/>
         </peripheral>
     </peripherals>
     <modules>
@@ -1985,9 +1985,51 @@
                 </register>
             </register-group>
         </module>
-        <module key="debug" name="DEBUG" description="Debug Support">
-            <register-group key="debug" name="DEBUG">
-                <register key="dbgmcu" name="DBGMCU" description="Debug MCU Configuration" offset="0x00" size="4" initial-value="0x00000000" access="RW">
+        <module key="cpu" name="CPU" description="RISC-V CPU">
+            <register-group key="csr" name="CSR">
+                <register key="mstatus" name="MSTATUS" description="Status" offset="0x00" size="4" initial-value="0x00000000" access="RW">
+                    <bit-field key="mppop" name="MPPOP" mask="0x01000000" access="RW"/>
+                    <bit-field key="mpop" name="MPOP" mask="0x00800000" access="RW"/>
+                    <bit-field key="mpp" name="MPP" mask="0x00001800" access="RW"/>
+                    <bit-field key="mpie" name="MPIE" mask="0x00000080" access="RW"/>
+                    <bit-field key="mie" name="MIE" mask="0x00000008" access="RW"/>
+                </register>
+                <register key="misa" name="MISA" description="ISA" offset="0x01" size="4" access="R">
+                    <bit-field key="mxl" name="MXL" mask="0xC0000000" access="R"/>
+                    <bit-field key="ext" name="EXTENSIONS" mask="0x03FFFFFF" access="R"/>
+                </register>
+                <register key="mtvec" name="MTVEC" description="Trap-handler Base Address" offset="0x05" size="4" access="RW">
+                    <bit-field key="addr" name="ADDR" mask="0xFFFFFFFC" access="RW"/>
+                    <bit-field key="mode" name="MODE" mask="0x00000003" access="RW"/>
+                </register>
+                <register key="mscratch" name="MSCRATCH" description="Scratch" offset="0x40" size="4" access="RW">
+                    <bit-field key="mscratch" name="MSCRATCH" mask="0xFFFFFFFF" access="RW"/>
+                </register>
+                <register key="mepc" name="MEPC" description="Exception Program Counter" offset="0x41" size="4" access="RW">
+                    <bit-field key="pc" name="PC" mask="0xFFFFFFFF" access="RW"/>
+                </register>
+                <register key="mcause" name="MCAUSE" description="Trap Cause" offset="0x42" size="4" access="RW">
+                    <bit-field key="int" name="INTERRUPT" mask="0x80000000" access="RW"/>
+                    <bit-field key="code" name="CODE" mask="0x7FFFFFFF" access="RW"/>
+                </register>
+                <register key="marchid" name="MARCHID" description="Architecture ID" offset="0xC12" size="4" access="R">
+                    <bit-field key="vendor0" name="VENDOR0" mask="0x7C000000" access="R"/>
+                    <bit-field key="vendor1" name="VENDOR1" mask="0x03E00000" access="R"/>
+                    <bit-field key="vendor2" name="VENDOR2" mask="0x001F0000" access="R"/>
+                    <bit-field key="arch_code" name="ARCH_CODE" mask="0x00007C00" access="R"/>
+                    <bit-field key="series_code" name="SERIES_CODE" mask="0x000003E0" access="R"/>
+                    <bit-field key="version_code" name="VERSION_CODE" mask="0x0000001F" access="R"/>
+                </register>
+                <register key="mimpid" name="MIMPID" description="Implementation ID" offset="0xC13" size="4" access="R">
+                    <bit-field key="vendor0" name="VENDOR0" mask="0x7C000000" access="R"/>
+                    <bit-field key="vendor1" name="VENDOR1" mask="0x03E00000" access="R"/>
+                    <bit-field key="vendor2" name="VENDOR2" mask="0x001F0000" access="R"/>
+                </register>
+                <register key="dcsr" name="DCSR" description="Debug Control and Status" offset="0x4B0" size="4" access="RW"/>
+                <register key="dpc" name="DPC" description="Debug Program Counter" offset="0x4B1" size="4" access="RW"/>
+                <register key="dscratch0" name="DSCRATCH0" description="Debug Scratch 0" offset="0x4B2" size="4" access="RW"/>
+                <register key="dscratch1" name="DSCRATCH1" description="Debug Scratch 1" offset="0x4B3" size="4" access="RW"/>
+                <register key="dbgmcu" name="DBGMCU" description="Debug MCU Configuration" offset="0x4C0" size="4" initial-value="0x00000000" access="RW">
                     <bit-field key="tim2_stop" name="TIM2_STOP" mask="0x00002000" access="RW"/>
                     <bit-field key="tim1_stop" name="TIM1_STOP" mask="0x00001000" access="RW"/>
                     <bit-field key="wwdg_stop" name="WWDG_STOP" mask="0x00000200" access="RW"/>
@@ -1995,6 +2037,11 @@
                     <bit-field key="standby" name="STANDBY" mask="0x00000004" access="RW"/>
                     <bit-field key="sleep" name="SLEEP" mask="0x00000001" access="RW"/>
                 </register>
+                <register key="intsyscr" name="INTSYSCR" description="Interrupt System Control" offset="0x504" size="4" initial-value="0x00000000" access="RW">
+                    <bit-field key="eabien" name="EABIEN" mask="0x00000004" access="RW"/>
+                    <bit-field key="inesten" name="INESTEN" mask="0x00000002" access="RW"/>
+                    <bit-field key="hwstken" name="HWSTKEN" mask="0x00000001" access="RW"/>
+                </register>
             </register-group>
         </module>
     </modules>
diff --git a/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32X035.xml b/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32X035.xml
index 79bc31f8..6da41ce9 100644
--- a/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32X035.xml
+++ b/src/Targets/TargetDescriptionFiles/RiscV/Wch/CH32X035.xml
@@ -420,8 +420,8 @@
                 <signal name="CC2" pad-key="pc15"/>
             </signals>
         </peripheral>
-        <peripheral key="debug" name="DEBUG" module-key="debug">
-            <register-group-instance register-group-key="debug" address-space-key="csr" offset="0x000007C0"/>
+        <peripheral key="cpu" name="CPU" module-key="cpu">
+            <register-group-instance register-group-key="csr" address-space-key="csr" offset="0x00000300"/>
         </peripheral>
     </peripherals>
     <modules>
@@ -3339,9 +3339,52 @@
                 </register-group>
             </register-group>
         </module>
-        <module key="debug" name="DEBUG" description="Debug Support">
-            <register-group key="debug" name="DEBUG">
-                <register key="dbgmcu" name="DBGMCU" description="Debug MCU Configuration" offset="0x00" size="4" initial-value="0x00000000" access="RW">
+        <module key="cpu" name="CPU" description="RISC-V CPU">
+            <register-group key="csr" name="CSR">
+                <register key="mstatus" name="MSTATUS" description="Status" offset="0x00" size="4" initial-value="0x00000000" access="RW">
+                    <bit-field key="mpp" name="MPP" mask="0x00001800" access="RW"/>
+                    <bit-field key="mpie" name="MPIE" mask="0x00000080" access="RW"/>
+                    <bit-field key="mie" name="MIE" mask="0x00000008" access="RW"/>
+                </register>
+                <register key="misa" name="MISA" description="ISA" offset="0x01" size="4" access="R">
+                    <bit-field key="mxl" name="MXL" mask="0xC0000000" access="R"/>
+                    <bit-field key="ext" name="EXTENSIONS" mask="0x03FFFFFF" access="R"/>
+                </register>
+                <register key="mtvec" name="MTVEC" description="Trap-handler Base Address" offset="0x05" size="4" access="RW">
+                    <bit-field key="addr" name="ADDR" mask="0xFFFFFFFC" access="RW"/>
+                    <bit-field key="mode" name="MODE" mask="0x00000003" access="RW"/>
+                </register>
+                <register key="mscratch" name="MSCRATCH" description="Scratch" offset="0x40" size="4" access="RW">
+                    <bit-field key="mscratch" name="MSCRATCH" mask="0xFFFFFFFF" access="RW"/>
+                </register>
+                <register key="mepc" name="MEPC" description="Exception Program Counter" offset="0x41" size="4" access="RW">
+                    <bit-field key="pc" name="PC" mask="0xFFFFFFFF" access="RW"/>
+                </register>
+                <register key="mcause" name="MCAUSE" description="Trap Cause" offset="0x42" size="4" access="RW">
+                    <bit-field key="int" name="INTERRUPT" mask="0x80000000" access="RW"/>
+                    <bit-field key="code" name="CODE" mask="0x7FFFFFFF" access="RW"/>
+                </register>
+                <register key="mtval" name="MTVAL" description="Exception Value (bad address or instruction)" offset="0x43" size="4" access="RW">
+                    <bit-field key="val" name="VALUE" mask="0xFFFFFFFF" access="RW"/>
+                </register>
+                <register key="marchid" name="MARCHID" description="Architecture ID" offset="0xC12" size="4" access="R">
+                    <bit-field key="vendor0" name="VENDOR0" mask="0x7C000000" access="R"/>
+                    <bit-field key="vendor1" name="VENDOR1" mask="0x03E00000" access="R"/>
+                    <bit-field key="vendor2" name="VENDOR2" mask="0x001F0000" access="R"/>
+                    <bit-field key="arch_code" name="ARCH_CODE" mask="0x00007C00" access="R"/>
+                    <bit-field key="series_code" name="SERIES_CODE" mask="0x000003E0" access="R"/>
+                    <bit-field key="version_code" name="VERSION_CODE" mask="0x0000001F" access="R"/>
+                </register>
+                <register key="mimpid" name="MIMPID" description="Implementation ID" offset="0xC13" size="4" access="R">
+                    <bit-field key="vendor0" name="VENDOR0" mask="0x7C000000" access="R"/>
+                    <bit-field key="vendor1" name="VENDOR1" mask="0x03E00000" access="R"/>
+                    <bit-field key="vendor2" name="VENDOR2" mask="0x001F0000" access="R"/>
+                </register>
+                <register key="dcsr" name="DCSR" description="Debug Control and Status" offset="0x4B0" size="4" access="RW"/>
+                <register key="dpc" name="DPC" description="Debug Program Counter" offset="0x4B1" size="4" access="RW"/>
+                <register key="dscratch0" name="DSCRATCH0" description="Debug Scratch 0" offset="0x4B2" size="4" access="RW"/>
+                <register key="dscratch1" name="DSCRATCH1" description="Debug Scratch 1" offset="0x4B3" size="4" access="RW"/>
+                <register key="dbgmcu" name="DBGMCU" description="Debug MCU Configuration" offset="0x4C0" size="4" initial-value="0x00000000" access="RW">
                     <bit-field key="tim3_stop" name="TIM3_STOP" mask="0x00004000" access="RW"/>
                     <bit-field key="tim2_stop" name="TIM2_STOP" mask="0x00002000" access="RW"/>
                     <bit-field key="tim1_stop" name="TIM1_STOP" mask="0x00001000" access="RW"/>
@@ -3351,6 +3394,13 @@
                     <bit-field key="stop" name="STOP" mask="0x00000002" access="RW"/>
                     <bit-field key="sleep" name="SLEEP" mask="0x00000001" access="RW"/>
                 </register>
+                <register key="gintenr" name="GINTENR" description="Global Interrupt Enable" offset="0x500" size="4" access="RW"/>
+                <register key="intsyscr" name="INTSYSCR" description="Interrupt System Control" offset="0x504" size="4" initial-value="0x00000000" access="RW">
+                    <bit-field key="eabien" name="EABIEN" mask="0x00000004" access="RW"/>
+                    <bit-field key="inesten" name="INESTEN" mask="0x00000002" access="RW"/>
+                    <bit-field key="hwstken" name="HWSTKEN" mask="0x00000001" access="RW"/>
+                </register>
+                <register key="corecfgr" name="CORECFGR" description="Microprocessor Configuration" offset="0x8C0" size="4" access="RW"/>
             </register-group>
         </module>
     </modules>