From 674b11575d6af2fd08cb77fdec493e93c6f38ad0 Mon Sep 17 00:00:00 2001 From: Nav Date: Tue, 24 Dec 2024 19:58:48 +0000 Subject: [PATCH] Tidying --- src/Targets/Microchip/AVR8/Avr8.cpp | 7 ++-- src/Targets/RiscV/RiscV.cpp | 54 +++++++++++++---------------- 2 files changed, 26 insertions(+), 35 deletions(-) diff --git a/src/Targets/Microchip/AVR8/Avr8.cpp b/src/Targets/Microchip/AVR8/Avr8.cpp index 8f125882..8f32c9e5 100644 --- a/src/Targets/Microchip/AVR8/Avr8.cpp +++ b/src/Targets/Microchip/AVR8/Avr8.cpp @@ -109,10 +109,7 @@ namespace Targets::Microchip::Avr8 } bool Avr8::supportsDebugTool(DebugTool* debugTool) { - return debugTool->getAvr8DebugInterface( - this->targetDescriptionFile, - this->targetConfig - ) != nullptr; + return debugTool->getAvr8DebugInterface(this->targetDescriptionFile, this->targetConfig) != nullptr; } void Avr8::setDebugTool(DebugTool* debugTool) { @@ -309,7 +306,7 @@ namespace Targets::Microchip::Avr8 registerFileMemorySegment.startAddress + i, 1, TargetRegisterType::GENERAL_PURPOSE_REGISTER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, std::nullopt, {} } diff --git a/src/Targets/RiscV/RiscV.cpp b/src/Targets/RiscV/RiscV.cpp index 345a4f12..3573b1db 100644 --- a/src/Targets/RiscV/RiscV.cpp +++ b/src/Targets/RiscV/RiscV.cpp @@ -17,10 +17,7 @@ namespace Targets::RiscV { - RiscV::RiscV( - const TargetConfig& targetConfig, - const TargetDescriptionFile& targetDescriptionFile - ) + RiscV::RiscV(const TargetConfig& targetConfig, const TargetDescriptionFile& targetDescriptionFile) : targetConfig(RiscVTargetConfig{targetConfig}) , targetDescriptionFile(targetDescriptionFile) , isaDescriptor(this->targetDescriptionFile.getIsaDescriptor()) @@ -98,7 +95,7 @@ namespace Targets::RiscV && !this->gprMemorySegmentDescriptor.addressRange.contains(descriptor->startAddress) ) { throw Exceptions::Exception{ - "Cannot access CPU register \"" + descriptor->key + "\" - unknown memory segment" + "Cannot access CPU register `" + descriptor->key + "` - unknown memory segment" }; } @@ -108,7 +105,7 @@ namespace Targets::RiscV if (descriptor->addressSpaceId != this->sysAddressSpaceDescriptor.id) { throw Exceptions::Exception{ - "Cannot access register \"" + descriptor->key + "\" - unknown address space" + "Cannot access register `" + descriptor->key + "` - unknown address space" }; } @@ -152,9 +149,7 @@ namespace Targets::RiscV } if (descriptor.addressSpaceId != this->sysAddressSpaceDescriptor.id) { - throw Exceptions::Exception{ - "Cannot access register \"" + descriptor.key + "\" - unknown address space" - }; + throw Exceptions::Exception{"Cannot access register `" + descriptor.key + "` - unknown address space"}; } auto value = pair.second; @@ -366,14 +361,13 @@ namespace Targets::RiscV if (segmentDescriptors.empty()) { throw Exceptions::Exception{ - "Cannot access system register \"" + regDescriptor.key + "\" - unknown memory segment" + "Cannot access system register `" + regDescriptor.key + "` - unknown memory segment" }; } if (segmentDescriptors.size() != 1) { throw Exceptions::Exception{ - "Cannot access system register \"" + regDescriptor.key - + "\" - register spans multiple memory segments" + "Cannot access system register `" + regDescriptor.key + "` - register spans multiple memory segments" }; } @@ -445,7 +439,7 @@ namespace Targets::RiscV TargetRegisterGroupDescriptor{ "gpr", "gpr", - "General Purpose Registers", + "GPR", cpuPeripheralDescriptor.key, addressSpaceDescriptor.key, std::nullopt, @@ -467,7 +461,7 @@ namespace Targets::RiscV gprMemorySegmentDescriptor.addressRange.startAddress + i, 4, TargetRegisterType::GENERAL_PURPOSE_REGISTER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, std::nullopt, {} } @@ -479,7 +473,7 @@ namespace Targets::RiscV TargetRegisterGroupDescriptor{ "csr", "csr", - "Control Status Registers", + "CSR", cpuPeripheralDescriptor.key, addressSpaceDescriptor.key, std::nullopt, @@ -499,7 +493,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0xF12, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, false), + TargetRegisterAccess{true, false}, "Architecture ID", {} } @@ -516,7 +510,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0xF13, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, false), + TargetRegisterAccess{true, false}, "Implementation ID", {} } @@ -533,7 +527,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x300, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine status", {} } @@ -550,7 +544,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x301, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "ISA and extensions", {} } @@ -567,7 +561,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x305, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine trap-handler base address", {} } @@ -584,7 +578,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x306, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine counter enable", {} } @@ -601,7 +595,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x340, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Scratch register for machine trap handlers", {} } @@ -618,7 +612,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x341, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine exception program counter", {} } @@ -635,7 +629,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x342, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine trap cause", {} } @@ -652,7 +646,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x343, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine bad address or instruction", {} } @@ -669,7 +663,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x344, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Machine interrupt pending", {} } @@ -686,7 +680,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B0, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Debug control and status", {} } @@ -703,7 +697,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B1, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Debug program counter", {} } @@ -720,7 +714,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B2, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Debug scratch 0", {} } @@ -737,7 +731,7 @@ namespace Targets::RiscV csrMemorySegmentDescriptor.addressRange.startAddress + 0x7B3, 4, TargetRegisterType::OTHER, - TargetRegisterAccess(true, true), + TargetRegisterAccess{true, true}, "Debug scratch 1", {} }