From 4e373ea45d4d0bcc606d99655dfc4759241ce5e4 Mon Sep 17 00:00:00 2001
From: Nav <nav@navnav.me>
Date: Wed, 13 Dec 2023 20:33:41 +0000
Subject: [PATCH] Tidying AVR8 TDFs

---
 .../AVR8/D-SERIES/AVR128DA28.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DA32.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DA48.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DA64.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DB28.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DB32.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DB48.xml              |     2 +-
 .../AVR8/D-SERIES/AVR128DB64.xml              |     2 +-
 .../AVR8/D-SERIES/AVR16DD14.xml               | 13314 +++++++--------
 .../AVR8/D-SERIES/AVR16DD20.xml               | 13690 +++++++--------
 .../AVR8/D-SERIES/AVR16DD28.xml               | 13996 +++++++--------
 .../AVR8/D-SERIES/AVR16DD32.xml               | 14146 +++++++--------
 .../AVR8/D-SERIES/AVR32DA28.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DA32.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DA48.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DB28.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DB32.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DB48.xml               |     2 +-
 .../AVR8/D-SERIES/AVR32DD14.xml               | 13298 +++++++--------
 .../AVR8/D-SERIES/AVR32DD20.xml               | 13706 +++++++--------
 .../AVR8/D-SERIES/AVR32DD28.xml               | 14012 +++++++--------
 .../AVR8/D-SERIES/AVR32DD32.xml               | 14162 ++++++++--------
 .../AVR8/D-SERIES/AVR64DA28.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DA32.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DA48.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DA64.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DB28.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DB32.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DB48.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DB64.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DD14.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DD20.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DD28.xml               |     2 +-
 .../AVR8/D-SERIES/AVR64DD32.xml               |     2 +-
 .../AVR8/E-SERIES/AVR64EA28.xml               | 12702 +++++++-------
 .../AVR8/E-SERIES/AVR64EA32.xml               | 12870 +++++++-------
 .../AVR8/E-SERIES/AVR64EA48.xml               | 13602 +++++++--------
 .../AVR8/MEGA/AT90CAN128.xml                  |     2 +-
 .../AVR8/MEGA/AT90CAN32.xml                   |     2 +-
 .../AVR8/MEGA/AT90CAN64.xml                   |     2 +-
 .../AVR8/MEGA/AT90PWM1.xml                    |     2 +-
 .../AVR8/MEGA/AT90PWM161.xml                  |     2 +-
 .../AVR8/MEGA/AT90PWM216.xml                  |     2 +-
 .../AVR8/MEGA/AT90PWM2B.xml                   |     2 +-
 .../AVR8/MEGA/AT90PWM316.xml                  |     2 +-
 .../AVR8/MEGA/AT90PWM3B.xml                   |     2 +-
 .../AVR8/MEGA/AT90PWM81.xml                   |     2 +-
 .../AVR8/MEGA/AT90USB1286.xml                 |     2 +-
 .../AVR8/MEGA/AT90USB1287.xml                 |     2 +-
 .../AVR8/MEGA/AT90USB162.xml                  |     2 +-
 .../AVR8/MEGA/AT90USB646.xml                  |     2 +-
 .../AVR8/MEGA/AT90USB647.xml                  |     2 +-
 .../AVR8/MEGA/AT90USB82.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA128.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA1280.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA1281.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA1284.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA1284P.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA1284RFR2.xml              |     2 +-
 .../AVR8/MEGA/ATMEGA128A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA128RFA1.xml               |     2 +-
 .../AVR8/MEGA/ATMEGA128RFR2.xml               |     2 +-
 .../AVR8/MEGA/ATMEGA16.xml                    |     2 +-
 .../AVR8/MEGA/ATMEGA1608.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA1609.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA162.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA164A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA164P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA164PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA165A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA165P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA165PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA168.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA168A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA168P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA168PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA168PB.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA169A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA169P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA169PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA16A.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA16M1.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA16U2.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA16U4.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA2560.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA2561.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA2564RFR2.xml              |     2 +-
 .../AVR8/MEGA/ATMEGA256RFR2.xml               |     2 +-
 .../AVR8/MEGA/ATMEGA32.xml                    |     2 +-
 .../AVR8/MEGA/ATMEGA3208.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA3209.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA324A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA324P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA324PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA324PB.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA325.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA3250.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA3250A.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA3250P.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA3250PA.xml                |     2 +-
 .../AVR8/MEGA/ATMEGA325A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA325P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA325PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA328.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA328P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA328PB.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA329.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA3290.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA3290A.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA3290P.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA3290PA.xml                |     2 +-
 .../AVR8/MEGA/ATMEGA329A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA329P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA329PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA32A.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA32C1.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA32M1.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA32U2.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA32U4.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA406.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA48.xml                    |     2 +-
 .../AVR8/MEGA/ATMEGA4808.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA4809.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA48A.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA48P.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA48PA.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA48PB.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA64.xml                    |     2 +-
 .../AVR8/MEGA/ATMEGA640.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA644.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA644A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA644P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA644PA.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA644RFR2.xml               |     2 +-
 .../AVR8/MEGA/ATMEGA645.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA6450.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA6450A.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA6450P.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA645A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA645P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA649.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA6490.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA6490A.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA6490P.xml                 |     2 +-
 .../AVR8/MEGA/ATMEGA649A.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA649P.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA64A.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA64C1.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA64M1.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA64RFR2.xml                |     2 +-
 .../AVR8/MEGA/ATMEGA808.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA809.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA88.xml                    |     2 +-
 .../AVR8/MEGA/ATMEGA88A.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA88P.xml                   |     2 +-
 .../AVR8/MEGA/ATMEGA88PA.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA88PB.xml                  |     2 +-
 .../AVR8/MEGA/ATMEGA8U2.xml                   |     2 +-
 .../AVR8/TINY/ATTINY13.xml                    |     2 +-
 .../AVR8/TINY/ATTINY13A.xml                   |     2 +-
 .../AVR8/TINY/ATTINY1604.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1606.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1607.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1614.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1616.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1617.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1624.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1626.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1627.xml                  |     2 +-
 .../AVR8/TINY/ATTINY1634.xml                  |     2 +-
 .../AVR8/TINY/ATTINY167.xml                   |     2 +-
 .../AVR8/TINY/ATTINY202.xml                   |     2 +-
 .../AVR8/TINY/ATTINY204.xml                   |     2 +-
 .../AVR8/TINY/ATTINY212.xml                   |     2 +-
 .../AVR8/TINY/ATTINY214.xml                   |     2 +-
 .../AVR8/TINY/ATTINY2313.xml                  |     2 +-
 .../AVR8/TINY/ATTINY2313A.xml                 |     2 +-
 .../AVR8/TINY/ATTINY24.xml                    |     2 +-
 .../AVR8/TINY/ATTINY24A.xml                   |     2 +-
 .../AVR8/TINY/ATTINY25.xml                    |     2 +-
 .../AVR8/TINY/ATTINY261.xml                   |     2 +-
 .../AVR8/TINY/ATTINY261A.xml                  |     2 +-
 .../AVR8/TINY/ATTINY3216.xml                  |     2 +-
 .../AVR8/TINY/ATTINY3217.xml                  |     2 +-
 .../AVR8/TINY/ATTINY402.xml                   |     2 +-
 .../AVR8/TINY/ATTINY404.xml                   |     2 +-
 .../AVR8/TINY/ATTINY406.xml                   |     2 +-
 .../AVR8/TINY/ATTINY412.xml                   |     2 +-
 .../AVR8/TINY/ATTINY414.xml                   |     2 +-
 .../AVR8/TINY/ATTINY416.xml                   |     2 +-
 .../AVR8/TINY/ATTINY417.xml                   |     2 +-
 .../AVR8/TINY/ATTINY4313.xml                  |     2 +-
 .../AVR8/TINY/ATTINY43U.xml                   |     2 +-
 .../AVR8/TINY/ATTINY44.xml                    |     2 +-
 .../AVR8/TINY/ATTINY441.xml                   |     2 +-
 .../AVR8/TINY/ATTINY44A.xml                   |     2 +-
 .../AVR8/TINY/ATTINY45.xml                    |     2 +-
 .../AVR8/TINY/ATTINY461.xml                   |     2 +-
 .../AVR8/TINY/ATTINY461A.xml                  |     2 +-
 .../AVR8/TINY/ATTINY48.xml                    |     2 +-
 .../AVR8/TINY/ATTINY804.xml                   |     2 +-
 .../AVR8/TINY/ATTINY806.xml                   |     2 +-
 .../AVR8/TINY/ATTINY807.xml                   |     2 +-
 .../AVR8/TINY/ATTINY814.xml                   |     2 +-
 .../AVR8/TINY/ATTINY816.xml                   |     2 +-
 .../AVR8/TINY/ATTINY817.xml                   |     2 +-
 .../AVR8/TINY/ATTINY828.xml                   |     2 +-
 .../AVR8/TINY/ATTINY84.xml                    |     2 +-
 .../AVR8/TINY/ATTINY841.xml                   |     2 +-
 .../AVR8/TINY/ATTINY84A.xml                   |     2 +-
 .../AVR8/TINY/ATTINY85.xml                    |     2 +-
 .../AVR8/TINY/ATTINY861.xml                   |     2 +-
 .../AVR8/TINY/ATTINY861A.xml                  |     2 +-
 .../AVR8/TINY/ATTINY87.xml                    |     2 +-
 .../AVR8/TINY/ATTINY88.xml                    |     2 +-
 .../AVR8/XMEGA/ATXMEGA128A1.xml               |     6 +-
 .../AVR8/XMEGA/ATXMEGA128A1U.xml              |     6 +-
 .../AVR8/XMEGA/ATXMEGA128A3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA128A3U.xml              |     2 +-
 .../AVR8/XMEGA/ATXMEGA128A4U.xml              |     2 +-
 .../AVR8/XMEGA/ATXMEGA128B1.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA128B3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA128C3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA128D3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA128D4.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA16A4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA16A4U.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA16C4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA16D4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA16E5.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA192A3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA192A3U.xml              |     2 +-
 .../AVR8/XMEGA/ATXMEGA192C3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA192D3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA256A3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA256A3B.xml              |     2 +-
 .../AVR8/XMEGA/ATXMEGA256A3BU.xml             |     2 +-
 .../AVR8/XMEGA/ATXMEGA256A3U.xml              |     2 +-
 .../AVR8/XMEGA/ATXMEGA256C3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA256D3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA32A4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA32A4U.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA32C3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA32C4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA32D3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA32D4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA32E5.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA384C3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA384D3.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA64A1.xml                |     6 +-
 .../AVR8/XMEGA/ATXMEGA64A1U.xml               |     6 +-
 .../AVR8/XMEGA/ATXMEGA64A3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA64A3U.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA64A4U.xml               |     2 +-
 .../AVR8/XMEGA/ATXMEGA64B1.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA64B3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA64C3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA64D3.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA64D4.xml                |     2 +-
 .../AVR8/XMEGA/ATXMEGA8E5.xml                 |     2 +-
 260 files changed, 75006 insertions(+), 75006 deletions(-)

diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA28.xml
index 95269faf..76af2fde 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DA28" package="SOIC28" pinout="SOIC28" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR128DA28" family="AVR8">
+    <device name="AVR128DA28" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA32.xml
index da0c0530..56a12058 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DA32" package="QFN32" pinout="QFN32" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR128DA32" family="AVR8">
+    <device name="AVR128DA32" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA48.xml
index da8e325b..a753506b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DA48" package="QFN48" pinout="QFN48" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR128DA48" family="AVR8">
+    <device name="AVR128DA48" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA64.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA64.xml
index 7e6967c0..7da4c4e5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DA64.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DA64" package="QFN64" pinout="QFN64" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR128DA64" family="AVR8">
+    <device name="AVR128DA64" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB28.xml
index 7dcb8a76..13851d23 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DB28" package="SOIC28" pinout="SOIC28" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR128DB28" family="AVR8">
+    <device name="AVR128DB28" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB32.xml
index ed0d8166..c7cdaa07 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DB32" package="QFN32" pinout="QFN32" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR128DB32" family="AVR8">
+    <device name="AVR128DB32" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB48.xml
index 77a32941..61a9b741 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DB48" package="QFN48" pinout="QFN48" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR128DB48" family="AVR8">
+    <device name="AVR128DB48" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB64.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB64.xml
index 9be279f4..6624de49 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR128DB64.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR128DB64" package="QFN64" pinout="QFN64" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR128DB64" family="AVR8">
+    <device name="AVR128DB64" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD14.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD14.xml
index 51aa99b8..37b37876 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD14.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD14.xml
@@ -1,6660 +1,6660 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR16DD14"
-               package="SOIC14"
-               pinout="SOIC14MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR16DD14" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x800"
-                            start="0x7800"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x4000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
-         <property-group name="OCD_FEATURES">
-            <property name="BREAK_PIN" value="PF6"/>
-            <property name="BREAK_PIN_ALT" value="PF2"/>
-         </property-group>
-         <property-group name="PROGRAMMING_INFO">
-            <property name="FUSE_ENABLED_VALUE" value="1"/>
-         </property-group>
-         <property-group name="UPDI_INTERFACE">
-            <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-            <property name="HV_IMPLEMENTATION" value="2"/>
-            <property name="PROGMEM_OFFSET" value="0x00800000"/>
-         </property-group>
-         <property-group name="SIGNATURES">
-            <property name="SIGNATURE0" value="0x1E"/>
-            <property name="SIGNATURE1" value="0x94"/>
-            <property name="SIGNATURE2" value="0x34"/>
-         </property-group>
-      </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="SOIC14MVIO">
-         <pin pad="AGND" position="1"/>
-         <pin pad="PF6" position="2"/>
-         <pin pad="PF7" position="3"/>
-         <pin pad="PA0" position="4"/>
-         <pin pad="PA1" position="5"/>
-         <pin pad="PC1" position="6"/>
-         <pin pad="PC2" position="7"/>
-         <pin pad="PC3" position="8"/>
-         <pin pad="VDDIO2" position="9"/>
-         <pin pad="PD4" position="10"/>
-         <pin pad="PD5" position="11"/>
-         <pin pad="PD6" position="12"/>
-         <pin pad="PD7" position="13"/>
-         <pin pad="AVDD" position="14"/>
-      </pinout>
-   </pinouts>
+    <variants>
+        <variant ordercode="AVR16DD14"
+                 package="SOIC14"
+                 pinout="SOIC14MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR16DD14" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x800"
+                                start="0x7800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x4000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
+            <property-group name="OCD_FEATURES">
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
+            </property-group>
+            <property-group name="PROGRAMMING_INFO">
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
+            </property-group>
+            <property-group name="UPDI_INTERFACE">
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
+            </property-group>
+            <property-group name="SIGNATURES">
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x94"/>
+                <property name="SIGNATURE2" value="0x34"/>
+            </property-group>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="SOIC14MVIO">
+            <pin pad="AGND" position="1"/>
+            <pin pad="PF6" position="2"/>
+            <pin pad="PF7" position="3"/>
+            <pin pad="PA0" position="4"/>
+            <pin pad="PA1" position="5"/>
+            <pin pad="PC1" position="6"/>
+            <pin pad="PC2" position="7"/>
+            <pin pad="PC3" position="8"/>
+            <pin pad="VDDIO2" position="9"/>
+            <pin pad="PD4" position="10"/>
+            <pin pad="PD5" position="11"/>
+            <pin pad="PD6" position="12"/>
+            <pin pad="PD7" position="13"/>
+            <pin pad="AVDD" position="14"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD20.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD20.xml
index 1a293345..cad612af 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD20.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD20.xml
@@ -1,6856 +1,6856 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR16DD20"
-               package="QFN20"
-               pinout="QFN20MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR16DD20" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x800"
-                            start="0x7800"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x4000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
+    <variants>
+        <variant ordercode="AVR16DD20"
+                 package="QFN20"
+                 pinout="QFN20MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR16DD20" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x800"
+                                start="0x7800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x4000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
             <property-group name="OCD_FEATURES">
-               <property name="BREAK_PIN" value="PF6"/>
-               <property name="BREAK_PIN_ALT" value="PF2"/>
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
             </property-group>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x94"/>
-               <property name="SIGNATURE2" value="0x33"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x94"/>
+                <property name="SIGNATURE2" value="0x33"/>
             </property-group>
-         </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN20MVIO">
-         <pin pad="PA4" position="1"/>
-         <pin pad="PA5" position="2"/>
-         <pin pad="PA6" position="3"/>
-         <pin pad="PA7" position="4"/>
-         <pin pad="PC1" position="5"/>
-         <pin pad="PC2" position="6"/>
-         <pin pad="PC3" position="7"/>
-         <pin pad="VDDIO2" position="8"/>
-         <pin pad="PD4" position="9"/>
-         <pin pad="PD5" position="10"/>
-         <pin pad="PD6" position="11"/>
-         <pin pad="PD7" position="12"/>
-         <pin pad="AVDD" position="13"/>
-         <pin pad="AGND" position="14"/>
-         <pin pad="PF6" position="15"/>
-         <pin pad="PF7" position="16"/>
-         <pin pad="PA0" position="17"/>
-         <pin pad="PA1" position="18"/>
-         <pin pad="PA2" position="19"/>
-         <pin pad="PA3" position="20"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN20MVIO">
+            <pin pad="PA4" position="1"/>
+            <pin pad="PA5" position="2"/>
+            <pin pad="PA6" position="3"/>
+            <pin pad="PA7" position="4"/>
+            <pin pad="PC1" position="5"/>
+            <pin pad="PC2" position="6"/>
+            <pin pad="PC3" position="7"/>
+            <pin pad="VDDIO2" position="8"/>
+            <pin pad="PD4" position="9"/>
+            <pin pad="PD5" position="10"/>
+            <pin pad="PD6" position="11"/>
+            <pin pad="PD7" position="12"/>
+            <pin pad="AVDD" position="13"/>
+            <pin pad="AGND" position="14"/>
+            <pin pad="PF6" position="15"/>
+            <pin pad="PF7" position="16"/>
+            <pin pad="PA0" position="17"/>
+            <pin pad="PA1" position="18"/>
+            <pin pad="PA2" position="19"/>
+            <pin pad="PA3" position="20"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD28.xml
index 4847c3b8..e20e3fb6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD28.xml
@@ -1,7009 +1,7009 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR16DD28"
-               package="SOIC28"
-               pinout="SOIC28MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR16DD28" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x800"
-                            start="0x7800"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x4000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="0" pad="PD3"/>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="0" pad="PD2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
-                  <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
-                  <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
-                  <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="1"
-                          pad="PF1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
-                  <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SCK"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MOSI"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="3"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="1"
-                          pad="PF1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB2"
-                          function="TCB2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOA"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOB"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="TXD"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
+    <variants>
+        <variant ordercode="AVR16DD28"
+                 package="SOIC28"
+                 pinout="SOIC28MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR16DD28" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x800"
+                                start="0x7800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x4000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="0" pad="PD3"/>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="0" pad="PD2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
+                        <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
+                        <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
+                        <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="1"
+                                pad="PF1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
+                        <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="TCB2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOA"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOB"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
             <property-group name="OCD_FEATURES">
-               <property name="BREAK_PIN" value="PF6"/>
-               <property name="BREAK_PIN_ALT" value="PF2"/>
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
             </property-group>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x94"/>
-               <property name="SIGNATURE2" value="0x32"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x94"/>
+                <property name="SIGNATURE2" value="0x32"/>
             </property-group>
-         </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PB4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="SOIC28MVIO">
-         <pin pad="PA7" position="1"/>
-         <pin pad="PC0" position="2"/>
-         <pin pad="PC1" position="3"/>
-         <pin pad="PC2" position="4"/>
-         <pin pad="PC3" position="5"/>
-         <pin pad="VDDIO2" position="6"/>
-         <pin pad="PD1" position="7"/>
-         <pin pad="PD2" position="8"/>
-         <pin pad="PD3" position="9"/>
-         <pin pad="PD4" position="10"/>
-         <pin pad="PD5" position="11"/>
-         <pin pad="PD6" position="12"/>
-         <pin pad="PD7" position="13"/>
-         <pin pad="AVDD" position="14"/>
-         <pin pad="AGND" position="15"/>
-         <pin pad="PF0" position="16"/>
-         <pin pad="PF1" position="17"/>
-         <pin pad="PF6" position="18"/>
-         <pin pad="PF7" position="19"/>
-         <pin pad="VDD0" position="20"/>
-         <pin pad="GND0" position="21"/>
-         <pin pad="PA0" position="22"/>
-         <pin pad="PA1" position="23"/>
-         <pin pad="PA2" position="24"/>
-         <pin pad="PA3" position="25"/>
-         <pin pad="PA4" position="26"/>
-         <pin pad="PA5" position="27"/>
-         <pin pad="PA6" position="28"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PB4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="SOIC28MVIO">
+            <pin pad="PA7" position="1"/>
+            <pin pad="PC0" position="2"/>
+            <pin pad="PC1" position="3"/>
+            <pin pad="PC2" position="4"/>
+            <pin pad="PC3" position="5"/>
+            <pin pad="VDDIO2" position="6"/>
+            <pin pad="PD1" position="7"/>
+            <pin pad="PD2" position="8"/>
+            <pin pad="PD3" position="9"/>
+            <pin pad="PD4" position="10"/>
+            <pin pad="PD5" position="11"/>
+            <pin pad="PD6" position="12"/>
+            <pin pad="PD7" position="13"/>
+            <pin pad="AVDD" position="14"/>
+            <pin pad="AGND" position="15"/>
+            <pin pad="PF0" position="16"/>
+            <pin pad="PF1" position="17"/>
+            <pin pad="PF6" position="18"/>
+            <pin pad="PF7" position="19"/>
+            <pin pad="VDD0" position="20"/>
+            <pin pad="GND0" position="21"/>
+            <pin pad="PA0" position="22"/>
+            <pin pad="PA1" position="23"/>
+            <pin pad="PA2" position="24"/>
+            <pin pad="PA3" position="25"/>
+            <pin pad="PA4" position="26"/>
+            <pin pad="PA5" position="27"/>
+            <pin pad="PA6" position="28"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD32.xml
index 240231e3..0a8c832f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR16DD32.xml
@@ -1,7084 +1,7084 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR16DD32"
-               package="QFN32"
-               pinout="QFN32MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR16DD32" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x800"
-                            start="0x7800"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x4000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x4000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="0" pad="PD3"/>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="0" pad="PD2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
-                  <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
-                  <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
-                  <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
-                  <signal function="AIN0" group="AIN" index="18" pad="PF2"/>
-                  <signal function="AIN0" group="AIN" index="19" pad="PF3"/>
-                  <signal function="AIN0" group="AIN" index="20" pad="PF4"/>
-                  <signal function="AIN0" group="AIN" index="21" pad="PF5"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_OUT"
-                          index="0"
-                          pad="PF3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
-                  <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SCK"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MOSI"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="3"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="3"
-                          pad="PF3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="4"
-                          pad="PF4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="5"
-                          pad="PF5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0_ALT1"
-                          group="WO"
-                          index="0"
-                          pad="PF4"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1_ALT1"
-                          group="WO"
-                          index="0"
-                          pad="PF5"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB2"
-                          function="TCB2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOA"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOB"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOC"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOD"
-                          index="3"
-                          pad="PF3"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="TXD"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
+    <variants>
+        <variant ordercode="AVR16DD32"
+                 package="QFN32"
+                 pinout="QFN32MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR16DD32" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x800"
+                                start="0x7800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x4000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x4000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="0" pad="PD3"/>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="0" pad="PD2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
+                        <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
+                        <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
+                        <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
+                        <signal function="AIN0" group="AIN" index="18" pad="PF2"/>
+                        <signal function="AIN0" group="AIN" index="19" pad="PF3"/>
+                        <signal function="AIN0" group="AIN" index="20" pad="PF4"/>
+                        <signal function="AIN0" group="AIN" index="21" pad="PF5"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_OUT"
+                                index="0"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
+                        <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="4"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="5"
+                                pad="PF5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0_ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF4"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1_ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF5"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="TCB2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOA"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOB"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOC"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOD"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
             <property-group name="OCD_FEATURES">
-               <property name="BREAK_PIN" value="PF6"/>
-               <property name="BREAK_PIN_ALT" value="PF2"/>
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
             </property-group>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x94"/>
-               <property name="SIGNATURE2" value="0x31"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x94"/>
+                <property name="SIGNATURE2" value="0x31"/>
             </property-group>
-         </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
-            <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
-            <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
-            <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
-            <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
-            <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
-            <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PB4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN32MVIO">
-         <pin pad="PA3" position="1"/>
-         <pin pad="PA4" position="2"/>
-         <pin pad="PA5" position="3"/>
-         <pin pad="PA6" position="4"/>
-         <pin pad="PA7" position="5"/>
-         <pin pad="PC0" position="6"/>
-         <pin pad="PC1" position="7"/>
-         <pin pad="PC2" position="8"/>
-         <pin pad="PC3" position="9"/>
-         <pin pad="VDDIO2" position="10"/>
-         <pin pad="PD1" position="11"/>
-         <pin pad="PD2" position="12"/>
-         <pin pad="PD3" position="13"/>
-         <pin pad="PD4" position="14"/>
-         <pin pad="PD5" position="15"/>
-         <pin pad="PD6" position="16"/>
-         <pin pad="PD7" position="17"/>
-         <pin pad="AVDD" position="18"/>
-         <pin pad="AGND" position="19"/>
-         <pin pad="PF0" position="20"/>
-         <pin pad="PF1" position="21"/>
-         <pin pad="PF2" position="22"/>
-         <pin pad="PF3" position="23"/>
-         <pin pad="PF4" position="24"/>
-         <pin pad="PF5" position="25"/>
-         <pin pad="PF6" position="26"/>
-         <pin pad="PF7" position="27"/>
-         <pin pad="VDD0" position="28"/>
-         <pin pad="GND0" position="29"/>
-         <pin pad="PA0" position="30"/>
-         <pin pad="PA1" position="31"/>
-         <pin pad="PA2" position="32"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
+                <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
+                <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
+                <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
+                <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
+                <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
+                <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PB4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN32MVIO">
+            <pin pad="PA3" position="1"/>
+            <pin pad="PA4" position="2"/>
+            <pin pad="PA5" position="3"/>
+            <pin pad="PA6" position="4"/>
+            <pin pad="PA7" position="5"/>
+            <pin pad="PC0" position="6"/>
+            <pin pad="PC1" position="7"/>
+            <pin pad="PC2" position="8"/>
+            <pin pad="PC3" position="9"/>
+            <pin pad="VDDIO2" position="10"/>
+            <pin pad="PD1" position="11"/>
+            <pin pad="PD2" position="12"/>
+            <pin pad="PD3" position="13"/>
+            <pin pad="PD4" position="14"/>
+            <pin pad="PD5" position="15"/>
+            <pin pad="PD6" position="16"/>
+            <pin pad="PD7" position="17"/>
+            <pin pad="AVDD" position="18"/>
+            <pin pad="AGND" position="19"/>
+            <pin pad="PF0" position="20"/>
+            <pin pad="PF1" position="21"/>
+            <pin pad="PF2" position="22"/>
+            <pin pad="PF3" position="23"/>
+            <pin pad="PF4" position="24"/>
+            <pin pad="PF5" position="25"/>
+            <pin pad="PF6" position="26"/>
+            <pin pad="PF7" position="27"/>
+            <pin pad="VDD0" position="28"/>
+            <pin pad="GND0" position="29"/>
+            <pin pad="PA0" position="30"/>
+            <pin pad="PA1" position="31"/>
+            <pin pad="PA2" position="32"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA28.xml
index c5b5ee24..cb4cae8e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DA28" package="SOIC28" pinout="SOIC28" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR32DA28" family="AVR8">
+    <device name="AVR32DA28" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA32.xml
index 3662d540..ddfdd4e5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DA32" package="QFN32" pinout="QFN32" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR32DA32" family="AVR8">
+    <device name="AVR32DA32" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA48.xml
index 4d07f115..fb3d16d5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DA48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DA48" package="QFN48" pinout="QFN48" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR32DA48" family="AVR8">
+    <device name="AVR32DA48" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB28.xml
index c44704bb..ca48c228 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DB28" package="SOIC28" pinout="SOIC28" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR32DB28" family="AVR8">
+    <device name="AVR32DB28" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB32.xml
index 872070c2..88f383b5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DB32" package="QFN32" pinout="QFN32" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR32DB32" family="AVR8">
+    <device name="AVR32DB32" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB48.xml
index fd54bc2d..61ca123e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DB48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR32DB48" package="QFN48" pinout="QFN48" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR32DB48" family="AVR8">
+    <device name="AVR32DB48" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD14.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD14.xml
index 1b9d6891..ce13931d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD14.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD14.xml
@@ -1,6660 +1,6660 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR32DD14"
-               package="SOIC14"
-               pinout="SOIC14MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR32DD14" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x1000"
-                            start="0x7000"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x8000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
+    <variants>
+        <variant ordercode="AVR32DD14"
+                 package="SOIC14"
+                 pinout="SOIC14MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR32DD14" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1000"
+                                start="0x7000"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x8000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
             <property-group name="OCD_FEATURES">
-               <property name="BREAK_PIN" value="PF6"/>
-               <property name="BREAK_PIN_ALT" value="PF2"/>
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
             </property-group>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x95"/>
-               <property name="SIGNATURE2" value="0x3B"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x95"/>
+                <property name="SIGNATURE2" value="0x3B"/>
             </property-group>
-         </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="SOIC14MVIO">
-         <pin pad="AGND" position="1"/>
-         <pin pad="PF6" position="2"/>
-         <pin pad="PF7" position="3"/>
-         <pin pad="PA0" position="4"/>
-         <pin pad="PA1" position="5"/>
-         <pin pad="PC1" position="6"/>
-         <pin pad="PC2" position="7"/>
-         <pin pad="PC3" position="8"/>
-         <pin pad="VDDIO2" position="9"/>
-         <pin pad="PD4" position="10"/>
-         <pin pad="PD5" position="11"/>
-         <pin pad="PD6" position="12"/>
-         <pin pad="PD7" position="13"/>
-         <pin pad="AVDD" position="14"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="SOIC14MVIO">
+            <pin pad="AGND" position="1"/>
+            <pin pad="PF6" position="2"/>
+            <pin pad="PF7" position="3"/>
+            <pin pad="PA0" position="4"/>
+            <pin pad="PA1" position="5"/>
+            <pin pad="PC1" position="6"/>
+            <pin pad="PC2" position="7"/>
+            <pin pad="PC3" position="8"/>
+            <pin pad="VDDIO2" position="9"/>
+            <pin pad="PD4" position="10"/>
+            <pin pad="PD5" position="11"/>
+            <pin pad="PD6" position="12"/>
+            <pin pad="PD7" position="13"/>
+            <pin pad="AVDD" position="14"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD20.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD20.xml
index 139ae2a4..95105dcb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD20.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD20.xml
@@ -1,6856 +1,6856 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR32DD20"
-               package="QFN20"
-               pinout="QFN20MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR32DD20" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x1000"
-                            start="0x7000"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x8000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
-         <property-group name="OCD_FEATURES">
-            <property name="BREAK_PIN" value="PF6"/>
-            <property name="BREAK_PIN_ALT" value="PF2"/>
-         </property-group>
-         <property-group name="PROGRAMMING_INFO">
-            <property name="FUSE_ENABLED_VALUE" value="1"/>
-         </property-group>
-         <property-group name="UPDI_INTERFACE">
-            <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-            <property name="HV_IMPLEMENTATION" value="2"/>
-            <property name="PROGMEM_OFFSET" value="0x00800000"/>
-         </property-group>
-         <property-group name="SIGNATURES">
-            <property name="SIGNATURE0" value="0x1E"/>
-            <property name="SIGNATURE1" value="0x95"/>
-            <property name="SIGNATURE2" value="0x3A"/>
-         </property-group>
-      </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN20MVIO">
-         <pin pad="PA4" position="1"/>
-         <pin pad="PA5" position="2"/>
-         <pin pad="PA6" position="3"/>
-         <pin pad="PA7" position="4"/>
-         <pin pad="PC1" position="5"/>
-         <pin pad="PC2" position="6"/>
-         <pin pad="PC3" position="7"/>
-         <pin pad="VDDIO2" position="8"/>
-         <pin pad="PD4" position="9"/>
-         <pin pad="PD5" position="10"/>
-         <pin pad="PD6" position="11"/>
-         <pin pad="PD7" position="12"/>
-         <pin pad="AVDD" position="13"/>
-         <pin pad="AGND" position="14"/>
-         <pin pad="PF6" position="15"/>
-         <pin pad="PF7" position="16"/>
-         <pin pad="PA0" position="17"/>
-         <pin pad="PA1" position="18"/>
-         <pin pad="PA2" position="19"/>
-         <pin pad="PA3" position="20"/>
-      </pinout>
-   </pinouts>
+    <variants>
+        <variant ordercode="AVR32DD20"
+                 package="QFN20"
+                 pinout="QFN20MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR32DD20" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1000"
+                                start="0x7000"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x8000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
+            <property-group name="OCD_FEATURES">
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
+            </property-group>
+            <property-group name="PROGRAMMING_INFO">
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
+            </property-group>
+            <property-group name="UPDI_INTERFACE">
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
+            </property-group>
+            <property-group name="SIGNATURES">
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x95"/>
+                <property name="SIGNATURE2" value="0x3A"/>
+            </property-group>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN20MVIO">
+            <pin pad="PA4" position="1"/>
+            <pin pad="PA5" position="2"/>
+            <pin pad="PA6" position="3"/>
+            <pin pad="PA7" position="4"/>
+            <pin pad="PC1" position="5"/>
+            <pin pad="PC2" position="6"/>
+            <pin pad="PC3" position="7"/>
+            <pin pad="VDDIO2" position="8"/>
+            <pin pad="PD4" position="9"/>
+            <pin pad="PD5" position="10"/>
+            <pin pad="PD6" position="11"/>
+            <pin pad="PD7" position="12"/>
+            <pin pad="AVDD" position="13"/>
+            <pin pad="AGND" position="14"/>
+            <pin pad="PF6" position="15"/>
+            <pin pad="PF7" position="16"/>
+            <pin pad="PA0" position="17"/>
+            <pin pad="PA1" position="18"/>
+            <pin pad="PA2" position="19"/>
+            <pin pad="PA3" position="20"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD28.xml
index df89b664..915c7c3c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD28.xml
@@ -1,7009 +1,7009 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR32DD28"
-               package="SOIC28"
-               pinout="SOIC28MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR32DD28" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x1000"
-                            start="0x7000"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x8000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="0" pad="PD3"/>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="0" pad="PD2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
-                  <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
-                  <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
-                  <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="1"
-                          pad="PF1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
-                  <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SCK"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MOSI"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="3"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="1"
-                          pad="PF1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB2"
-                          function="TCB2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOA"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOB"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="TXD"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
-         <property-group name="OCD_FEATURES">
-            <property name="BREAK_PIN" value="PF6"/>
-            <property name="BREAK_PIN_ALT" value="PF2"/>
-         </property-group>
-         <property-group name="PROGRAMMING_INFO">
-            <property name="FUSE_ENABLED_VALUE" value="1"/>
-         </property-group>
-         <property-group name="UPDI_INTERFACE">
-            <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-            <property name="HV_IMPLEMENTATION" value="2"/>
-            <property name="PROGMEM_OFFSET" value="0x00800000"/>
-         </property-group>
-         <property-group name="SIGNATURES">
-            <property name="SIGNATURE0" value="0x1E"/>
-            <property name="SIGNATURE1" value="0x95"/>
-            <property name="SIGNATURE2" value="0x39"/>
-         </property-group>
-      </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PB4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="SOIC28MVIO">
-         <pin pad="PA7" position="1"/>
-         <pin pad="PC0" position="2"/>
-         <pin pad="PC1" position="3"/>
-         <pin pad="PC2" position="4"/>
-         <pin pad="PC3" position="5"/>
-         <pin pad="VDDIO2" position="6"/>
-         <pin pad="PD1" position="7"/>
-         <pin pad="PD2" position="8"/>
-         <pin pad="PD3" position="9"/>
-         <pin pad="PD4" position="10"/>
-         <pin pad="PD5" position="11"/>
-         <pin pad="PD6" position="12"/>
-         <pin pad="PD7" position="13"/>
-         <pin pad="AVDD" position="14"/>
-         <pin pad="AGND" position="15"/>
-         <pin pad="PF0" position="16"/>
-         <pin pad="PF1" position="17"/>
-         <pin pad="PF6" position="18"/>
-         <pin pad="PF7" position="19"/>
-         <pin pad="VDD0" position="20"/>
-         <pin pad="GND0" position="21"/>
-         <pin pad="PA0" position="22"/>
-         <pin pad="PA1" position="23"/>
-         <pin pad="PA2" position="24"/>
-         <pin pad="PA3" position="25"/>
-         <pin pad="PA4" position="26"/>
-         <pin pad="PA5" position="27"/>
-         <pin pad="PA6" position="28"/>
-      </pinout>
-   </pinouts>
+    <variants>
+        <variant ordercode="AVR32DD28"
+                 package="SOIC28"
+                 pinout="SOIC28MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR32DD28" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1000"
+                                start="0x7000"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x8000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="0" pad="PD3"/>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="0" pad="PD2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
+                        <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
+                        <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
+                        <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="1"
+                                pad="PF1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
+                        <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="TCB2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOA"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOB"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
+            <property-group name="OCD_FEATURES">
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
+            </property-group>
+            <property-group name="PROGRAMMING_INFO">
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
+            </property-group>
+            <property-group name="UPDI_INTERFACE">
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
+            </property-group>
+            <property-group name="SIGNATURES">
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x95"/>
+                <property name="SIGNATURE2" value="0x39"/>
+            </property-group>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PB4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="SOIC28MVIO">
+            <pin pad="PA7" position="1"/>
+            <pin pad="PC0" position="2"/>
+            <pin pad="PC1" position="3"/>
+            <pin pad="PC2" position="4"/>
+            <pin pad="PC3" position="5"/>
+            <pin pad="VDDIO2" position="6"/>
+            <pin pad="PD1" position="7"/>
+            <pin pad="PD2" position="8"/>
+            <pin pad="PD3" position="9"/>
+            <pin pad="PD4" position="10"/>
+            <pin pad="PD5" position="11"/>
+            <pin pad="PD6" position="12"/>
+            <pin pad="PD7" position="13"/>
+            <pin pad="AVDD" position="14"/>
+            <pin pad="AGND" position="15"/>
+            <pin pad="PF0" position="16"/>
+            <pin pad="PF1" position="17"/>
+            <pin pad="PF6" position="18"/>
+            <pin pad="PF7" position="19"/>
+            <pin pad="VDD0" position="20"/>
+            <pin pad="GND0" position="21"/>
+            <pin pad="PA0" position="22"/>
+            <pin pad="PA1" position="23"/>
+            <pin pad="PA2" position="24"/>
+            <pin pad="PA3" position="25"/>
+            <pin pad="PA4" position="26"/>
+            <pin pad="PA5" position="27"/>
+            <pin pad="PA6" position="28"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD32.xml
index 323aca5c..c0a6a5cb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR32DD32.xml
@@ -1,7084 +1,7084 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR32DD32"
-               package="QFN32"
-               pinout="QFN32MVIO"
-               speedmax="32000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR DD" name="AVR32DD32" family="AVR8">
-      <address-spaces>
-         <address-space endianness="little"
-                        id="data"
-                        name="data"
-                        size="0x10000"
-                        start="0x0000">
-            <memory-segment exec="0"
-                            name="IO"
-                            rw="RW"
-                            size="0x103F"
-                            start="0x00"
-                            type="io"/>
-            <memory-segment exec="0"
-                            name="LOCKBITS"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x04"
-                            start="0x1040"
-                            type="lockbits"/>
-            <memory-segment exec="0"
-                            name="FUSES"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x10"
-                            start="0x1050"
-                            type="fuses"/>
-            <memory-segment exec="0"
-                            name="USER_SIGNATURES"
-                            pagesize="0x20"
-                            rw="RW"
-                            size="0x20"
-                            start="0x1080"
-                            type="user_signatures"/>
-            <memory-segment exec="0"
-                            name="SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x03"
-                            start="0x1100"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="PROD_SIGNATURES"
-                            pagesize="0x80"
-                            rw="R"
-                            size="0x7D"
-                            start="0x1103"
-                            type="signatures"/>
-            <memory-segment exec="0"
-                            name="EEPROM"
-                            pagesize="0x1"
-                            rw="RW"
-                            size="0x100"
-                            start="0x1400"
-                            type="eeprom"/>
-            <memory-segment exec="0"
-                            name="INTERNAL_SRAM"
-                            rw="RW"
-                            size="0x1000"
-                            start="0x7000"
-                            type="ram"/>
-            <memory-segment exec="0"
-                            name="MAPPED_PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x8000"
-                            type="other"/>
-         </address-space>
-         <address-space endianness="little"
-                        id="prog"
-                        name="prog"
-                        size="0x8000"
-                        start="0x0000">
-            <memory-segment exec="1"
-                            name="PROGMEM"
-                            pagesize="0x200"
-                            rw="RW"
-                            size="0x8000"
-                            start="0x00"
-                            type="flash"/>
-         </address-space>
-      </address-spaces>
-      <peripherals>
-         <module id="cmp_control_v8" name="AC">
-            <instance name="AC0">
-               <register-group address-space="data"
-                               name="AC0"
-                               name-in-module="AC"
-                               offset="0x0680"/>
-               <signals>
-                  <signal function="AC0" group="N" index="0" pad="PD3"/>
-                  <signal function="AC0" group="N" index="2" pad="PD7"/>
-                  <signal function="AC0" group="N" index="3" pad="PC2"/>
-                  <signal function="AC0" group="P" index="0" pad="PD2"/>
-                  <signal function="AC0" group="P" index="3" pad="PD6"/>
-                  <signal function="AC0" group="P" index="4" pad="PC3"/>
-                  <signal field="PORTMUX.ACROUTEA.AC0"
-                          function="AC0"
-                          group="OUT"
-                          index="0"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="adc_12b_diff_ctrl_v1" name="ADC">
-            <instance name="ADC0">
-               <register-group address-space="data"
-                               name="ADC0"
-                               name-in-module="ADC"
-                               offset="0x0600"/>
-               <signals>
-                  <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
-                  <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
-                  <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
-                  <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
-                  <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
-                  <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
-                  <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
-                  <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
-                  <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
-                  <signal function="AIN0" group="AIN" index="18" pad="PF2"/>
-                  <signal function="AIN0" group="AIN" index="19" pad="PF3"/>
-                  <signal function="AIN0" group="AIN" index="20" pad="PF4"/>
-                  <signal function="AIN0" group="AIN" index="21" pad="PF5"/>
-                  <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
-                  <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
-                  <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
-                  <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
-                  <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
-                  <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
-                  <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
-                  <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
-                  <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
-                  <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="bor_lvd_ctrl_v1" name="BOD">
-            <instance name="BOD">
-               <register-group address-space="data"
-                               name="BOD"
-                               name-in-module="BOD"
-                               offset="0x00A0"/>
-            </instance>
-         </module>
-         <module id="cla_ccl_v1" name="CCL">
-            <instance name="CCL">
-               <register-group address-space="data"
-                               name="CCL"
-                               name-in-module="CCL"
-                               offset="0x01C0"/>
-               <signals>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_IN"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT0"
-                          function="CCL_ALT1"
-                          group="LUT0_OUT"
-                          index="0"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL"
-                          group="LUT1_OUT"
-                          index="0"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT1"
-                          function="CCL_ALT1"
-                          group="LUT1_IN"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_IN"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT2"
-                          function="CCL_ALT1"
-                          group="LUT2_OUT"
-                          index="0"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_IN"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.CCLROUTEA.LUT3"
-                          function="CCL"
-                          group="LUT3_OUT"
-                          index="0"
-                          pad="PF3"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="CLKCTRL">
-            <instance name="CLKCTRL">
-               <register-group address-space="data"
-                               name="CLKCTRL"
-                               name-in-module="CLKCTRL"
-                               offset="0x0060"/>
-               <signals>
-                  <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
-                  <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
-                  <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
-                  <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
-                  <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
-                  <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="cpu_avr_xt_v1" name="CPU">
-            <instance name="CPU">
-               <register-group address-space="data"
-                               name="CPU"
-                               name-in-module="CPU"
-                               offset="0x0030"/>
-               <parameters>
-                  <param name="CORE_VERSION" value="V4S"/>
-               </parameters>
-            </instance>
-         </module>
-         <module id="int_8bit_v3" name="CPUINT">
-            <instance name="CPUINT">
-               <register-group address-space="data"
-                               name="CPUINT"
-                               name-in-module="CPUINT"
-                               offset="0x0110"/>
-            </instance>
-         </module>
-         <module id="math_pdi_crc_v1" name="CRCSCAN">
-            <instance name="CRCSCAN">
-               <register-group address-space="data"
-                               name="CRCSCAN"
-                               name-in-module="CRCSCAN"
-                               offset="0x0120"/>
-            </instance>
-         </module>
-         <module id="dac_nbit_ctrl_v5" name="DAC">
-            <instance name="DAC0">
-               <register-group address-space="data"
-                               name="DAC0"
-                               name-in-module="DAC"
-                               offset="0x06A0"/>
-               <signals>
-                  <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="EVSYS">
-            <instance name="EVSYS">
-               <register-group address-space="data"
-                               name="EVSYS"
-                               name-in-module="EVSYS"
-                               offset="0x0200"/>
-               <signals>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="0"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="3"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                          function="EVSYS_ALT1"
-                          group="EVOUT"
-                          index="5"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="FUSE">
-            <instance name="FUSE">
-               <register-group address-space="data"
-                               name="FUSE"
-                               name-in-module="FUSE"
-                               offset="0x1050"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="GPR">
-            <instance name="GPR">
-               <register-group address-space="data"
-                               name="GPR"
-                               name-in-module="GPR"
-                               offset="0x001C"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="LOCK">
-            <instance name="LOCK">
-               <register-group address-space="data"
-                               name="LOCK"
-                               name-in-module="LOCK"
-                               offset="0x1040"/>
-            </instance>
-         </module>
-         <module id="io_multiv_ctrl_avr_v1" name="MVIO">
-            <instance name="MVIO">
-               <register-group address-space="data"
-                               name="MVIO"
-                               name-in-module="MVIO"
-                               offset="0x00C0"/>
-            </instance>
-         </module>
-         <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
-            <instance name="NVMCTRL">
-               <register-group address-space="data"
-                               name="NVMCTRL"
-                               name-in-module="NVMCTRL"
-                               offset="0x1000"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_port" name="PORT">
-            <instance name="PORTA">
-               <register-group address-space="data"
-                               name="PORTA"
-                               name-in-module="PORT"
-                               offset="0x0400"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-               </signals>
-            </instance>
-            <instance name="PORTC">
-               <register-group address-space="data"
-                               name="PORTC"
-                               name-in-module="PORT"
-                               offset="0x0440"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="PORTD">
-               <register-group address-space="data"
-                               name="PORTD"
-                               name-in-module="PORT"
-                               offset="0x0460"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-               </signals>
-            </instance>
-            <instance name="PORTF">
-               <register-group address-space="data"
-                               name="PORTF"
-                               name-in-module="PORT"
-                               offset="0x04A0"/>
-               <signals>
-                  <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                  <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                  <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
-                  <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
-                  <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
-                  <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
-                  <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                  <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="PORTMUX">
-            <instance name="PORTMUX">
-               <register-group address-space="data"
-                               name="PORTMUX"
-                               name-in-module="PORTMUX"
-                               offset="0x05E0"/>
-            </instance>
-         </module>
-         <module id="rst_integration_v8" name="RSTCTRL">
-            <instance name="RSTCTRL">
-               <register-group address-space="data"
-                               name="RSTCTRL"
-                               name-in-module="RSTCTRL"
-                               offset="0x0040"/>
-               <signals>
-                  <signal function="OTHER" group="RESET" pad="PF6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_rtc_v1" name="RTC">
-            <instance name="RTC">
-               <register-group address-space="data"
-                               name="RTC"
-                               name-in-module="RTC"
-                               offset="0x0140"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="SIGROW">
-            <instance name="SIGROW">
-               <register-group address-space="data"
-                               name="SIGROW"
-                               name-in-module="SIGROW"
-                               offset="0x1100"/>
-            </instance>
-         </module>
-         <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
-            <instance name="SLPCTRL">
-               <register-group address-space="data"
-                               name="SLPCTRL"
-                               name-in-module="SLPCTRL"
-                               offset="0x0050"/>
-            </instance>
-         </module>
-         <module id="spi_8bit_v2" name="SPI">
-            <instance name="SPI0">
-               <register-group address-space="data"
-                               name="SPI0"
-                               name-in-module="SPI"
-                               offset="0x0940"/>
-               <signals>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MISO"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="MOSI"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0"
-                          group="SS"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MISO"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="MOSI"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SCK"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT3"
-                          group="SS"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MISO"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="MOSI"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT4"
-                          group="SS"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MISO"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="MOSI"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT5"
-                          group="SS"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MISO"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="MOSI"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SCK"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.SPIROUTEA.SPI0"
-                          function="SPI0_ALT6"
-                          group="SS"
-                          pad="PF7"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="SYSCFG">
-            <instance name="SYSCFG">
-               <register-group address-space="data"
-                               name="SYSCFG"
-                               name-in-module="SYSCFG"
-                               offset="0x0F00"/>
-            </instance>
-         </module>
-         <module id="tmr_16b_pwm_v1" name="TCA">
-            <instance name="TCA0">
-               <register-group address-space="data"
-                               name="TCA0"
-                               name-in-module="TCA"
-                               offset="0x0A00"/>
-               <signals>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="0"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="1"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="2"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="3"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="4"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0"
-                          group="WO"
-                          index="5"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="1"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="2"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT2"
-                          group="WO"
-                          index="3"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="1"
-                          pad="PD1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="2"
-                          pad="PD2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="3"
-                          pad="PD3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="4"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT3"
-                          group="WO"
-                          index="5"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="0"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="3"
-                          pad="PF3"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="4"
-                          pad="PF4"/>
-                  <signal field="PORTMUX.TCAROUTEA.TCA0"
-                          function="TCA0_ALT5"
-                          group="WO"
-                          index="5"
-                          pad="PF5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_16b_capture_v1" name="TCB">
-            <instance name="TCB0">
-               <register-group address-space="data"
-                               name="TCB0"
-                               name-in-module="TCB"
-                               offset="0x0B00"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0"
-                          group="WO"
-                          index="0"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TCBROUTEA.TCB0"
-                          function="TCB0_ALT1"
-                          group="WO"
-                          index="0"
-                          pad="PF4"/>
-               </signals>
-            </instance>
-            <instance name="TCB1">
-               <register-group address-space="data"
-                               name="TCB1"
-                               name-in-module="TCB"
-                               offset="0x0B10"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1"
-                          group="WO"
-                          index="0"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TCBROUTEA.TCB1"
-                          function="TCB1_ALT1"
-                          group="WO"
-                          index="0"
-                          pad="PF5"/>
-               </signals>
-            </instance>
-            <instance name="TCB2">
-               <register-group address-space="data"
-                               name="TCB2"
-                               name-in-module="TCB"
-                               offset="0x0B20"/>
-               <signals>
-                  <signal field="PORTMUX.TCBROUTEA.TCB2"
-                          function="TCB2"
-                          group="WO"
-                          index="0"
-                          pad="PC0"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="tmr_12b_psc_v1" name="TCD">
-            <instance name="TCD0">
-               <register-group address-space="data"
-                               name="TCD0"
-                               name-in-module="TCD"
-                               offset="0x0B80"/>
-               <signals>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOC"
-                          index="2"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0"
-                          group="WOD"
-                          index="3"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOA"
-                          pad="PF0"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOB"
-                          index="1"
-                          pad="PF1"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOC"
-                          index="2"
-                          pad="PF2"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT2"
-                          group="WOD"
-                          index="3"
-                          pad="PF3"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOA"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOB"
-                          index="1"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOC"
-                          index="2"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.TCDROUTEA.TCD0"
-                          function="TCD0_ALT4"
-                          group="WOD"
-                          index="3"
-                          pad="PD5"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="i2c_8bit_avr_v3" name="TWI">
-            <instance name="TWI0">
-               <register-group address-space="data"
-                               name="TWI0"
-                               name-in-module="TWI"
-                               offset="0x0900"/>
-               <signals>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SCL"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT1"
-                          group="SDA"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SCL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT2"
-                          group="SDA"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SCL_DUAL"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.TWIROUTEA.TWI0"
-                          function="I2C0_ALT3"
-                          group="SDA_DUAL"
-                          pad="PC2"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="uart_autobd_v4" name="USART">
-            <instance name="USART0">
-               <register-group address-space="data"
-                               name="USART0"
-                               name-in-module="USART"
-                               offset="0x0800"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="RXD"
-                          pad="PA1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="TXD"
-                          pad="PA0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XCK"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0"
-                          group="XDIR"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="RXD"
-                          pad="PA5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="TXD"
-                          pad="PA4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XCK"
-                          pad="PA6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT1"
-                          group="XDIR"
-                          pad="PA7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="RXD"
-                          pad="PA3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT2"
-                          group="TXD"
-                          pad="PA2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="RXD"
-                          pad="PD5"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="TXD"
-                          pad="PD4"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XCK"
-                          pad="PD6"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT3"
-                          group="XDIR"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="RXD"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="TXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART0"
-                          function="USART0_ALT4"
-                          group="XCK"
-                          pad="PC3"/>
-               </signals>
-            </instance>
-            <instance name="USART1">
-               <register-group address-space="data"
-                               name="USART1"
-                               name-in-module="USART"
-                               offset="0x0820"/>
-               <signals>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="RXD"
-                          pad="PC1"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="TXD"
-                          pad="PC0"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XCK"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1"
-                          group="XDIR"
-                          pad="PC3"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="RXD"
-                          pad="PD7"/>
-                  <signal field="PORTMUX.USARTROUTEA.USART1"
-                          function="USART1_ALT2"
-                          group="TXD"
-                          pad="PD6"/>
-               </signals>
-            </instance>
-         </module>
-         <module id="avrdd" name="USERROW">
-            <instance name="USERROW">
-               <register-group address-space="data"
-                               name="USERROW"
-                               name-in-module="USERROW"
-                               offset="0x1080"/>
-            </instance>
-         </module>
-         <module id="gpio_ports_avr_v2_vport" name="VPORT">
-            <instance name="VPORTA">
-               <register-group address-space="data"
-                               name="VPORTA"
-                               name-in-module="VPORT"
-                               offset="0x0000"/>
-            </instance>
-            <instance name="VPORTC">
-               <register-group address-space="data"
-                               name="VPORTC"
-                               name-in-module="VPORT"
-                               offset="0x0008"/>
-            </instance>
-            <instance name="VPORTD">
-               <register-group address-space="data"
-                               name="VPORTD"
-                               name-in-module="VPORT"
-                               offset="0x000C"/>
-            </instance>
-            <instance name="VPORTF">
-               <register-group address-space="data"
-                               name="VPORTF"
-                               name-in-module="VPORT"
-                               offset="0x0014"/>
-            </instance>
-         </module>
-         <module id="avrdd" name="VREF">
-            <instance name="VREF">
-               <register-group address-space="data"
-                               name="VREF"
-                               name-in-module="VREF"
-                               offset="0x00B0"/>
-            </instance>
-         </module>
-         <module id="wdt_windowed_v2" name="WDT">
-            <instance name="WDT">
-               <register-group address-space="data"
-                               name="WDT"
-                               name-in-module="WDT"
-                               offset="0x0100"/>
-            </instance>
-         </module>
-         <module id="cmp_zxover_ctrl_v3" name="ZCD">
-            <instance name="ZCD3">
-               <register-group address-space="data"
-                               name="ZCD3"
-                               name-in-module="ZCD"
-                               offset="0x06D8"/>
-               <signals>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="IN"
-                          pad="PC2"/>
-                  <signal field="PORTMUX.ZCDROUTEA.ZCD3"
-                          function="ZCD3"
-                          group="OUT"
-                          pad="PA7"/>
-               </signals>
-            </instance>
-         </module>
-      </peripherals>
-      <interrupts>
-         <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
-         <interrupt index="2" module-instance="BOD" name="VLM"/>
-         <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
-         <interrupt index="4" module-instance="MVIO" name="MVIO"/>
-         <interrupt index="5" module-instance="RTC" name="CNT"/>
-         <interrupt index="6" module-instance="RTC" name="PIT"/>
-         <interrupt index="7" module-instance="CCL" name="CCL"/>
-         <interrupt index="8" module-instance="PORTA" name="PORT"/>
-         <interrupt index="9" module-instance="TCA0" name="LUNF"/>
-         <interrupt index="9" module-instance="TCA0" name="OVF"/>
-         <interrupt index="10" module-instance="TCA0" name="HUNF"/>
-         <interrupt index="11" module-instance="TCA0" name="CMP0"/>
-         <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
-         <interrupt index="12" module-instance="TCA0" name="CMP1"/>
-         <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
-         <interrupt index="13" module-instance="TCA0" name="CMP2"/>
-         <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
-         <interrupt index="14" module-instance="TCB0" name="INT"/>
-         <interrupt index="15" module-instance="TCB1" name="INT"/>
-         <interrupt index="16" module-instance="TCD0" name="OVF"/>
-         <interrupt index="17" module-instance="TCD0" name="TRIG"/>
-         <interrupt index="18" module-instance="TWI0" name="TWIS"/>
-         <interrupt index="19" module-instance="TWI0" name="TWIM"/>
-         <interrupt index="20" module-instance="SPI0" name="INT"/>
-         <interrupt index="21" module-instance="USART0" name="RXC"/>
-         <interrupt index="22" module-instance="USART0" name="DRE"/>
-         <interrupt index="23" module-instance="USART0" name="TXC"/>
-         <interrupt index="24" module-instance="PORTD" name="PORT"/>
-         <interrupt index="25" module-instance="AC0" name="AC"/>
-         <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
-         <interrupt index="27" module-instance="ADC0" name="WCMP"/>
-         <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
-         <interrupt index="29" module-instance="PORTC" name="PORT"/>
-         <interrupt index="30" module-instance="TCB2" name="INT"/>
-         <interrupt index="31" module-instance="USART1" name="RXC"/>
-         <interrupt index="32" module-instance="USART1" name="DRE"/>
-         <interrupt index="33" module-instance="USART1" name="TXC"/>
-         <interrupt index="34" module-instance="PORTF" name="PORT"/>
-         <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
-      </interrupts>
-      <interfaces>
-         <interface name="UPDI" type="updi"/>
-      </interfaces>
-      <property-groups>
-         <property-group name="OCD_FEATURES">
-            <property name="BREAK_PIN" value="PF6"/>
-            <property name="BREAK_PIN_ALT" value="PF2"/>
-         </property-group>
-         <property-group name="PROGRAMMING_INFO">
-            <property name="FUSE_ENABLED_VALUE" value="1"/>
-         </property-group>
-         <property-group name="UPDI_INTERFACE">
-            <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-            <property name="HV_IMPLEMENTATION" value="2"/>
-            <property name="PROGMEM_OFFSET" value="0x00800000"/>
-         </property-group>
-         <property-group name="SIGNATURES">
-            <property name="SIGNATURE0" value="0x1E"/>
-            <property name="SIGNATURE1" value="0x95"/>
-            <property name="SIGNATURE2" value="0x38"/>
-         </property-group>
-      </property-groups>
-   </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
-               <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Shortest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-            <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
-            <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_v1"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
-               <bitfield caption="Resolution selection"
-                         mask="0x0C"
-                         name="RESSEL"
-                         rw="RW"
-                         values="ADC_RESSEL"/>
-               <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Conversion mode"
-                         mask="0x20"
-                         name="CONVMODE"
-                         rw="RW"
-                         values="ADC_CONVMODE"/>
-               <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Accumulation Samples"
-                         mask="0x07"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Pre-scaler"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sampling Delay Selection"
-                         mask="0x0F"
-                         name="SAMPDLY"
-                         rw="RW"
-                         values="ADC_SAMPDLY"/>
-               <bitfield caption="Initial Delay Selection"
-                         mask="0xE0"
-                         name="INITDLY"
-                         rw="RW"
-                         values="ADC_INITDLY"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-            </register>
-            <register caption="Sample Control"
-                      initval="0x00"
-                      name="SAMPCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
-            </register>
-            <register caption="Positive mux input"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-            </register>
-            <register caption="Negative mux input"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x7F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-            </register>
-            <register caption="Command"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
-               <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start Event Input Enable"
-                         mask="0x01"
-                         name="STARTEI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
-               <bitfield caption="Window Comparator Flag"
-                         mask="0x02"
-                         name="WCMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Data"
-                      initval="0x00"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
-            </register>
-            <register caption="ADC Accumulator Result"
-                      name="RES"
-                      offset="0x10"
-                      rw="R"
-                      size="2"/>
-            <register caption="Window comparator low threshold"
-                      name="WINLT"
-                      offset="0x12"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window comparator high threshold"
-                      name="WINHT"
-                      offset="0x14"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Conversion mode select" name="ADC_CONVMODE">
-            <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
-            <value caption="Differential mode" name="DIFF" value="0x1"/>
-         </value-group>
-         <value-group caption="Resolution selection" name="ADC_RESSEL">
-            <value caption="12-bit mode" name="12BIT" value="0x0"/>
-            <value caption="10-bit mode" name="10BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x00"/>
-            <value caption="2 results accumulated" name="ACC2" value="0x01"/>
-            <value caption="4 results accumulated" name="ACC4" value="0x02"/>
-            <value caption="8 results accumulated" name="ACC8" value="0x03"/>
-            <value caption="16 results accumulated" name="ACC16" value="0x04"/>
-            <value caption="32 results accumulated" name="ACC32" value="0x05"/>
-            <value caption="64 results accumulated" name="ACC64" value="0x06"/>
-            <value caption="128 results accumulated" name="ACC128" value="0x7"/>
-         </value-group>
-         <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
-            <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
-            <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
-            <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
-            <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
-            <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
-            <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
-            <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
-            <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
-            <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
-            <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
-            <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
-            <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
-            <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
-         </value-group>
-         <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
-            <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
-            <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
-            <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
-            <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
-            <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
-         </value-group>
-         <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
-            <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
-            <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
-            <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
-            <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
-            <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
-            <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
-            <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
-            <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
-            <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
-            <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
-            <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
-            <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
-            <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
-            <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
-            <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
-            <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x40"/>
-            <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
-            <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
-            <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
-            <value caption="DAC0" name="DAC0" value="0x48"/>
-            <value caption="DACREF0" name="DACREF0" value="0x49"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled with wake-up halted until BOD is ready"
-                   name="ENWAKE"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
-            <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DIS" value="0x00"/>
-            <value caption="Enabled" name="ENABLED" value="0x01"/>
-            <value caption="Sampled" name="SAMPLED" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
-            <value caption="Internal High-Frequency Oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
-            <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
-            <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x00"/>
-            <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
-            <value caption="Linked LUT input source" name="LINK" value="0x02"/>
-            <value caption="Event input source A" name="EVENTA" value="0x03"/>
-            <value caption="Event input source B" name="EVENTB" value="0x04"/>
-            <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
-            <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
-            <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
-            <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
-            <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
-            <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrdd" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x00"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="Clock Failure Detect Test"
-                         mask="0x02"
-                         name="CFDTST"
-                         rw="W"/>
-               <bitfield caption="Clock Failure Detect Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Enable"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-               <bitfield caption="Interrupt type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Interrupt Flag"
-                         mask="0x01"
-                         name="CFD"
-                         rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="RW"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="RW"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="RW"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="RW"/>
-               <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
-               <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
-               <bitfield caption="Frequency select"
-                         mask="0x3C"
-                         name="FRQSEL"
-                         rw="RW"
-                         values="CLKCTRL_FRQSEL"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="PLL Control A"
-                      name="PLLCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multiplication factor"
-                         mask="0x03"
-                         name="MULFAC"
-                         rw="RW"
-                         values="CLKCTRL_MULFAC"/>
-               <bitfield caption="Source"
-                         mask="0x40"
-                         name="SOURCE"
-                         rw="RW"
-                         values="CLKCTRL_SOURCE"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC HF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="External Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Frequency Range"
-                         mask="0x0C"
-                         name="FRQRANGE"
-                         rw="RW"
-                         values="CLKCTRL_FRQRANGE"/>
-               <bitfield caption="Start-up Time Select"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="2X" name="2X" value="0x00"/>
-            <value caption="4X" name="4X" value="0x01"/>
-            <value caption="8X" name="8X" value="0x02"/>
-            <value caption="16X" name="16X" value="0x03"/>
-            <value caption="32X" name="32X" value="0x04"/>
-            <value caption="64X" name="64X" value="0x05"/>
-            <value caption="6X" name="6X" value="0x08"/>
-            <value caption="10X" name="10X" value="0x09"/>
-            <value caption="12X" name="12X" value="0x0A"/>
-            <value caption="24X" name="24X" value="0x0B"/>
-            <value caption="48X" name="48X" value="0x0C"/>
-         </value-group>
-         <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
-            <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular Interrupt" name="INT" value="0x0"/>
-            <value caption="NMI" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
-            <value caption="1 MHz system clock" name="1M" value="0x0"/>
-            <value caption="2 MHz system clock" name="2M" value="0x1"/>
-            <value caption="3 MHz system clock" name="3M" value="0x2"/>
-            <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
-            <value caption="8 MHz system clock" name="8M" value="0x5"/>
-            <value caption="12 MHz system clock" name="12M" value="0x6"/>
-            <value caption="16 MHz system clock" name="16M" value="0x7"/>
-            <value caption="20 MHz system clock" name="20M" value="0x8"/>
-            <value caption="24 MHz system clock" name="24M" value="0x9"/>
-         </value-group>
-         <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
-            <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
-            <value caption="2 x multiplication factor" name="2x" value="0x1"/>
-            <value caption="3 x multiplication factor" name="3x" value="0x2"/>
-         </value-group>
-         <value-group caption="Source select" name="CLKCTRL_SOURCE">
-            <value caption="High frequency internal oscillator as PLL source"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="High frequency external clock or external high frequency oscillator as PLL source"
-                   name="XOSCHF"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
-            <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
-            <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
-         </value-group>
-         <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
-            <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
-            <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
-            <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
-            <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
-         </value-group>
-         <value-group caption="External Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="XTAL" value="0x0"/>
-            <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_v5"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Event System" id="avrdd" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Software Event B"
-                      initval="0x00"
-                      name="SWEVENTB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0x03"
-                         name="SWEVENTB"
-                         rw="W"
-                         values="EVSYS_SWEVENTB"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 0 generator select"
-                         mask="0xFF"
-                         name="CHANNEL0"
-                         rw="RW"
-                         values="EVSYS_CHANNEL0"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 1 generator select"
-                         mask="0xFF"
-                         name="CHANNEL1"
-                         rw="RW"
-                         values="EVSYS_CHANNEL1"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 2 generator select"
-                         mask="0xFF"
-                         name="CHANNEL2"
-                         rw="RW"
-                         values="EVSYS_CHANNEL2"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 3 generator select"
-                         mask="0xFF"
-                         name="CHANNEL3"
-                         rw="RW"
-                         values="EVSYS_CHANNEL3"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 4 generator select"
-                         mask="0xFF"
-                         name="CHANNEL4"
-                         rw="RW"
-                         values="EVSYS_CHANNEL4"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel 5 generator select"
-                         mask="0xFF"
-                         name="CHANNEL5"
-                         rw="RW"
-                         values="EVSYS_CHANNEL5"/>
-            </register>
-            <register caption="User 0 - CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 1 - CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 2 - CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 3 - CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 4 - CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 5 - CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 6 - CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 7 - CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 12 - ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 13 - EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 15 - EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 16 - EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 18 - EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 20 - USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 21 - USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 26 - TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 27 - TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 30 - TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 31 - TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 32 - TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 33 - TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 34 - TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 35 - TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 40 - TCD0 Event A"
-                      initval="0x00"
-                      name="USERTCD0INPUTA"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="User 41 - TCD0 Event B"
-                      initval="0x00"
-                      name="USERTCD0INPUTB"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
-            <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
-            <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
-            <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
-            <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
-            <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
-            <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
-            <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
-            <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
-            <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
-            <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
-            <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
-            <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
-            <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
-            <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
-            <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
-            <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
-            <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV8192"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV4096"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV2048"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV1024"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
-            <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
-            <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
-            <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer output 0"
-                   name="RTC_PIT_DIV512"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer output 1"
-                   name="RTC_PIT_DIV256"
-                   value="0x9"/>
-            <value caption="Periodic Interrupt Timer output 2"
-                   name="RTC_PIT_DIV128"
-                   value="0xA"/>
-            <value caption="Periodic Interrupt Timer output 3"
-                   name="RTC_PIT_DIV64"
-                   value="0xB"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
-            <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
-            <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
-            <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
-            <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
-            <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
-            <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
-            <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
-            <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
-            <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
-            <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
-            <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
-            <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
-            <value caption="Software event on channel 8" name="CH8" value="0x0"/>
-            <value caption="Software event on channel 9" name="CH9" value="0x1"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrdd" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Frequency Select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="FUSE_CLKSEL"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x08"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-               <bitfield caption="MVIO System Configuration"
-                         mask="0x18"
-                         name="MVSYSCFG"
-                         rw="RW"
-                         values="FUSE_MVSYSCFG"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-            <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
-            <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
-            <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="BOD disabled" name="DISABLE" value="0x00"/>
-            <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Frequency Select" name="FUSE_CLKSEL">
-            <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
-            <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="GPIO mode" name="GPIO" value="0x0"/>
-            <value caption="Reset mode" name="RST" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="GPIO Mode" name="GPIO" value="0x0"/>
-            <value caption="UPDI Mode" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
-            <value caption="Device used in a dual supply configuration"
-                   name="DUAL"
-                   value="0x1"/>
-            <value caption="Device used in a single supply configuration"
-                   name="SINGLE"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrdd" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x3"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrdd" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
-         <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Enable"
-                         mask="0x01"
-                         name="VDDIO2IE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="VDDIO2 Interrupt Flag"
-                         mask="0x01"
-                         name="VDDIO2IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v1"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x02"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
-               <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
-            <register caption="Address"
-                      name="ADDR"
-                      offset="0x08"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Write" name="FLWR" value="0x02"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash Multi-Page Erase 2 pages"
-                   name="FLMPER2"
-                   value="0x09"/>
-            <value caption="Flash Multi-Page Erase 4 pages"
-                   name="FLMPER4"
-                   value="0x0A"/>
-            <value caption="Flash Multi-Page Erase 8 pages"
-                   name="FLMPER8"
-                   value="0x0B"/>
-            <value caption="Flash Multi-Page Erase 16 pages"
-                   name="FLMPER16"
-                   value="0x0C"/>
-            <value caption="Flash Multi-Page Erase 32 pages"
-                   name="FLMPER32"
-                   value="0x0D"/>
-            <value caption="EEPROM Write" name="EEWR" value="0x12"/>
-            <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
-            <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
-            <value caption="EEPROM Multi-Byte Erase 2 bytes"
-                   name="EEMBER2"
-                   value="0x19"/>
-            <value caption="EEPROM Multi-Byte Erase 4 bytes"
-                   name="EEMBER4"
-                   value="0x1A"/>
-            <value caption="EEPROM Multi-Byte Erase 8 bytes"
-                   name="EEMBER8"
-                   value="0x1B"/>
-            <value caption="EEPROM Multi-Byte Erase 16 bytes"
-                   name="EEMBER16"
-                   value="0x1C"/>
-            <value caption="EEPROM Multi-Byte Erase 32 bytes"
-                   name="EEMBER32"
-                   value="0x1D"/>
-            <value caption="Chip Erase Command" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
-            <value caption="Write to section not allowed"
-                   name="ILLEGALSADDR"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="DOUBLESELECT"
-                   value="0x3"/>
-            <value caption="Starting a new programming operation before previous is completed"
-                   name="ONGOINGPROG"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control update mask"
-                         mask="0xFF"
-                         name="PINCTRLUPD"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control set mask"
-                         mask="0xFF"
-                         name="PINCTRLSET"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin control clear mask"
-                         mask="0xFF"
-                         name="PINCTRLCLR"
-                         rw="RW"/>
-            </register>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-               <bitfield caption="CCL Look-Up Table 3 Signals"
-                         mask="0x08"
-                         name="LUT3"
-                         rw="RW"
-                         values="PORTMUX_LUT3"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Signals"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Signals"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-            </register>
-            <register caption="TCD route A"
-                      initval="0x00"
-                      name="TCDROUTEA"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCD0 Signals"
-                         mask="0x07"
-                         name="TCD0"
-                         rw="RW"
-                         values="PORTMUX_TCD0"/>
-            </register>
-         </register-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
-            <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
-            <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
-            <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
-            <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-            <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
-            <value caption="WO on PB4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
-            <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
-            <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
-            <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
-            <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
-            <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
-            <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
-            <value caption="PA2, PA3" name="ALT2" value="0x2"/>
-            <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
-            <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
-            <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
-            <value caption="PD6, PD7" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software reset enable"
-                         mask="0x01"
-                         name="SWRST"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
-            <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
-            <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrdd" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 0"
-                         mask="0xFFFF"
-                         name="TEMPSENSE0"
-                         rw="R"/>
-            </register>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2">
-               <bitfield caption="Temperature Calibration 1"
-                         mask="0xFFFF"
-                         name="TEMPSENSE1"
-                         rw="R"/>
-            </register>
-            <register caption="LOTNUM0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="LOTNUM5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="RANDOM"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="SCRIBE"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS0"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="XPOS1"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS0"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="YPOS1"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES0"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES1"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES2"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="RES3"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v2"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="VREGCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Performance Mode"
-                         mask="0x07"
-                         name="PMODE"
-                         rw="RW"
-                         values="SLPCTRL_PMODE"/>
-               <bitfield caption="High Temperature Low Leakage Enable"
-                         mask="0x10"
-                         name="HTLLEN"
-                         rw="RW"
-                         values="SLPCTRL_HTLLEN"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-         <value-group caption="High Temperature Low Leakage Enable select"
-                      name="SLPCTRL_HTLLEN">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Enabled" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
-            <value caption="" name="AUTO" value="0x0"/>
-            <value caption="" name="FULL" value="0x1"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
-         <register-group caption="Timer Counter D" name="TCD" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Synchronization prescaler"
-                         mask="0x06"
-                         name="SYNCPRES"
-                         rw="RW"
-                         values="TCD_SYNCPRES"/>
-               <bitfield caption="Counter prescaler"
-                         mask="0x18"
-                         name="CNTPRES"
-                         rw="RW"
-                         values="TCD_CNTPRES"/>
-               <bitfield caption="Clock select"
-                         mask="0x60"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCD_CLKSEL"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x03"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCD_WGMODE"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare output value override"
-                         mask="0x01"
-                         name="CMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
-               <bitfield caption="Fifty percent waveform"
-                         mask="0x08"
-                         name="FIFTY"
-                         rw="RW"/>
-               <bitfield caption="Compare C output select"
-                         mask="0x40"
-                         name="CMPCSEL"
-                         rw="RW"
-                         values="TCD_CMPCSEL"/>
-               <bitfield caption="Compare D output select"
-                         mask="0x80"
-                         name="CMPDSEL"
-                         rw="RW"
-                         values="TCD_CMPDSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Synchronize end of cycle strobe"
-                         mask="0x01"
-                         name="SYNCEOC"
-                         rw="RW"/>
-               <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
-               <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
-               <bitfield caption="Software Capture A Strobe"
-                         mask="0x08"
-                         name="SCAPTUREA"
-                         rw="RW"/>
-               <bitfield caption="Software Capture B Strobe"
-                         mask="0x10"
-                         name="SCAPTUREB"
-                         rw="RW"/>
-               <bitfield caption="Disable at end of cycle"
-                         mask="0x80"
-                         name="DISEOC"
-                         rw="RW"/>
-            </register>
-            <register caption="EVCTRLA"
-                      initval="0x00"
-                      name="EVCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="EVCTRLB"
-                      initval="0x00"
-                      name="EVCTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Trigger event enable"
-                         mask="0x01"
-                         name="TRIGEI"
-                         rw="RW"/>
-               <bitfield caption="Event action"
-                         mask="0x04"
-                         name="ACTION"
-                         rw="RW"
-                         values="TCD_ACTION"/>
-               <bitfield caption="Edge select"
-                         mask="0x10"
-                         name="EDGE"
-                         rw="RW"
-                         values="TCD_EDGE"/>
-               <bitfield caption="Event config"
-                         mask="0xC0"
-                         name="CFG"
-                         rw="RW"
-                         values="TCD_CFG"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Trigger A interrupt enable"
-                         mask="0x04"
-                         name="TRIGA"
-                         rw="RW"/>
-               <bitfield caption="Trigger B interrupt enable"
-                         mask="0x08"
-                         name="TRIGB"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
-               <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
-               <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
-               <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
-            </register>
-            <register caption="Input Control A"
-                      initval="0x00"
-                      name="INPUTCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Input Control B"
-                      initval="0x00"
-                      name="INPUTCTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input mode"
-                         mask="0x0F"
-                         name="INPUTMODE"
-                         rw="RW"
-                         values="TCD_INPUTMODE"/>
-            </register>
-            <register caption="Fault Control"
-                      initval="0x00"
-                      name="FAULTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
-               <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
-               <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
-               <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
-               <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
-               <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
-               <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
-               <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
-            </register>
-            <register caption="Delay Control"
-                      initval="0x00"
-                      name="DLYCTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay select"
-                         mask="0x03"
-                         name="DLYSEL"
-                         rw="RW"
-                         values="TCD_DLYSEL"/>
-               <bitfield caption="Delay trigger"
-                         mask="0x0C"
-                         name="DLYTRIG"
-                         rw="RW"
-                         values="TCD_DLYTRIG"/>
-               <bitfield caption="Delay prescaler"
-                         mask="0x30"
-                         name="DLYPRESC"
-                         rw="RW"
-                         values="TCD_DLYPRESC"/>
-            </register>
-            <register caption="Delay value"
-                      initval="0x00"
-                      name="DLYVAL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
-            </register>
-            <register caption="Dither Control A"
-                      initval="0x00"
-                      name="DITCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither select"
-                         mask="0x03"
-                         name="DITHERSEL"
-                         rw="RW"
-                         values="TCD_DITHERSEL"/>
-            </register>
-            <register caption="Dither value"
-                      initval="0x00"
-                      name="DITVAL"
-                      offset="0x19"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
-               <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
-            </register>
-            <register caption="Capture A"
-                      name="CAPTUREA"
-                      offset="0x22"
-                      rw="R"
-                      size="2"/>
-            <register caption="Capture B"
-                      name="CAPTUREB"
-                      offset="0x24"
-                      rw="R"
-                      size="2"/>
-            <register caption="Compare A Set"
-                      name="CMPASET"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare A Clear"
-                      name="CMPACLR"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Set"
-                      name="CMPBSET"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare B Clear"
-                      name="CMPBCLR"
-                      offset="0x2E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock select" name="TCD_CLKSEL">
-            <value caption="Internal High-Frequency oscillator"
-                   name="OSCHF"
-                   value="0x00"/>
-            <value caption="PLL" name="PLL" value="0x01"/>
-            <value caption="External Clock" name="EXTCLK" value="0x02"/>
-            <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
-         </value-group>
-         <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
-            <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
-            <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
-         </value-group>
-         <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
-            <value caption="Selected clock source divided by 1"
-                   name="DIV1"
-                   value="0x00"/>
-            <value caption="Selected clock source divided by 2"
-                   name="DIV2"
-                   value="0x01"/>
-            <value caption="Selected clock source divided by 4"
-                   name="DIV4"
-                   value="0x02"/>
-            <value caption="Selected clock source divided by 8"
-                   name="DIV8"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
-            <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
-            <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
-            <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
-            <value caption="Dual slope mode" name="DS" value="0x3"/>
-         </value-group>
-         <value-group caption="Compare C output select" name="TCD_CMPCSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Compare D output select" name="TCD_CMPDSEL">
-            <value caption="PWM A output" name="PWMA" value="0x0"/>
-            <value caption="PWM B output" name="PWMB" value="0x1"/>
-         </value-group>
-         <value-group caption="Dither select" name="TCD_DITHERSEL">
-            <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
-            <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
-            <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
-            <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
-            <value caption="No prescaling" name="DIV1" value="0x0"/>
-            <value caption="Prescale with 2" name="DIV2" value="0x1"/>
-            <value caption="Prescale with 4" name="DIV4" value="0x2"/>
-            <value caption="Prescale with 8" name="DIV8" value="0x3"/>
-         </value-group>
-         <value-group caption="Delay select" name="TCD_DLYSEL">
-            <value caption="No delay" name="OFF" value="0x0"/>
-            <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
-            <value caption="Event delay enabled" name="EVENT" value="0x2"/>
-         </value-group>
-         <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
-            <value caption="Compare A set" name="CMPASET" value="0x0"/>
-            <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
-            <value caption="Compare B set" name="CMPBSET" value="0x2"/>
-            <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
-         </value-group>
-         <value-group caption="Event action select" name="TCD_ACTION">
-            <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
-            <value caption="Event trigger a fault and capture"
-                   name="CAPTURE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Event config select" name="TCD_CFG">
-            <value caption="Neither Filter nor Asynchronous Event is enabled"
-                   name="NEITHER"
-                   value="0x0"/>
-            <value caption="Input Capture Noise Cancellation Filter enabled"
-                   name="FILTER"
-                   value="0x1"/>
-            <value caption="Asynchronous Event output qualification enabled"
-                   name="ASYNC"
-                   value="0x2"/>
-         </value-group>
-         <value-group caption="Edge select" name="TCD_EDGE">
-            <value caption="The falling edge or low level of event generates retrigger or fault action"
-                   name="FALL_LOW"
-                   value="0x0"/>
-            <value caption="The rising edge or high level of event generates retrigger or fault action"
-                   name="RISE_HIGH"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Input mode select" name="TCD_INPUTMODE">
-            <value caption="Input has no actions" name="NONE" value="0x00"/>
-            <value caption="Stop output, jump to opposite compare cycle and wait"
-                   name="JMPWAIT"
-                   value="0x01"/>
-            <value caption="Stop output, execute opposite compare cycle and wait"
-                   name="EXECWAIT"
-                   value="0x02"/>
-            <value caption="stop output, execute opposite compare cycle while fault active"
-                   name="EXECFAULT"
-                   value="0x03"/>
-            <value caption="Stop all outputs, maintain frequency"
-                   name="FREQ"
-                   value="0x04"/>
-            <value caption="Stop all outputs, execute dead time while fault active"
-                   name="EXECDT"
-                   value="0x05"/>
-            <value caption="Stop all outputs, jump to next compare cycle and wait"
-                   name="WAIT"
-                   value="0x06"/>
-            <value caption="Stop all outputs, wait for software action"
-                   name="WAITSW"
-                   value="0x07"/>
-            <value caption="Stop output on edge, jump to next compare cycle"
-                   name="EDGETRIG"
-                   value="0x08"/>
-            <value caption="Stop output on edge, maintain frequency"
-                   name="EDGETRIGFREQ"
-                   value="0x09"/>
-            <value caption="Stop output at level, maintain frequency"
-                   name="LVLTRIGFREQ"
-                   value="0x0A"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrdd" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x20">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrdd" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="ADC0 Reference"
-                      initval="0x00"
-                      name="ADC0REF"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
-            <value caption="VDD as reference" name="VDD" value="0x05"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
-         <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Invert signal from pin"
-                         mask="0x08"
-                         name="INVERT"
-                         rw="RW"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode"
-                         mask="0x03"
-                         name="INTMODE"
-                         rw="RW"
-                         values="ZCD_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
-               <bitfield caption="ZCD State"
-                         mask="0x10"
-                         name="STATE"
-                         rw="R"
-                         values="ZCD_STATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
-            <value caption="No interrupt" name="NONE" value="0x0"/>
-            <value caption="Interrupt on rising input signal"
-                   name="RISING"
-                   value="0x1"/>
-            <value caption="Interrupt on falling input signal"
-                   name="FALLING"
-                   value="0x2"/>
-            <value caption="Interrupt on both rising and falling input signal"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="ZCD State select" name="ZCD_STATE">
-            <value caption="Output is 0" name="LOW" value="0x0"/>
-            <value caption="Output is 1" name="HIGH" value="0x1"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN32MVIO">
-         <pin pad="PA3" position="1"/>
-         <pin pad="PA4" position="2"/>
-         <pin pad="PA5" position="3"/>
-         <pin pad="PA6" position="4"/>
-         <pin pad="PA7" position="5"/>
-         <pin pad="PC0" position="6"/>
-         <pin pad="PC1" position="7"/>
-         <pin pad="PC2" position="8"/>
-         <pin pad="PC3" position="9"/>
-         <pin pad="VDDIO2" position="10"/>
-         <pin pad="PD1" position="11"/>
-         <pin pad="PD2" position="12"/>
-         <pin pad="PD3" position="13"/>
-         <pin pad="PD4" position="14"/>
-         <pin pad="PD5" position="15"/>
-         <pin pad="PD6" position="16"/>
-         <pin pad="PD7" position="17"/>
-         <pin pad="AVDD" position="18"/>
-         <pin pad="AGND" position="19"/>
-         <pin pad="PF0" position="20"/>
-         <pin pad="PF1" position="21"/>
-         <pin pad="PF2" position="22"/>
-         <pin pad="PF3" position="23"/>
-         <pin pad="PF4" position="24"/>
-         <pin pad="PF5" position="25"/>
-         <pin pad="PF6" position="26"/>
-         <pin pad="PF7" position="27"/>
-         <pin pad="VDD0" position="28"/>
-         <pin pad="GND0" position="29"/>
-         <pin pad="PA0" position="30"/>
-         <pin pad="PA1" position="31"/>
-         <pin pad="PA2" position="32"/>
-      </pinout>
-   </pinouts>
+    <variants>
+        <variant ordercode="AVR32DD32"
+                 package="QFN32"
+                 pinout="QFN32MVIO"
+                 speedmax="32000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR32DD32" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
+        <address-spaces>
+            <address-space endianness="little"
+                           id="data"
+                           name="data"
+                           size="0x10000"
+                           start="0x0000">
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x20"
+                                rw="RW"
+                                size="0x20"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x1"
+                                rw="RW"
+                                size="0x100"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1000"
+                                start="0x7000"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
+            </address-space>
+            <address-space endianness="little"
+                           id="prog"
+                           name="prog"
+                           size="0x8000"
+                           start="0x0000">
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x200"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x00"
+                                type="flash"/>
+            </address-space>
+        </address-spaces>
+        <peripherals>
+            <module id="cmp_control_v8" name="AC">
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AC0" group="N" index="0" pad="PD3"/>
+                        <signal function="AC0" group="N" index="2" pad="PD7"/>
+                        <signal function="AC0" group="N" index="3" pad="PC2"/>
+                        <signal function="AC0" group="P" index="0" pad="PD2"/>
+                        <signal function="AC0" group="P" index="3" pad="PD6"/>
+                        <signal function="AC0" group="P" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="AC0"
+                                group="OUT"
+                                index="0"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="adc_12b_diff_ctrl_v1" name="ADC">
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AIN0" group="AIN" index="1" pad="PD1"/>
+                        <signal function="AIN0" group="AIN" index="2" pad="PD2"/>
+                        <signal function="AIN0" group="AIN" index="3" pad="PD3"/>
+                        <signal function="AIN0" group="AIN" index="4" pad="PD4"/>
+                        <signal function="AIN0" group="AIN" index="5" pad="PD5"/>
+                        <signal function="AIN0" group="AIN" index="6" pad="PD6"/>
+                        <signal function="AIN0" group="AIN" index="7" pad="PD7"/>
+                        <signal function="AIN0" group="AIN" index="16" pad="PF0"/>
+                        <signal function="AIN0" group="AIN" index="17" pad="PF1"/>
+                        <signal function="AIN0" group="AIN" index="18" pad="PF2"/>
+                        <signal function="AIN0" group="AIN" index="19" pad="PF3"/>
+                        <signal function="AIN0" group="AIN" index="20" pad="PF4"/>
+                        <signal function="AIN0" group="AIN" index="21" pad="PF5"/>
+                        <signal function="AIN0" group="AIN" index="22" pad="PA2"/>
+                        <signal function="AIN0" group="AIN" index="23" pad="PA3"/>
+                        <signal function="AIN0" group="AIN" index="24" pad="PA4"/>
+                        <signal function="AIN0" group="AIN" index="25" pad="PA5"/>
+                        <signal function="AIN0" group="AIN" index="26" pad="PA6"/>
+                        <signal function="AIN0" group="AIN" index="27" pad="PA7"/>
+                        <signal function="AIN0" group="AIN" index="28" pad="PC0"/>
+                        <signal function="AIN0" group="AIN" index="29" pad="PC1"/>
+                        <signal function="AIN0" group="AIN" index="30" pad="PC2"/>
+                        <signal function="AIN0" group="AIN" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="bor_lvd_ctrl_v1" name="BOD">
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
+            </module>
+            <module id="cla_ccl_v1" name="CCL">
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_IN"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="CCL_ALT1"
+                                group="LUT0_OUT"
+                                index="0"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL"
+                                group="LUT1_OUT"
+                                index="0"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="CCL_ALT1"
+                                group="LUT1_IN"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_IN"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="CCL_ALT1"
+                                group="LUT2_OUT"
+                                index="0"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_IN"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="CCL"
+                                group="LUT3_OUT"
+                                index="0"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="CLKCTRL">
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="CLKCTRL" group="CLKOUT" pad="PA7"/>
+                        <signal function="CLKCTRL" group="EXTCLK" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTAL32K1" pad="PF0"/>
+                        <signal function="CLKCTRL" group="XTAL32K2" pad="PF1"/>
+                        <signal function="CLKCTRL" group="XTALHF1" pad="PA0"/>
+                        <signal function="CLKCTRL" group="XTALHF2" pad="PA1"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K1" pad="PA0"/>
+                        <signal function="CLKCTRL_ALT1" group="XTAL32K2" pad="PA1"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="cpu_avr_xt_v1" name="CPU">
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
+            </module>
+            <module id="int_8bit_v3" name="CPUINT">
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
+            </module>
+            <module id="math_pdi_crc_v1" name="CRCSCAN">
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
+            </module>
+            <module id="dac_nbit_ctrl_v5" name="DAC">
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="DAC0" group="OUT" index="0" pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="EVSYS">
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="EVSYS_ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="FUSE">
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="GPR">
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="LOCK">
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
+            </module>
+            <module id="io_multiv_ctrl_avr_v1" name="MVIO">
+                <instance name="MVIO">
+                    <register-group address-space="data"
+                                    name="MVIO"
+                                    name-in-module="MVIO"
+                                    offset="0x00C0"/>
+                </instance>
+            </module>
+            <module id="nvm_ctrl_avr_v1" name="NVMCTRL">
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_port" name="PORT">
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="PORTMUX">
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
+            </module>
+            <module id="rst_integration_v8" name="RSTCTRL">
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_rtc_v1" name="RTC">
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="SIGROW">
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
+            </module>
+            <module id="clk_sleep_ctrl_avr_v2" name="SLPCTRL">
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
+            </module>
+            <module id="spi_8bit_v2" name="SPI">
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0"
+                                group="SS"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MISO"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="MOSI"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="SPI0_ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="SYSCFG">
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
+            </module>
+            <module id="tmr_16b_pwm_v1" name="TCA">
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="4"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="TCA0_ALT5"
+                                group="WO"
+                                index="5"
+                                pad="PF5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_16b_capture_v1" name="TCB">
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="TCB0_ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF4"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="TCB1_ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF5"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="TCB2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="tmr_12b_psc_v1" name="TCD">
+                <instance name="TCD0">
+                    <register-group address-space="data"
+                                    name="TCD0"
+                                    name-in-module="TCD"
+                                    offset="0x0B80"/>
+                    <signals>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOC"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0"
+                                group="WOD"
+                                index="3"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOA"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOB"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOC"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT2"
+                                group="WOD"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOA"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOB"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOC"
+                                index="2"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCDROUTEA.TCD0"
+                                function="TCD0_ALT4"
+                                group="WOD"
+                                index="3"
+                                pad="PD5"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="i2c_8bit_avr_v3" name="TWI">
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="I2C0_ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="uart_autobd_v4" name="USART">
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0"
+                                group="XDIR"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="RXD"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="TXD"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT1"
+                                group="XDIR"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="RXD"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT2"
+                                group="TXD"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="RXD"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="TXD"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT3"
+                                group="XDIR"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="RXD"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="TXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="USART0_ALT4"
+                                group="XCK"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1"
+                                group="XDIR"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="USART1_ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                    </signals>
+                </instance>
+            </module>
+            <module id="avrdd" name="USERROW">
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
+            </module>
+            <module id="gpio_ports_avr_v2_vport" name="VPORT">
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
+            </module>
+            <module id="avrdd" name="VREF">
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                </instance>
+            </module>
+            <module id="wdt_windowed_v2" name="WDT">
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
+            </module>
+            <module id="cmp_zxover_ctrl_v3" name="ZCD">
+                <instance name="ZCD3">
+                    <register-group address-space="data"
+                                    name="ZCD3"
+                                    name-in-module="ZCD"
+                                    offset="0x06D8"/>
+                    <signals>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="IN"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.ZCDROUTEA.ZCD3"
+                                function="ZCD3"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+            </module>
+        </peripherals>
+        <interrupts>
+            <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
+            <interrupt index="2" module-instance="BOD" name="VLM"/>
+            <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
+            <interrupt index="4" module-instance="MVIO" name="MVIO"/>
+            <interrupt index="5" module-instance="RTC" name="CNT"/>
+            <interrupt index="6" module-instance="RTC" name="PIT"/>
+            <interrupt index="7" module-instance="CCL" name="CCL"/>
+            <interrupt index="8" module-instance="PORTA" name="PORT"/>
+            <interrupt index="9" module-instance="TCA0" name="LUNF"/>
+            <interrupt index="9" module-instance="TCA0" name="OVF"/>
+            <interrupt index="10" module-instance="TCA0" name="HUNF"/>
+            <interrupt index="11" module-instance="TCA0" name="CMP0"/>
+            <interrupt index="11" module-instance="TCA0" name="LCMP0"/>
+            <interrupt index="12" module-instance="TCA0" name="CMP1"/>
+            <interrupt index="12" module-instance="TCA0" name="LCMP1"/>
+            <interrupt index="13" module-instance="TCA0" name="CMP2"/>
+            <interrupt index="13" module-instance="TCA0" name="LCMP2"/>
+            <interrupt index="14" module-instance="TCB0" name="INT"/>
+            <interrupt index="15" module-instance="TCB1" name="INT"/>
+            <interrupt index="16" module-instance="TCD0" name="OVF"/>
+            <interrupt index="17" module-instance="TCD0" name="TRIG"/>
+            <interrupt index="18" module-instance="TWI0" name="TWIS"/>
+            <interrupt index="19" module-instance="TWI0" name="TWIM"/>
+            <interrupt index="20" module-instance="SPI0" name="INT"/>
+            <interrupt index="21" module-instance="USART0" name="RXC"/>
+            <interrupt index="22" module-instance="USART0" name="DRE"/>
+            <interrupt index="23" module-instance="USART0" name="TXC"/>
+            <interrupt index="24" module-instance="PORTD" name="PORT"/>
+            <interrupt index="25" module-instance="AC0" name="AC"/>
+            <interrupt index="26" module-instance="ADC0" name="RESRDY"/>
+            <interrupt index="27" module-instance="ADC0" name="WCMP"/>
+            <interrupt index="28" module-instance="ZCD3" name="ZCD"/>
+            <interrupt index="29" module-instance="PORTC" name="PORT"/>
+            <interrupt index="30" module-instance="TCB2" name="INT"/>
+            <interrupt index="31" module-instance="USART1" name="RXC"/>
+            <interrupt index="32" module-instance="USART1" name="DRE"/>
+            <interrupt index="33" module-instance="USART1" name="TXC"/>
+            <interrupt index="34" module-instance="PORTF" name="PORT"/>
+            <interrupt index="35" module-instance="NVMCTRL" name="EE"/>
+        </interrupts>
+        <interfaces>
+            <interface name="UPDI" type="updi"/>
+        </interfaces>
+        <property-groups>
+            <property-group name="OCD_FEATURES">
+                <property name="BREAK_PIN" value="PF6"/>
+                <property name="BREAK_PIN_ALT" value="PF2"/>
+            </property-group>
+            <property-group name="PROGRAMMING_INFO">
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
+            </property-group>
+            <property-group name="UPDI_INTERFACE">
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
+            </property-group>
+            <property-group name="SIGNATURES">
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x95"/>
+                <property name="SIGNATURE2" value="0x38"/>
+            </property-group>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="WINSEL" value="0x00"/>
+                    <mode name="WINDOW" qualifier="WINSEL" value="0x01 0x02"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Shortest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+                <value caption="Power profile 2" name="PROFILE2" value="0x2"/>
+                <value caption="Power profile 3" name="PROFILE3" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_v1"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x18">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Free running mode" mask="0x02" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Resolution selection"
+                              mask="0x0C"
+                              name="RESSEL"
+                              rw="RW"
+                              values="ADC_RESSEL"/>
+                    <bitfield caption="Left adjust result" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Conversion mode"
+                              mask="0x20"
+                              name="CONVMODE"
+                              rw="RW"
+                              values="ADC_CONVMODE"/>
+                    <bitfield caption="Run standby mode" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Accumulation Samples"
+                              mask="0x07"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Pre-scaler"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sampling Delay Selection"
+                              mask="0x0F"
+                              name="SAMPDLY"
+                              rw="RW"
+                              values="ADC_SAMPDLY"/>
+                    <bitfield caption="Initial Delay Selection"
+                              mask="0xE0"
+                              name="INITDLY"
+                              rw="RW"
+                              values="ADC_INITDLY"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                </register>
+                <register caption="Sample Control"
+                          initval="0x00"
+                          name="SAMPCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample lenght" mask="0xFF" name="SAMPLEN" rw="RW"/>
+                </register>
+                <register caption="Positive mux input"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                </register>
+                <register caption="Negative mux input"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x7F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                </register>
+                <register caption="Command"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Conversion" mask="0x01" name="STCONV" rw="RW"/>
+                    <bitfield caption="Stop Conversion" mask="0x02" name="SPCONV" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start Event Input Enable"
+                              mask="0x01"
+                              name="STARTEI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Flag" mask="0x01" name="RESRDY" rw="RW"/>
+                    <bitfield caption="Window Comparator Flag"
+                              mask="0x02"
+                              name="WCMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Data"
+                          initval="0x00"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Temporary" mask="0xFF" name="TEMP" rw="RW"/>
+                </register>
+                <register caption="ADC Accumulator Result"
+                          name="RES"
+                          offset="0x10"
+                          rw="R"
+                          size="2"/>
+                <register caption="Window comparator low threshold"
+                          name="WINLT"
+                          offset="0x12"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window comparator high threshold"
+                          name="WINHT"
+                          offset="0x14"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Conversion mode select" name="ADC_CONVMODE">
+                <value caption="Single-Ended mode" name="SINGLEENDED" value="0x0"/>
+                <value caption="Differential mode" name="DIFF" value="0x1"/>
+            </value-group>
+            <value-group caption="Resolution selection" name="ADC_RESSEL">
+                <value caption="12-bit mode" name="12BIT" value="0x0"/>
+                <value caption="10-bit mode" name="10BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Accumulation Samples select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x00"/>
+                <value caption="2 results accumulated" name="ACC2" value="0x01"/>
+                <value caption="4 results accumulated" name="ACC4" value="0x02"/>
+                <value caption="8 results accumulated" name="ACC8" value="0x03"/>
+                <value caption="16 results accumulated" name="ACC16" value="0x04"/>
+                <value caption="32 results accumulated" name="ACC32" value="0x05"/>
+                <value caption="64 results accumulated" name="ACC64" value="0x06"/>
+                <value caption="128 results accumulated" name="ACC128" value="0x7"/>
+            </value-group>
+            <value-group caption="Clock Pre-scaler select" name="ADC_PRESC">
+                <value caption="CLK_PER divided by 2" name="DIV2" value="0x00"/>
+                <value caption="CLK_PER divided by 4" name="DIV4" value="0x01"/>
+                <value caption="CLK_PER divided by 8" name="DIV8" value="0x02"/>
+                <value caption="CLK_PER divided by 12" name="DIV12" value="0x03"/>
+                <value caption="CLK_PER divided by 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER divided by 20" name="DIV20" value="0x05"/>
+                <value caption="CLK_PER divided by 24" name="DIV24" value="0x06"/>
+                <value caption="CLK_PER divided by 28" name="DIV28" value="0x07"/>
+                <value caption="CLK_PER divided by 32" name="DIV32" value="0x08"/>
+                <value caption="CLK_PER divided by 48" name="DIV48" value="0x09"/>
+                <value caption="CLK_PER divided by 64" name="DIV64" value="0x0A"/>
+                <value caption="CLK_PER divided by 96" name="DIV96" value="0x0B"/>
+                <value caption="CLK_PER divided by 128" name="DIV128" value="0x0C"/>
+                <value caption="CLK_PER divided by 256" name="DIV256" value="0x0D"/>
+            </value-group>
+            <value-group caption="Initial Delay Selection" name="ADC_INITDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x00"/>
+                <value caption="Delay 16 CLK_ADC cycles" name="DLY16" value="0x01"/>
+                <value caption="Delay 32 CLK_ADC cycles" name="DLY32" value="0x02"/>
+                <value caption="Delay 64 CLK_ADC cycles" name="DLY64" value="0x03"/>
+                <value caption="Delay 128 CLK_ADC cycles" name="DLY128" value="0x04"/>
+                <value caption="Delay 256 CLK_ADC cycles" name="DLY256" value="0x05"/>
+            </value-group>
+            <value-group caption="Sampling Delay Selection" name="ADC_SAMPDLY">
+                <value caption="Delay 0 CLK_ADC cycles" name="DLY0" value="0x0"/>
+                <value caption="Delay 1 CLK_ADC cycles" name="DLY1" value="0x1"/>
+                <value caption="Delay 2 CLK_ADC cycles" name="DLY2" value="0x2"/>
+                <value caption="Delay 3 CLK_ADC cycles" name="DLY3" value="0x3"/>
+                <value caption="Delay 4 CLK_ADC cycles" name="DLY4" value="0x4"/>
+                <value caption="Delay 5 CLK_ADC cycles" name="DLY5" value="0x5"/>
+                <value caption="Delay 6 CLK_ADC cycles" name="DLY6" value="0x6"/>
+                <value caption="Delay 7 CLK_ADC cycles" name="DLY7" value="0x7"/>
+                <value caption="Delay 8 CLK_ADC cycles" name="DLY8" value="0x8"/>
+                <value caption="Delay 9 CLK_ADC cycles" name="DLY9" value="0x9"/>
+                <value caption="Delay 10 CLK_ADC cycles" name="DLY10" value="0xA"/>
+                <value caption="Delay 11 CLK_ADC cycles" name="DLY11" value="0xB"/>
+                <value caption="Delay 12 CLK_ADC cycles" name="DLY12" value="0xC"/>
+                <value caption="Delay 13 CLK_ADC cycles" name="DLY13" value="0xD"/>
+                <value caption="Delay 14 CLK_ADC cycles" name="DLY14" value="0xE"/>
+                <value caption="Delay 15 CLK_ADC cycles" name="DLY15" value="0xF"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x40"/>
+                <value caption="Temperature sensor" name="TEMPSENSE" value="0x42"/>
+                <value caption="VDD/10" name="VDDDIV10" value="0x44"/>
+                <value caption="VDDIO2/10" name="VDDIO2DIV10" value="0x45"/>
+                <value caption="DAC0" name="DAC0" value="0x48"/>
+                <value caption="DACREF0" name="DACREF0" value="0x49"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_v1" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled with wake-up halted until BOD is ready"
+                       name="ENWAKE"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="128Hz sampling frequency" name="128HZ" value="0x0"/>
+                <value caption="32Hz sampling frequency" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DIS" value="0x00"/>
+                <value caption="Enabled" name="ENABLED" value="0x01"/>
+                <value caption="Sampled" name="SAMPLED" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="1.9 V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="Selection by INSEL2" name="IN2" value="0x1"/>
+                <value caption="Internal High-Frequency Oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN0 input source" name="IN0" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART0 TXD input source" name="USART0" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0x0B"/>
+                <value caption="TCD0 WOA input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN1 input source" name="IN1" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 MOSI input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0x0B"/>
+                <value caption="TCD0 WOB input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x00"/>
+                <value caption="Feedback input source" name="FEEDBACK" value="0x01"/>
+                <value caption="Linked LUT input source" name="LINK" value="0x02"/>
+                <value caption="Event input source A" name="EVENTA" value="0x03"/>
+                <value caption="Event input source B" name="EVENTB" value="0x04"/>
+                <value caption="IO pin LUTn-IN2 input source" name="IN2" value="0x05"/>
+                <value caption="AC0 OUT input source" name="AC0" value="0x06"/>
+                <value caption="ZCD3 OUT input source" name="ZCD3" value="0x07"/>
+                <value caption="USART1 TXD input source" name="USART1" value="0x08"/>
+                <value caption="SPI0 SCK input source" name="SPI0" value="0x09"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x0A"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0x0B"/>
+                <value caption="TCD0 WOC input source" name="TCD0" value="0x0C"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrdd" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x40">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x00"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Clock Failure Detect Test"
+                              mask="0x02"
+                              name="CFDTST"
+                              rw="W"/>
+                    <bitfield caption="Clock Failure Detect Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Enable"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Interrupt Flag"
+                              mask="0x01"
+                              name="CFD"
+                              rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="RW"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="RW"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="RW"/>
+                    <bitfield caption="External Clock status" mask="0x10" name="EXTS" rw="RW"/>
+                    <bitfield caption="PLL oscillator status" mask="0x20" name="PLLS" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Autotune" mask="0x01" name="AUTOTUNE" rw="RW"/>
+                    <bitfield caption="Frequency select"
+                              mask="0x3C"
+                              name="FRQSEL"
+                              rw="RW"
+                              values="CLKCTRL_FRQSEL"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="PLL Control A"
+                          name="PLLCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multiplication factor"
+                              mask="0x03"
+                              name="MULFAC"
+                              rw="RW"
+                              values="CLKCTRL_MULFAC"/>
+                    <bitfield caption="Source"
+                              mask="0x40"
+                              name="SOURCE"
+                              rw="RW"
+                              values="CLKCTRL_SOURCE"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC HF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="External Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Frequency Range"
+                              mask="0x0C"
+                              name="FRQRANGE"
+                              rw="RW"
+                              values="CLKCTRL_FRQRANGE"/>
+                    <bitfield caption="Start-up Time Select"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run Standby" mask="0x80" name="RUNSTBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="2X" name="2X" value="0x00"/>
+                <value caption="4X" name="4X" value="0x01"/>
+                <value caption="8X" name="8X" value="0x02"/>
+                <value caption="16X" name="16X" value="0x03"/>
+                <value caption="32X" name="32X" value="0x04"/>
+                <value caption="64X" name="64X" value="0x05"/>
+                <value caption="6X" name="6X" value="0x08"/>
+                <value caption="10X" name="10X" value="0x09"/>
+                <value caption="12X" name="12X" value="0x0A"/>
+                <value caption="24X" name="24X" value="0x0B"/>
+                <value caption="48X" name="48X" value="0x0C"/>
+            </value-group>
+            <value-group caption="Clock Failure Detect Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="XOSCHF" name="XOSCHF" value="0x1"/>
+                <value caption="XOSC32K" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular Interrupt" name="INT" value="0x0"/>
+                <value caption="NMI" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Frequency select" name="CLKCTRL_FRQSEL">
+                <value caption="1 MHz system clock" name="1M" value="0x0"/>
+                <value caption="2 MHz system clock" name="2M" value="0x1"/>
+                <value caption="3 MHz system clock" name="3M" value="0x2"/>
+                <value caption="4 MHz system clock (default)" name="4M" value="0x3"/>
+                <value caption="8 MHz system clock" name="8M" value="0x5"/>
+                <value caption="12 MHz system clock" name="12M" value="0x6"/>
+                <value caption="16 MHz system clock" name="16M" value="0x7"/>
+                <value caption="20 MHz system clock" name="20M" value="0x8"/>
+                <value caption="24 MHz system clock" name="24M" value="0x9"/>
+            </value-group>
+            <value-group caption="Multiplication factor select" name="CLKCTRL_MULFAC">
+                <value caption="PLL is disabled" name="DISABLE" value="0x0"/>
+                <value caption="2 x multiplication factor" name="2x" value="0x1"/>
+                <value caption="3 x multiplication factor" name="3x" value="0x2"/>
+            </value-group>
+            <value-group caption="Source select" name="CLKCTRL_SOURCE">
+                <value caption="High frequency internal oscillator as PLL source"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="High frequency external clock or external high frequency oscillator as PLL source"
+                       name="XOSCHF"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-up Time Select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF cycles" name="256" value="0x0"/>
+                <value caption="1K XOSCHF cycles" name="1K" value="0x1"/>
+                <value caption="4K XOSCHF cycles" name="4K" value="0x2"/>
+            </value-group>
+            <value-group caption="Frequency Range select" name="CLKCTRL_FRQRANGE">
+                <value caption="Max 8 MHz XTAL Frequency" name="8M" value="0x0"/>
+                <value caption="Max 16 MHz XTAL Frequency" name="16M" value="0x1"/>
+                <value caption="Max 24 MHz XTAL Frequency" name="24M" value="0x2"/>
+                <value caption="Max 32 MHz XTAL Frequency" name="32M" value="0x3"/>
+            </value-group>
+            <value-group caption="External Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="XTAL" value="0x0"/>
+                <value caption="External clock on XTALHF1 pin" name="EXTCLOCK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_v5"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x4">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Event System" id="avrdd" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Software Event B"
+                          initval="0x00"
+                          name="SWEVENTB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0x03"
+                              name="SWEVENTB"
+                              rw="W"
+                              values="EVSYS_SWEVENTB"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 0 generator select"
+                              mask="0xFF"
+                              name="CHANNEL0"
+                              rw="RW"
+                              values="EVSYS_CHANNEL0"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 1 generator select"
+                              mask="0xFF"
+                              name="CHANNEL1"
+                              rw="RW"
+                              values="EVSYS_CHANNEL1"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 2 generator select"
+                              mask="0xFF"
+                              name="CHANNEL2"
+                              rw="RW"
+                              values="EVSYS_CHANNEL2"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 3 generator select"
+                              mask="0xFF"
+                              name="CHANNEL3"
+                              rw="RW"
+                              values="EVSYS_CHANNEL3"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 4 generator select"
+                              mask="0xFF"
+                              name="CHANNEL4"
+                              rw="RW"
+                              values="EVSYS_CHANNEL4"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel 5 generator select"
+                              mask="0xFF"
+                              name="CHANNEL5"
+                              rw="RW"
+                              values="EVSYS_CHANNEL5"/>
+                </register>
+                <register caption="User 0 - CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 1 - CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 2 - CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 3 - CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 4 - CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 5 - CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 6 - CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 7 - CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 12 - ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 13 - EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 15 - EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 16 - EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 18 - EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 20 - USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 21 - USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 26 - TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 27 - TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 30 - TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 31 - TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 32 - TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 33 - TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 34 - TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 35 - TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 40 - TCD0 Event A"
+                          initval="0x00"
+                          name="USERTCD0INPUTA"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="User 41 - TCD0 Event B"
+                          initval="0x00"
+                          name="USERTCD0INPUTB"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel 0 generator select" name="EVSYS_CHANNEL0">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 1 generator select" name="EVSYS_CHANNEL1">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port A Pin 0" name="PORTA_PIN0" value="0x40"/>
+                <value caption="Port A Pin 1" name="PORTA_PIN1" value="0x41"/>
+                <value caption="Port A Pin 2" name="PORTA_PIN2" value="0x42"/>
+                <value caption="Port A Pin 3" name="PORTA_PIN3" value="0x43"/>
+                <value caption="Port A Pin 4" name="PORTA_PIN4" value="0x44"/>
+                <value caption="Port A Pin 5" name="PORTA_PIN5" value="0x45"/>
+                <value caption="Port A Pin 6" name="PORTA_PIN6" value="0x46"/>
+                <value caption="Port A Pin 7" name="PORTA_PIN7" value="0x47"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 2 generator select" name="EVSYS_CHANNEL2">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 3 generator select" name="EVSYS_CHANNEL3">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port C Pin 0" name="PORTC_PIN0" value="0x40"/>
+                <value caption="Port C Pin 1" name="PORTC_PIN1" value="0x41"/>
+                <value caption="Port C Pin 2" name="PORTC_PIN2" value="0x42"/>
+                <value caption="Port C Pin 3" name="PORTC_PIN3" value="0x43"/>
+                <value caption="Port D Pin 1" name="PORTD_PIN1" value="0x49"/>
+                <value caption="Port D Pin 2" name="PORTD_PIN2" value="0x4A"/>
+                <value caption="Port D Pin 3" name="PORTD_PIN3" value="0x4B"/>
+                <value caption="Port D Pin 4" name="PORTD_PIN4" value="0x4C"/>
+                <value caption="Port D Pin 5" name="PORTD_PIN5" value="0x4D"/>
+                <value caption="Port D Pin 6" name="PORTD_PIN6" value="0x4E"/>
+                <value caption="Port D Pin 7" name="PORTD_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 4 generator select" name="EVSYS_CHANNEL4">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV8192"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV4096"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV2048"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV1024"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
+                <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
+                <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
+                <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Channel 5 generator select" name="EVSYS_CHANNEL5">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="MVIO VDDIO2 OK" name="MVIO" value="0x5"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer output 0"
+                       name="RTC_PIT_DIV512"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer output 1"
+                       name="RTC_PIT_DIV256"
+                       value="0x9"/>
+                <value caption="Periodic Interrupt Timer output 2"
+                       name="RTC_PIT_DIV128"
+                       value="0xA"/>
+                <value caption="Periodic Interrupt Timer output 3"
+                       name="RTC_PIT_DIV64"
+                       value="0xB"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RESRDY" value="0x24"/>
+                <value caption="Zero Cross Detect 3 out" name="ZCD3" value="0x30"/>
+                <value caption="Port F Pin 0" name="PORTF_PIN0" value="0x48"/>
+                <value caption="Port F Pin 1" name="PORTF_PIN1" value="0x49"/>
+                <value caption="Port F Pin 2" name="PORTF_PIN2" value="0x4A"/>
+                <value caption="Port F Pin 3" name="PORTF_PIN3" value="0x4B"/>
+                <value caption="Port F Pin 4" name="PORTF_PIN4" value="0x4C"/>
+                <value caption="Port F Pin 5" name="PORTF_PIN5" value="0x4D"/>
+                <value caption="Port F Pin 6" name="PORTF_PIN6" value="0x4E"/>
+                <value caption="Port F Pin 7" name="PORTF_PIN7" value="0x4F"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter D0 event 0" name="TCD0_CMPBCLR" value="0xB0"/>
+                <value caption="Timer/Counter D0 event 1" name="TCD0_CMPASET" value="0xB1"/>
+                <value caption="Timer/Counter D0 event 2" name="TCD0_CMPBSET" value="0xB2"/>
+                <value caption="Timer/Counter D0 event 3" name="TCD0_PROGEV" value="0xB3"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTB">
+                <value caption="Software event on channel 8" name="CH8" value="0x0"/>
+                <value caption="Software event on channel 9" name="CH9" value="0x1"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrdd" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Frequency Select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="FUSE_CLKSEL"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save" mask="0x01" name="EESAVE" rw="RW"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x08"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                    <bitfield caption="MVIO System Configuration"
+                              mask="0x18"
+                              name="MVSYSCFG"
+                              rw="RW"
+                              values="FUSE_MVSYSCFG"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+                <value caption="BOD enabled in continuous mode. Execution is halted at wake-up until BOD is running."
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="1.9V" name="BODLEVEL0" value="0x00"/>
+                <value caption="2.45V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7V" name="BODLEVEL2" value="0x02"/>
+                <value caption="2.85V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sample frequency is 128 Hz" name="128Hz" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32Hz" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="BOD disabled" name="DISABLE" value="0x00"/>
+                <value caption="BOD enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="BOD enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Frequency Select" name="FUSE_CLKSEL">
+                <value caption="1-32MHz internal oscillator" name="OSCHF" value="0x0"/>
+                <value caption="32.768kHz internal oscillator" name="OSC32K" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="GPIO mode" name="GPIO" value="0x0"/>
+                <value caption="Reset mode" name="RST" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="GPIO Mode" name="GPIO" value="0x0"/>
+                <value caption="UPDI Mode" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="MVIO System Configuration select" name="FUSE_MVSYSCFG">
+                <value caption="Device used in a dual supply configuration"
+                       name="DUAL"
+                       value="0x1"/>
+                <value caption="Device used in a single supply configuration"
+                       name="SINGLE"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrdd" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x3"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrdd" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Multi-Voltage I/O" id="io_multiv_ctrl_avr_v1" name="MVIO">
+            <register-group caption="Multi-Voltage I/O" name="MVIO" size="0x4">
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Enable"
+                              mask="0x01"
+                              name="VDDIO2IE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="VDDIO2 Interrupt Flag"
+                              mask="0x01"
+                              name="VDDIO2IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="VDDIO2 Status" mask="0x01" name="VDDIO2S" rw="R"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v1"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x02"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Flash busy" mask="0x01" name="FBUSY" rw="R"/>
+                    <bitfield caption="EEPROM busy" mask="0x02" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x06" rw="RW" size="2"/>
+                <register caption="Address"
+                          name="ADDR"
+                          offset="0x08"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Write" name="FLWR" value="0x02"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash Multi-Page Erase 2 pages"
+                       name="FLMPER2"
+                       value="0x09"/>
+                <value caption="Flash Multi-Page Erase 4 pages"
+                       name="FLMPER4"
+                       value="0x0A"/>
+                <value caption="Flash Multi-Page Erase 8 pages"
+                       name="FLMPER8"
+                       value="0x0B"/>
+                <value caption="Flash Multi-Page Erase 16 pages"
+                       name="FLMPER16"
+                       value="0x0C"/>
+                <value caption="Flash Multi-Page Erase 32 pages"
+                       name="FLMPER32"
+                       value="0x0D"/>
+                <value caption="EEPROM Write" name="EEWR" value="0x12"/>
+                <value caption="EEPROM Erase and Write" name="EEERWR" value="0x13"/>
+                <value caption="EEPROM Byte Erase" name="EEBER" value="0x18"/>
+                <value caption="EEPROM Multi-Byte Erase 2 bytes"
+                       name="EEMBER2"
+                       value="0x19"/>
+                <value caption="EEPROM Multi-Byte Erase 4 bytes"
+                       name="EEMBER4"
+                       value="0x1A"/>
+                <value caption="EEPROM Multi-Byte Erase 8 bytes"
+                       name="EEMBER8"
+                       value="0x1B"/>
+                <value caption="EEPROM Multi-Byte Erase 16 bytes"
+                       name="EEMBER16"
+                       value="0x1C"/>
+                <value caption="EEPROM Multi-Byte Erase 32 bytes"
+                       name="EEMBER32"
+                       value="0x1D"/>
+                <value caption="Chip Erase Command" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command" name="EECHER" value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Write command not selected" name="ILLEGALCMD" value="0x1"/>
+                <value caption="Write to section not allowed"
+                       name="ILLEGALSADDR"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="DOUBLESELECT"
+                       value="0x3"/>
+                <value caption="Starting a new programming operation before previous is completed"
+                       name="ONGOINGPROG"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v2_port" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control update mask"
+                              mask="0xFF"
+                              name="PINCTRLUPD"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control set mask"
+                              mask="0xFF"
+                              name="PINCTRLSET"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin control clear mask"
+                              mask="0xFF"
+                              name="PINCTRLCLR"
+                              rw="RW"/>
+                </register>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input level select" mask="0x40" name="INLVL" rw="RW"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrdd" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x10">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                    <bitfield caption="CCL Look-Up Table 3 Signals"
+                              mask="0x08"
+                              name="LUT3"
+                              rw="RW"
+                              values="PORTMUX_LUT3"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Signals"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Signals"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                </register>
+                <register caption="TCD route A"
+                          initval="0x00"
+                          name="TCDROUTEA"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCD0 Signals"
+                              mask="0x07"
+                              name="TCD0"
+                              rw="RW"
+                              values="PORTMUX_TCD0"/>
+                </register>
+            </register-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 3 Signals select" name="PORTMUX_LUT3">
+                <value caption="Out: PF3 In: PF0, PF1, PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC0, PC1" name="ALT3" value="0x3"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT4" value="0x4"/>
+                <value caption="PC0, PC1, PC2, PC3" name="ALT5" value="0x5"/>
+                <value caption="PC1, PC2, PC3, PF7" name="ALT6" value="0x6"/>
+                <value caption="NA, NA, NA, Set to 1" name="NONE" value="0x7"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+                <value caption="PG0, PG1, PG2, PG3, PG4, PG5" name="PORTG" value="0x6"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="WO on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="WO on PA3" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="WO on PC0" name="DEFAULT" value="0x0"/>
+                <value caption="WO on PB4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCD0 Signals select" name="PORTMUX_TCD0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PB4, PB5, PB6, PB7" name="ALT1" value="0x1"/>
+                <value caption="PF0, PF1, PF2, PF3" name="ALT2" value="0x2"/>
+                <value caption="PG4, PG5, PG6, PG7" name="ALT3" value="0x3"/>
+                <value caption="PA4, PA5, PD4, PD5" name="ALT4" value="0x4"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="PA2, PA3, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PA2, PA3, PC6, PC7" name="ALT1" value="0x1"/>
+                <value caption="PC2, PC3, PC6, PC7" name="ALT2" value="0x2"/>
+                <value caption="PA0, PA1, PC2, PC3" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Signals select" name="PORTMUX_USART0">
+                <value caption="PA0, PA1, PA2, PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PA4, PA5, PA6, PA7" name="ALT1" value="0x1"/>
+                <value caption="PA2, PA3" name="ALT2" value="0x2"/>
+                <value caption="PD4, PD5, PD6, PD7" name="ALT3" value="0x3"/>
+                <value caption="PC1, PC2, PC3" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Signals select" name="PORTMUX_USART1">
+                <value caption="PC0, PC1, PC2, PC3" name="DEFAULT" value="0x0"/>
+                <value caption="PD6, PD7" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller" id="rst_integration_v8" name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x4">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software reset enable"
+                              mask="0x01"
+                              name="SWRST"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_v1" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="32.768 kHz from OSC32K" name="OSC32K" value="0x0"/>
+                <value caption="1.024 kHz from OSC32K" name="OSC1K" value="0x1"/>
+                <value caption="32.768 kHz from XOSC32K" name="XTAL32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrdd" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 0"
+                              mask="0xFFFF"
+                              name="TEMPSENSE0"
+                              rw="R"/>
+                </register>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2">
+                    <bitfield caption="Temperature Calibration 1"
+                              mask="0xFFFF"
+                              name="TEMPSENSE1"
+                              rw="R"/>
+                </register>
+                <register caption="LOTNUM0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="LOTNUM5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="RANDOM"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="SCRIBE"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS0"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="XPOS1"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS0"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="YPOS1"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES0"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES1"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES2"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="RES3"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v2"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="VREGCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Performance Mode"
+                              mask="0x07"
+                              name="PMODE"
+                              rw="RW"
+                              values="SLPCTRL_PMODE"/>
+                    <bitfield caption="High Temperature Low Leakage Enable"
+                              mask="0x10"
+                              name="HTLLEN"
+                              rw="RW"
+                              values="SLPCTRL_HTLLEN"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+            <value-group caption="High Temperature Low Leakage Enable select"
+                         name="SLPCTRL_HTLLEN">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Enabled" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Performance Mode select" name="SLPCTRL_PMODE">
+                <value caption="" name="AUTO" value="0x0"/>
+                <value caption="" name="FULL" value="0x1"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrdd" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Timer Counter D" id="tmr_12b_psc_v1" name="TCD">
+            <register-group caption="Timer Counter D" name="TCD" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Synchronization prescaler"
+                              mask="0x06"
+                              name="SYNCPRES"
+                              rw="RW"
+                              values="TCD_SYNCPRES"/>
+                    <bitfield caption="Counter prescaler"
+                              mask="0x18"
+                              name="CNTPRES"
+                              rw="RW"
+                              values="TCD_CNTPRES"/>
+                    <bitfield caption="Clock select"
+                              mask="0x60"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCD_CLKSEL"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x03"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCD_WGMODE"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare output value override"
+                              mask="0x01"
+                              name="CMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Auto update" mask="0x02" name="AUPDATE" rw="RW"/>
+                    <bitfield caption="Fifty percent waveform"
+                              mask="0x08"
+                              name="FIFTY"
+                              rw="RW"/>
+                    <bitfield caption="Compare C output select"
+                              mask="0x40"
+                              name="CMPCSEL"
+                              rw="RW"
+                              values="TCD_CMPCSEL"/>
+                    <bitfield caption="Compare D output select"
+                              mask="0x80"
+                              name="CMPDSEL"
+                              rw="RW"
+                              values="TCD_CMPDSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x0F" name="CMPAVAL" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0xF0" name="CMPBVAL" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Synchronize end of cycle strobe"
+                              mask="0x01"
+                              name="SYNCEOC"
+                              rw="RW"/>
+                    <bitfield caption="synchronize strobe" mask="0x02" name="SYNC" rw="RW"/>
+                    <bitfield caption="Restart strobe" mask="0x04" name="RESTART" rw="RW"/>
+                    <bitfield caption="Software Capture A Strobe"
+                              mask="0x08"
+                              name="SCAPTUREA"
+                              rw="RW"/>
+                    <bitfield caption="Software Capture B Strobe"
+                              mask="0x10"
+                              name="SCAPTUREB"
+                              rw="RW"/>
+                    <bitfield caption="Disable at end of cycle"
+                              mask="0x80"
+                              name="DISEOC"
+                              rw="RW"/>
+                </register>
+                <register caption="EVCTRLA"
+                          initval="0x00"
+                          name="EVCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="EVCTRLB"
+                          initval="0x00"
+                          name="EVCTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Trigger event enable"
+                              mask="0x01"
+                              name="TRIGEI"
+                              rw="RW"/>
+                    <bitfield caption="Event action"
+                              mask="0x04"
+                              name="ACTION"
+                              rw="RW"
+                              values="TCD_ACTION"/>
+                    <bitfield caption="Edge select"
+                              mask="0x10"
+                              name="EDGE"
+                              rw="RW"
+                              values="TCD_EDGE"/>
+                    <bitfield caption="Event config"
+                              mask="0xC0"
+                              name="CFG"
+                              rw="RW"
+                              values="TCD_CFG"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Trigger A interrupt enable"
+                              mask="0x04"
+                              name="TRIGA"
+                              rw="RW"/>
+                    <bitfield caption="Trigger B interrupt enable"
+                              mask="0x08"
+                              name="TRIGB"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable ready" mask="0x01" name="ENRDY" rw="R"/>
+                    <bitfield caption="Command ready" mask="0x02" name="CMDRDY" rw="R"/>
+                    <bitfield caption="PWM activity on A" mask="0x40" name="PWMACTA" rw="RW"/>
+                    <bitfield caption="PWM activity on B" mask="0x80" name="PWMACTB" rw="RW"/>
+                </register>
+                <register caption="Input Control A"
+                          initval="0x00"
+                          name="INPUTCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Input Control B"
+                          initval="0x00"
+                          name="INPUTCTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input mode"
+                              mask="0x0F"
+                              name="INPUTMODE"
+                              rw="RW"
+                              values="TCD_INPUTMODE"/>
+                </register>
+                <register caption="Fault Control"
+                          initval="0x00"
+                          name="FAULTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare A value" mask="0x01" name="CMPA" rw="RW"/>
+                    <bitfield caption="Compare B value" mask="0x02" name="CMPB" rw="RW"/>
+                    <bitfield caption="Compare C value" mask="0x04" name="CMPC" rw="RW"/>
+                    <bitfield caption="Compare D vaule" mask="0x08" name="CMPD" rw="RW"/>
+                    <bitfield caption="Compare A enable" mask="0x10" name="CMPAEN" rw="RW"/>
+                    <bitfield caption="Compare B enable" mask="0x20" name="CMPBEN" rw="RW"/>
+                    <bitfield caption="Compare C enable" mask="0x40" name="CMPCEN" rw="RW"/>
+                    <bitfield caption="Compare D enable" mask="0x80" name="CMPDEN" rw="RW"/>
+                </register>
+                <register caption="Delay Control"
+                          initval="0x00"
+                          name="DLYCTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay select"
+                              mask="0x03"
+                              name="DLYSEL"
+                              rw="RW"
+                              values="TCD_DLYSEL"/>
+                    <bitfield caption="Delay trigger"
+                              mask="0x0C"
+                              name="DLYTRIG"
+                              rw="RW"
+                              values="TCD_DLYTRIG"/>
+                    <bitfield caption="Delay prescaler"
+                              mask="0x30"
+                              name="DLYPRESC"
+                              rw="RW"
+                              values="TCD_DLYPRESC"/>
+                </register>
+                <register caption="Delay value"
+                          initval="0x00"
+                          name="DLYVAL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Delay value" mask="0xFF" name="DLYVAL" rw="RW"/>
+                </register>
+                <register caption="Dither Control A"
+                          initval="0x00"
+                          name="DITCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither select"
+                              mask="0x03"
+                              name="DITHERSEL"
+                              rw="RW"
+                              values="TCD_DITHERSEL"/>
+                </register>
+                <register caption="Dither value"
+                          initval="0x00"
+                          name="DITVAL"
+                          offset="0x19"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Dither value" mask="0x0F" name="DITHER" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug run" mask="0x01" name="DBGRUN" rw="RW"/>
+                    <bitfield caption="Fault detection" mask="0x04" name="FAULTDET" rw="RW"/>
+                </register>
+                <register caption="Capture A"
+                          name="CAPTUREA"
+                          offset="0x22"
+                          rw="R"
+                          size="2"/>
+                <register caption="Capture B"
+                          name="CAPTUREB"
+                          offset="0x24"
+                          rw="R"
+                          size="2"/>
+                <register caption="Compare A Set"
+                          name="CMPASET"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare A Clear"
+                          name="CMPACLR"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Set"
+                          name="CMPBSET"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare B Clear"
+                          name="CMPBCLR"
+                          offset="0x2E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock select" name="TCD_CLKSEL">
+                <value caption="Internal High-Frequency oscillator"
+                       name="OSCHF"
+                       value="0x00"/>
+                <value caption="PLL" name="PLL" value="0x01"/>
+                <value caption="External Clock" name="EXTCLK" value="0x02"/>
+                <value caption="Peripheral clock" name="CLKPER" value="0x03"/>
+            </value-group>
+            <value-group caption="Counter prescaler select" name="TCD_CNTPRES">
+                <value caption="Sync clock divided by 1" name="DIV1" value="0x00"/>
+                <value caption="Sync clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="Sync clock divided by 32" name="DIV32" value="0x02"/>
+            </value-group>
+            <value-group caption="Synchronization prescaler select" name="TCD_SYNCPRES">
+                <value caption="Selected clock source divided by 1"
+                       name="DIV1"
+                       value="0x00"/>
+                <value caption="Selected clock source divided by 2"
+                       name="DIV2"
+                       value="0x01"/>
+                <value caption="Selected clock source divided by 4"
+                       name="DIV4"
+                       value="0x02"/>
+                <value caption="Selected clock source divided by 8"
+                       name="DIV8"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCD_WGMODE">
+                <value caption="One ramp mode" name="ONERAMP" value="0x0"/>
+                <value caption="Two ramp mode" name="TWORAMP" value="0x1"/>
+                <value caption="Four ramp mode" name="FOURRAMP" value="0x2"/>
+                <value caption="Dual slope mode" name="DS" value="0x3"/>
+            </value-group>
+            <value-group caption="Compare C output select" name="TCD_CMPCSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Compare D output select" name="TCD_CMPDSEL">
+                <value caption="PWM A output" name="PWMA" value="0x0"/>
+                <value caption="PWM B output" name="PWMB" value="0x1"/>
+            </value-group>
+            <value-group caption="Dither select" name="TCD_DITHERSEL">
+                <value caption="On-time ramp B" name="ONTIMEB" value="0x0"/>
+                <value caption="On-time ramp A and B" name="ONTIMEAB" value="0x1"/>
+                <value caption="Dead-time rampB" name="DEADTIMEB" value="0x2"/>
+                <value caption="Dead-time ramp A and B" name="DEADTIMEAB" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay prescaler select" name="TCD_DLYPRESC">
+                <value caption="No prescaling" name="DIV1" value="0x0"/>
+                <value caption="Prescale with 2" name="DIV2" value="0x1"/>
+                <value caption="Prescale with 4" name="DIV4" value="0x2"/>
+                <value caption="Prescale with 8" name="DIV8" value="0x3"/>
+            </value-group>
+            <value-group caption="Delay select" name="TCD_DLYSEL">
+                <value caption="No delay" name="OFF" value="0x0"/>
+                <value caption="Input blanking enabled" name="INBLANK" value="0x1"/>
+                <value caption="Event delay enabled" name="EVENT" value="0x2"/>
+            </value-group>
+            <value-group caption="Delay trigger select" name="TCD_DLYTRIG">
+                <value caption="Compare A set" name="CMPASET" value="0x0"/>
+                <value caption="Compare A clear" name="CMPACLR" value="0x1"/>
+                <value caption="Compare B set" name="CMPBSET" value="0x2"/>
+                <value caption="Compare B clear" name="CMPBCLR" value="0x3"/>
+            </value-group>
+            <value-group caption="Event action select" name="TCD_ACTION">
+                <value caption="Event trigger a fault" name="FAULT" value="0x0"/>
+                <value caption="Event trigger a fault and capture"
+                       name="CAPTURE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Event config select" name="TCD_CFG">
+                <value caption="Neither Filter nor Asynchronous Event is enabled"
+                       name="NEITHER"
+                       value="0x0"/>
+                <value caption="Input Capture Noise Cancellation Filter enabled"
+                       name="FILTER"
+                       value="0x1"/>
+                <value caption="Asynchronous Event output qualification enabled"
+                       name="ASYNC"
+                       value="0x2"/>
+            </value-group>
+            <value-group caption="Edge select" name="TCD_EDGE">
+                <value caption="The falling edge or low level of event generates retrigger or fault action"
+                       name="FALL_LOW"
+                       value="0x0"/>
+                <value caption="The rising edge or high level of event generates retrigger or fault action"
+                       name="RISE_HIGH"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Input mode select" name="TCD_INPUTMODE">
+                <value caption="Input has no actions" name="NONE" value="0x00"/>
+                <value caption="Stop output, jump to opposite compare cycle and wait"
+                       name="JMPWAIT"
+                       value="0x01"/>
+                <value caption="Stop output, execute opposite compare cycle and wait"
+                       name="EXECWAIT"
+                       value="0x02"/>
+                <value caption="stop output, execute opposite compare cycle while fault active"
+                       name="EXECFAULT"
+                       value="0x03"/>
+                <value caption="Stop all outputs, maintain frequency"
+                       name="FREQ"
+                       value="0x04"/>
+                <value caption="Stop all outputs, execute dead time while fault active"
+                       name="EXECDT"
+                       value="0x05"/>
+                <value caption="Stop all outputs, jump to next compare cycle and wait"
+                       name="WAIT"
+                       value="0x06"/>
+                <value caption="Stop all outputs, wait for software action"
+                       name="WAITSW"
+                       value="0x07"/>
+                <value caption="Stop output on edge, jump to next compare cycle"
+                       name="EDGETRIG"
+                       value="0x08"/>
+                <value caption="Stop output on edge, maintain frequency"
+                       name="EDGETRIGFREQ"
+                       value="0x09"/>
+                <value caption="Stop output at level, maintain frequency"
+                       name="LVLTRIGFREQ"
+                       value="0x0A"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrdd" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x20">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v2_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrdd" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="ADC0 Reference"
+                          initval="0x00"
+                          name="ADC0REF"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x00"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x01"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x02"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x03"/>
+                <value caption="VDD as reference" name="VDD" value="0x05"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x06"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="Zero Cross Detect" id="cmp_zxover_ctrl_v3" name="ZCD">
+            <register-group caption="Zero Cross Detect" name="ZCD" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Invert signal from pin"
+                              mask="0x08"
+                              name="INVERT"
+                              rw="RW"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x03"
+                              name="INTMODE"
+                              rw="RW"
+                              values="ZCD_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ZCD Interrupt Flag" mask="0x01" name="CROSSIF" rw="RW"/>
+                    <bitfield caption="ZCD State"
+                              mask="0x10"
+                              name="STATE"
+                              rw="R"
+                              values="ZCD_STATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode select" name="ZCD_INTMODE">
+                <value caption="No interrupt" name="NONE" value="0x0"/>
+                <value caption="Interrupt on rising input signal"
+                       name="RISING"
+                       value="0x1"/>
+                <value caption="Interrupt on falling input signal"
+                       name="FALLING"
+                       value="0x2"/>
+                <value caption="Interrupt on both rising and falling input signal"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="ZCD State select" name="ZCD_STATE">
+                <value caption="Output is 0" name="LOW" value="0x0"/>
+                <value caption="Output is 1" name="HIGH" value="0x1"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN32MVIO">
+            <pin pad="PA3" position="1"/>
+            <pin pad="PA4" position="2"/>
+            <pin pad="PA5" position="3"/>
+            <pin pad="PA6" position="4"/>
+            <pin pad="PA7" position="5"/>
+            <pin pad="PC0" position="6"/>
+            <pin pad="PC1" position="7"/>
+            <pin pad="PC2" position="8"/>
+            <pin pad="PC3" position="9"/>
+            <pin pad="VDDIO2" position="10"/>
+            <pin pad="PD1" position="11"/>
+            <pin pad="PD2" position="12"/>
+            <pin pad="PD3" position="13"/>
+            <pin pad="PD4" position="14"/>
+            <pin pad="PD5" position="15"/>
+            <pin pad="PD6" position="16"/>
+            <pin pad="PD7" position="17"/>
+            <pin pad="AVDD" position="18"/>
+            <pin pad="AGND" position="19"/>
+            <pin pad="PF0" position="20"/>
+            <pin pad="PF1" position="21"/>
+            <pin pad="PF2" position="22"/>
+            <pin pad="PF3" position="23"/>
+            <pin pad="PF4" position="24"/>
+            <pin pad="PF5" position="25"/>
+            <pin pad="PF6" position="26"/>
+            <pin pad="PF7" position="27"/>
+            <pin pad="VDD0" position="28"/>
+            <pin pad="GND0" position="29"/>
+            <pin pad="PA0" position="30"/>
+            <pin pad="PA1" position="31"/>
+            <pin pad="PA2" position="32"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA28.xml
index 91818ede..0d72f5e5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DA28" package="SOIC28" pinout="SOIC28" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR64DA28" family="AVR8">
+    <device name="AVR64DA28" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA32.xml
index 71077995..3a2cba31 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DA32" package="QFN32" pinout="QFN32" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR64DA32" family="AVR8">
+    <device name="AVR64DA32" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA48.xml
index 9af09d19..46b3be62 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DA48" package="QFN48" pinout="QFN48" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR64DA48" family="AVR8">
+    <device name="AVR64DA48" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA64.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA64.xml
index 5b7c7425..5c673427 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DA64.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DA64" package="QFN64" pinout="QFN64" speedmax="24000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DA" name="AVR64DA64" family="AVR8">
+    <device name="AVR64DA64" family="AVR8" architecture="AVR8X" avr-family="AVR DA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB28.xml
index 8f539dbd..2083ca34 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DB28" package="SOIC28" pinout="SOIC28" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR64DB28" family="AVR8">
+    <device name="AVR64DB28" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB32.xml
index 7afb21d6..83f6d4d7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DB32" package="QFN32" pinout="QFN32" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR64DB32" family="AVR8">
+    <device name="AVR64DB32" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB48.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB48.xml
index 00e6c7be..22afbcca 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB48.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DB48" package="QFN48" pinout="QFN48" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR64DB48" family="AVR8">
+    <device name="AVR64DB48" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB64.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB64.xml
index 885e7327..7dacb886 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DB64.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DB64" package="QFN64" pinout="QFN64" speedmax="32000000" tempmax="125" tempmin="-40"
                  vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DB" name="AVR64DB64" family="AVR8">
+    <device name="AVR64DB64" family="AVR8" architecture="AVR8X" avr-family="AVR DB">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0200" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD14.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD14.xml
index 1b43ded0..5fc8b031 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD14.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD14.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DD14" package="SOIC14" pinout="SOIC14MVIO" speedmax="32000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DD" name="AVR64DD14" family="AVR8">
+    <device name="AVR64DD14" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD20.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD20.xml
index 5c01089d..0046a36a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD20.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD20.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DD20" package="QFN20" pinout="QFN20MVIO" speedmax="32000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DD" name="AVR64DD20" family="AVR8">
+    <device name="AVR64DD20" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD28.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD28.xml
index 9edbf078..487eeac3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD28.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DD28" package="SOIC28" pinout="SOIC28MVIO" speedmax="32000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DD" name="AVR64DD28" family="AVR8">
+    <device name="AVR64DD28" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD32.xml b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD32.xml
index abebc25e..142ab2c5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/D-SERIES/AVR64DD32.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AVR64DD32" package="QFN32" pinout="QFN32MVIO" speedmax="32000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR DD" name="AVR64DD32" family="AVR8">
+    <device name="AVR64DD32" family="AVR8" architecture="AVR8X" avr-family="AVR DD">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x1" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA28.xml b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA28.xml
index 75c666ab..616ec01f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA28.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA28.xml
@@ -1,971 +1,971 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR64EA28"
-               package="SOIC28"
-               pinout="SOIC28"
-               speedmax="20000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR EA" name="AVR64EA28" family="AVR8">
-         <address-spaces>
+    <variants>
+        <variant ordercode="AVR64EA28"
+                 package="SOIC28"
+                 pinout="SOIC28"
+                 speedmax="20000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR64EA28" family="AVR8" architecture="AVR8X" avr-family="AVR EA">
+        <address-spaces>
             <address-space endianness="little"
                            id="data"
                            name="data"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="0"
-                               name="IO"
-                               rw="RW"
-                               size="0x103F"
-                               start="0x00"
-                               type="io"/>
-               <memory-segment exec="0"
-                               name="LOCKBITS"
-                               pagesize="0x4"
-                               rw="RW"
-                               size="0x04"
-                               start="0x1040"
-                               type="lockbits"/>
-               <memory-segment exec="0"
-                               name="FUSES"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x10"
-                               start="0x1050"
-                               type="fuses"/>
-               <memory-segment exec="0"
-                               name="USER_SIGNATURES"
-                               pagesize="0x40"
-                               rw="RW"
-                               size="0x40"
-                               start="0x1080"
-                               type="user_signatures"/>
-               <memory-segment exec="0"
-                               name="SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x03"
-                               start="0x1100"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="PROD_SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x7D"
-                               start="0x1103"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="EEPROM"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x200"
-                               start="0x1400"
-                               type="eeprom"/>
-               <memory-segment exec="0"
-                               name="INTERNAL_SRAM"
-                               rw="RW"
-                               size="0x1800"
-                               start="0x6800"
-                               type="ram"/>
-               <memory-segment exec="0"
-                               name="MAPPED_PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x8000"
-                               start="0x8000"
-                               type="other"/>
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x4"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x40"
+                                rw="RW"
+                                size="0x40"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x200"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1800"
+                                start="0x6800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
             </address-space>
             <address-space endianness="little"
                            id="prog"
                            name="prog"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="1"
-                               name="PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x10000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_NRWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x2000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_RWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0xE000"
-                               start="0x2000"
-                               type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x10000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_NRWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x2000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_RWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0xE000"
+                                start="0x2000"
+                                type="flash"/>
             </address-space>
-         </address-spaces>
-         <peripherals>
+        </address-spaces>
+        <peripherals>
             <module id="cmp_control_v8" name="AC">
-               <instance name="AC0">
-                  <register-group address-space="data"
-                                  name="AC0"
-                                  name-in-module="AC"
-                                  offset="0x0680"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC0"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="AC1">
-                  <register-group address-space="data"
-                                  name="AC1"
-                                  name-in-module="AC"
-                                  offset="0x0688"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC1"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="AC1">
+                    <register-group address-space="data"
+                                    name="AC1"
+                                    name-in-module="AC"
+                                    offset="0x0688"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC1"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="adc_12b_diff_ctrl_avr_v2" name="ADC">
-               <instance name="ADC0">
-                  <register-group address-space="data"
-                                  name="ADC0"
-                                  name-in-module="ADC"
-                                  offset="0x0600"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD1"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD2"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="4" pad="PD4"/>
-                     <signal function="AINN" group="AINN" index="5" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="6" pad="PD6"/>
-                     <signal function="AINN" group="AINN" index="7" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="16" pad="PF0"/>
-                     <signal function="AINN" group="AINN" index="17" pad="PF1"/>
-                     <signal function="AINN" group="AINN" index="22" pad="PA2"/>
-                     <signal function="AINN" group="AINN" index="23" pad="PA3"/>
-                     <signal function="AINN" group="AINN" index="24" pad="PA4"/>
-                     <signal function="AINN" group="AINN" index="25" pad="PA5"/>
-                     <signal function="AINN" group="AINN" index="26" pad="PA6"/>
-                     <signal function="AINN" group="AINN" index="27" pad="PA7"/>
-                     <signal function="AINN" group="AINN" index="28" pad="PC0"/>
-                     <signal function="AINN" group="AINN" index="29" pad="PC1"/>
-                     <signal function="AINN" group="AINN" index="30" pad="PC2"/>
-                     <signal function="AINN" group="AINN" index="31" pad="PC3"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD0"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD1"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="5" pad="PD5"/>
-                     <signal function="AINP" group="AINP" index="6" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="7" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="16" pad="PF0"/>
-                     <signal function="AINP" group="AINP" index="17" pad="PF1"/>
-                     <signal function="AINP" group="AINP" index="22" pad="PA2"/>
-                     <signal function="AINP" group="AINP" index="23" pad="PA3"/>
-                     <signal function="AINP" group="AINP" index="24" pad="PA4"/>
-                     <signal function="AINP" group="AINP" index="25" pad="PA5"/>
-                     <signal function="AINP" group="AINP" index="26" pad="PA6"/>
-                     <signal function="AINP" group="AINP" index="27" pad="PA7"/>
-                     <signal function="AINP" group="AINP" index="28" pad="PC0"/>
-                     <signal function="AINP" group="AINP" index="29" pad="PC1"/>
-                     <signal function="AINP" group="AINP" index="30" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="31" pad="PC3"/>
-                  </signals>
-               </instance>
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD1"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD2"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="4" pad="PD4"/>
+                        <signal function="AINN" group="AINN" index="5" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="6" pad="PD6"/>
+                        <signal function="AINN" group="AINN" index="7" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="16" pad="PF0"/>
+                        <signal function="AINN" group="AINN" index="17" pad="PF1"/>
+                        <signal function="AINN" group="AINN" index="22" pad="PA2"/>
+                        <signal function="AINN" group="AINN" index="23" pad="PA3"/>
+                        <signal function="AINN" group="AINN" index="24" pad="PA4"/>
+                        <signal function="AINN" group="AINN" index="25" pad="PA5"/>
+                        <signal function="AINN" group="AINN" index="26" pad="PA6"/>
+                        <signal function="AINN" group="AINN" index="27" pad="PA7"/>
+                        <signal function="AINN" group="AINN" index="28" pad="PC0"/>
+                        <signal function="AINN" group="AINN" index="29" pad="PC1"/>
+                        <signal function="AINN" group="AINN" index="30" pad="PC2"/>
+                        <signal function="AINN" group="AINN" index="31" pad="PC3"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD0"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD1"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="5" pad="PD5"/>
+                        <signal function="AINP" group="AINP" index="6" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="7" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="16" pad="PF0"/>
+                        <signal function="AINP" group="AINP" index="17" pad="PF1"/>
+                        <signal function="AINP" group="AINP" index="22" pad="PA2"/>
+                        <signal function="AINP" group="AINP" index="23" pad="PA3"/>
+                        <signal function="AINP" group="AINP" index="24" pad="PA4"/>
+                        <signal function="AINP" group="AINP" index="25" pad="PA5"/>
+                        <signal function="AINP" group="AINP" index="26" pad="PA6"/>
+                        <signal function="AINP" group="AINP" index="27" pad="PA7"/>
+                        <signal function="AINP" group="AINP" index="28" pad="PC0"/>
+                        <signal function="AINP" group="AINP" index="29" pad="PC1"/>
+                        <signal function="AINP" group="AINP" index="30" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="bor_lvd_ctrl_avr_v2" name="BOD">
-               <instance name="BOD">
-                  <register-group address-space="data"
-                                  name="BOD"
-                                  name-in-module="BOD"
-                                  offset="0x00A0"/>
-               </instance>
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
             </module>
             <module id="cla_ccl_v1" name="CCL">
-               <instance name="CCL">
-                  <register-group address-space="data"
-                                  name="CCL"
-                                  name-in-module="CCL"
-                                  offset="0x01C0"/>
-                  <signals>
-                     <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
-                     <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
-                     <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
-                     <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
-                     <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
-                     <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
-                     <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
-                     <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
-                     <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
-                     <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
-                     <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="ALT1"
-                             group="LUT0_OUT"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="DEFAULT"
-                             group="LUT0_OUT"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT1"
-                             function="DEFAULT"
-                             group="LUT1_OUT"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="ALT1"
-                             group="LUT2_OUT"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="DEFAULT"
-                             group="LUT2_OUT"
-                             pad="PD3"/>
-                  </signals>
-               </instance>
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
+                        <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
+                        <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
+                        <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
+                        <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
+                        <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
+                        <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
+                        <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
+                        <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
+                        <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
+                        <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="ALT1"
+                                group="LUT0_OUT"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="DEFAULT"
+                                group="LUT0_OUT"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="DEFAULT"
+                                group="LUT1_OUT"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="ALT1"
+                                group="LUT2_OUT"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="DEFAULT"
+                                group="LUT2_OUT"
+                                pad="PD3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="CLKCTRL">
-               <instance name="CLKCTRL">
-                  <register-group address-space="data"
-                                  name="CLKCTRL"
-                                  name-in-module="CLKCTRL"
-                                  offset="0x0060"/>
-                  <signals>
-                     <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
-                     <signal function="OUT" group="CLKOUT" pad="PA7"/>
-                     <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
-                     <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
-                     <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
-                     <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
-                  </signals>
-               </instance>
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
+                        <signal function="OUT" group="CLKOUT" pad="PA7"/>
+                        <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
+                        <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
+                        <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
+                        <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
+                    </signals>
+                </instance>
             </module>
             <module id="cpu_avr_xt_v1" name="CPU">
-               <instance name="CPU">
-                  <register-group address-space="data"
-                                  name="CPU"
-                                  name-in-module="CPU"
-                                  offset="0x0030"/>
-                  <parameters>
-                     <param name="CORE_VERSION" value="V4S"/>
-                  </parameters>
-               </instance>
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
             </module>
             <module id="int_8bit_v3" name="CPUINT">
-               <instance name="CPUINT">
-                  <register-group address-space="data"
-                                  name="CPUINT"
-                                  name-in-module="CPUINT"
-                                  offset="0x0110"/>
-               </instance>
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
             </module>
             <module id="math_pdi_crc_v1" name="CRCSCAN">
-               <instance name="CRCSCAN">
-                  <register-group address-space="data"
-                                  name="CRCSCAN"
-                                  name-in-module="CRCSCAN"
-                                  offset="0x0120"/>
-               </instance>
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
             </module>
             <module id="dac_nbit_ctrl_avr_v6" name="DAC">
-               <instance name="DAC0">
-                  <register-group address-space="data"
-                                  name="DAC0"
-                                  name-in-module="DAC"
-                                  offset="0x06A0"/>
-                  <signals>
-                     <signal function="VOUT" group="OUT" pad="PD6"/>
-                  </signals>
-               </instance>
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="VOUT" group="OUT" pad="PD6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="EVSYS">
-               <instance name="EVSYS">
-                  <register-group address-space="data"
-                                  name="EVSYS"
-                                  name-in-module="EVSYS"
-                                  offset="0x0200"/>
-                  <signals>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="5"
-                             pad="PF7"/>
-                  </signals>
-               </instance>
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="FUSE">
-               <instance name="FUSE">
-                  <register-group address-space="data"
-                                  name="FUSE"
-                                  name-in-module="FUSE"
-                                  offset="0x1050"/>
-               </instance>
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
             </module>
             <module id="avrea" name="GPR">
-               <instance name="GPR">
-                  <register-group address-space="data"
-                                  name="GPR"
-                                  name-in-module="GPR"
-                                  offset="0x001C"/>
-               </instance>
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
             </module>
             <module id="avrea" name="LOCK">
-               <instance name="LOCK">
-                  <register-group address-space="data"
-                                  name="LOCK"
-                                  name-in-module="LOCK"
-                                  offset="0x1040"/>
-               </instance>
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
             </module>
             <module id="nvm_ctrl_avr_v3" name="NVMCTRL">
-               <instance name="NVMCTRL">
-                  <register-group address-space="data"
-                                  name="NVMCTRL"
-                                  name-in-module="NVMCTRL"
-                                  offset="0x1000"/>
-               </instance>
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3" name="PORT">
-               <instance name="PORTA">
-                  <register-group address-space="data"
-                                  name="PORTA"
-                                  name-in-module="PORT"
-                                  offset="0x0400"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTC">
-                  <register-group address-space="data"
-                                  name="PORTC"
-                                  name-in-module="PORT"
-                                  offset="0x0440"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-                  </signals>
-               </instance>
-               <instance name="PORTD">
-                  <register-group address-space="data"
-                                  name="PORTD"
-                                  name-in-module="PORT"
-                                  offset="0x0460"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTF">
-                  <register-group address-space="data"
-                                  name="PORTF"
-                                  name-in-module="PORT"
-                                  offset="0x04A0"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-                  </signals>
-               </instance>
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="PORTMUX">
-               <instance name="PORTMUX">
-                  <register-group address-space="data"
-                                  name="PORTMUX"
-                                  name-in-module="PORTMUX"
-                                  offset="0x05E0"/>
-               </instance>
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
             </module>
             <module id="rst_integration_avr_v2" name="RSTCTRL">
-               <instance name="RSTCTRL">
-                  <register-group address-space="data"
-                                  name="RSTCTRL"
-                                  name-in-module="RSTCTRL"
-                                  offset="0x0040"/>
-                  <signals>
-                     <signal function="OTHER" group="RESET" pad="PF6"/>
-                  </signals>
-               </instance>
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_rtc_avr_v2" name="RTC">
-               <instance name="RTC">
-                  <register-group address-space="data"
-                                  name="RTC"
-                                  name-in-module="RTC"
-                                  offset="0x0140"/>
-               </instance>
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
             </module>
             <module id="avrea" name="SIGROW">
-               <instance name="SIGROW">
-                  <register-group address-space="data"
-                                  name="SIGROW"
-                                  name-in-module="SIGROW"
-                                  offset="0x1100"/>
-               </instance>
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
             </module>
             <module id="clk_sleep_ctrl_avr_v1" name="SLPCTRL">
-               <instance name="SLPCTRL">
-                  <register-group address-space="data"
-                                  name="SLPCTRL"
-                                  name-in-module="SLPCTRL"
-                                  offset="0x0050"/>
-               </instance>
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
             </module>
             <module id="spi_8bit_v2" name="SPI">
-               <instance name="SPI0">
-                  <register-group address-space="data"
-                                  name="SPI0"
-                                  name-in-module="SPI"
-                                  offset="0x0940"/>
-                  <signals>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MISO"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MOSI"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SCK"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SS"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MISO"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MOSI"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SCK"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SS"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MOSI"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SS"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MOSI"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SCK"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SS"
-                             pad="PF7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MISO"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MOSI"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SCK"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SS"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MOSI"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SS"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="SYSCFG">
-               <instance name="SYSCFG">
-                  <register-group address-space="data"
-                                  name="SYSCFG"
-                                  name-in-module="SYSCFG"
-                                  offset="0x0F00"/>
-               </instance>
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
             </module>
             <module id="tmr_16b_pwm_v1" name="TCA">
-               <instance name="TCA0">
-                  <register-group address-space="data"
-                                  name="TCA0"
-                                  name-in-module="TCA"
-                                  offset="0x0A00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="1"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="3"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="0"
-                             pad="PD0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="1"
-                             pad="PD1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="2"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="3"
-                             pad="PD3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="4"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="5"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="0"
-                             pad="PF0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="1"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="1"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="3"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="4"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="5"
-                             pad="PA5"/>
-                  </signals>
-               </instance>
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="0"
+                                pad="PD0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_capture_v1" name="TCB">
-               <instance name="TCB0">
-                  <register-group address-space="data"
-                                  name="TCB0"
-                                  name-in-module="TCB"
-                                  offset="0x0B00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA2"/>
-                  </signals>
-               </instance>
-               <instance name="TCB1">
-                  <register-group address-space="data"
-                                  name="TCB1"
-                                  name-in-module="TCB"
-                                  offset="0x0B10"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="TCB2">
-                  <register-group address-space="data"
-                                  name="TCB2"
-                                  name-in-module="TCB"
-                                  offset="0x0B20"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB2"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                  </signals>
-               </instance>
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
             </module>
             <module id="i2c_8bit_avr_v3" name="TWI">
-               <instance name="TWI0">
-                  <register-group address-space="data"
-                                  name="TWI0"
-                                  name-in-module="TWI"
-                                  offset="0x0900"/>
-                  <signals>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SCL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SDA"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                  </signals>
-               </instance>
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
             </module>
             <module id="uart_autobd_v4" name="USART">
-               <instance name="USART0">
-                  <register-group address-space="data"
-                                  name="USART0"
-                                  name-in-module="USART"
-                                  offset="0x0800"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="RXD"
-                             index="1"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="TXD"
-                             index="1"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XCK"
-                             index="1"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XDIR"
-                             index="1"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="RXD"
-                             index="2"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="TXD"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="RXD"
-                             index="3"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="TXD"
-                             index="3"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XCK"
-                             index="3"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XDIR"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="RXD"
-                             index="4"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="TXD"
-                             index="4"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="XCK"
-                             index="4"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="USART1">
-                  <register-group address-space="data"
-                                  name="USART1"
-                                  name-in-module="USART"
-                                  offset="0x0820"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="RXD"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="TXD"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PC3"/>
-                  </signals>
-               </instance>
-               <instance name="USART2">
-                  <register-group address-space="data"
-                                  name="USART2"
-                                  name-in-module="USART"
-                                  offset="0x0840"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PF0"/>
-                  </signals>
-               </instance>
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="RXD"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="TXD"
+                                index="1"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XCK"
+                                index="1"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XDIR"
+                                index="1"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="RXD"
+                                index="2"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="TXD"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="RXD"
+                                index="3"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="TXD"
+                                index="3"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XCK"
+                                index="3"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XDIR"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="RXD"
+                                index="4"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="TXD"
+                                index="4"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="XCK"
+                                index="4"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART2">
+                    <register-group address-space="data"
+                                    name="USART2"
+                                    name-in-module="USART"
+                                    offset="0x0840"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PF0"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="USERROW">
-               <instance name="USERROW">
-                  <register-group address-space="data"
-                                  name="USERROW"
-                                  name-in-module="USERROW"
-                                  offset="0x1080"/>
-               </instance>
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3_vport" name="VPORT">
-               <instance name="VPORTA">
-                  <register-group address-space="data"
-                                  name="VPORTA"
-                                  name-in-module="VPORT"
-                                  offset="0x0000"/>
-               </instance>
-               <instance name="VPORTC">
-                  <register-group address-space="data"
-                                  name="VPORTC"
-                                  name-in-module="VPORT"
-                                  offset="0x0008"/>
-               </instance>
-               <instance name="VPORTD">
-                  <register-group address-space="data"
-                                  name="VPORTD"
-                                  name-in-module="VPORT"
-                                  offset="0x000C"/>
-               </instance>
-               <instance name="VPORTF">
-                  <register-group address-space="data"
-                                  name="VPORTF"
-                                  name-in-module="VPORT"
-                                  offset="0x0014"/>
-               </instance>
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
             </module>
             <module id="avrea" name="VREF">
-               <instance name="VREF">
-                  <register-group address-space="data"
-                                  name="VREF"
-                                  name-in-module="VREF"
-                                  offset="0x00B0"/>
-                  <signals>
-                     <signal function="VREF" group="VREFA" pad="PD7"/>
-                  </signals>
-               </instance>
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                    <signals>
+                        <signal function="VREF" group="VREFA" pad="PD7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="wdt_windowed_v2" name="WDT">
-               <instance name="WDT">
-                  <register-group address-space="data"
-                                  name="WDT"
-                                  name-in-module="WDT"
-                                  offset="0x0100"/>
-               </instance>
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
             </module>
-         </peripherals>
-         <interrupts>
+        </peripherals>
+        <interrupts>
             <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
             <interrupt index="2" module-instance="BOD" name="VLM"/>
             <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
@@ -1008,5468 +1008,5468 @@
             <interrupt index="34" module-instance="USART2" name="RXC"/>
             <interrupt index="35" module-instance="USART2" name="DRE"/>
             <interrupt index="36" module-instance="USART2" name="TXC"/>
-         </interrupts>
-         <interfaces>
+        </interrupts>
+        <interfaces>
             <interface name="UPDI" type="updi"/>
-         </interfaces>
-         <property-groups>
+        </interfaces>
+        <property-groups>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x96"/>
-               <property name="SIGNATURE2" value="0x20"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x96"/>
+                <property name="SIGNATURE2" value="0x20"/>
             </property-group>
-         </property-groups>
-      </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window selection mode"
-                         mask="0x03"
-                         name="WINSEL"
-                         rw="RW"
-                         values="AC_WINSEL"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
-               <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="WINDOW"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_WINDOW_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-               <bitfield caption="Analog Comparator Window State"
-                         mask="0xC0"
-                         name="WINSTATE"
-                         rw="R"
-                         values="AC_WINSTATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Fastest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-         </value-group>
-         <value-group caption="Window selection mode" name="AC_WINSEL">
-            <value caption="Window function disabled" name="DISABLED" value="0x0"/>
-            <value caption="Select ACn+1 as upper limit in window compare"
-                   name="UPSEL1"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
-            <value caption="Window interrupt when input above both references"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="Window interrupt when input betweeen references"
-                   name="INSIDE"
-                   value="0x1"/>
-            <value caption="Window interrupt when input below both references"
-                   name="BELOW"
-                   value="0x2"/>
-            <value caption="Window interrupt when input outside reference"
-                   name="OUTSIDE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
-            <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
-            <value caption="Above window" name="ABOVE" value="0x0"/>
-            <value caption="Inside window" name="INSIDE" value="0x1"/>
-            <value caption="Below window" name="BELOW" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_avr_v2"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler Value"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="ADC_REFSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-               <bitfield caption="Window Mode Source"
-                         mask="0x08"
-                         name="WINSRC"
-                         rw="RW"
-                         values="ADC_WINSRC"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Enable"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Enable"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Enable"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Enable"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Flag"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Flag"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Flag"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Flag"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Flag"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Flag"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Status register"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
-            </register>
-            <register caption="Control F"
-                      initval="0x00"
-                      name="CTRLF"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample numbers"
-                         mask="0x0F"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-               <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
-               <bitfield caption="Sign Chopping"
-                         mask="0x40"
-                         name="CHOPPING"
-                         rw="RW"
-                         values="ADC_CHOPPING"/>
-            </register>
-            <register caption="Command register"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start command"
-                         mask="0x07"
-                         name="START"
-                         rw="RW"
-                         values="ADC_START"/>
-               <bitfield caption="Mode"
-                         mask="0x70"
-                         name="MODE"
-                         rw="RW"
-                         values="ADC_MODE"/>
-               <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
-            </register>
-            <register caption="PGA Control"
-                      initval="0x00"
-                      name="PGACTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
-               <bitfield caption="PGA BIAS Select"
-                         mask="0x18"
-                         name="PGABIASSEL"
-                         rw="RW"
-                         values="ADC_PGABIASSEL"/>
-               <bitfield caption="Gain"
-                         mask="0xE0"
-                         name="GAIN"
-                         rw="RW"
-                         values="ADC_GAIN"/>
-            </register>
-            <register caption="Positive Input Multiplexer"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Negative Input Multiplexer"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Result"
-                      initval="0x00000000"
-                      name="RESULT"
-                      offset="0x10"
-                      rw="R"
-                      size="4"/>
-            <register caption="Sample"
-                      initval="0x0000"
-                      name="SAMPLE"
-                      offset="0x14"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temporary Data 0"
-                      initval="0x00"
-                      name="TEMP0"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 1"
-                      initval="0x00"
-                      name="TEMP1"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 2"
-                      initval="0x00"
-                      name="TEMP2"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Window Low Threshold"
-                      initval="0x0000"
-                      name="WINLT"
-                      offset="0x1C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window High Threshold"
-                      initval="0x0000"
-                      name="WINHT"
-                      offset="0x1E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Mode select" name="ADC_MODE">
-            <value caption="Single Conversion with 8-bit resolution"
-                   name="SINGLE_8BIT"
-                   value="0x00"/>
-            <value caption="Single Conversion with 12-bit resolution"
-                   name="SINGLE_12BIT"
-                   value="0x01"/>
-            <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
-                   name="SERIES"
-                   value="0x02"/>
-            <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
-                   name="SERIES_SCALING"
-                   value="0x03"/>
-            <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST"
-                   value="0x04"/>
-            <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST_SCALING"
-                   value="0x05"/>
-         </value-group>
-         <value-group caption="Start command select" name="ADC_START">
-            <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
-            <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
-                   name="IMMEDIATE"
-                   value="0x01"/>
-            <value caption="Start when MUXPOS register is written"
-                   name="MUXPOS_WRITE"
-                   value="0x02"/>
-            <value caption="Start when MUXNEG register is written"
-                   name="MUXNEG_WRITE"
-                   value="0x03"/>
-            <value caption="Start when an event is received"
-                   name="EVENT_TRIGGER"
-                   value="0x04"/>
-         </value-group>
-         <value-group caption="Prescaler Value select" name="ADC_PRESC">
-            <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
-            <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
-            <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
-            <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
-            <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
-            <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
-            <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
-            <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
-            <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
-            <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
-            <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
-            <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
-            <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
-            <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
-            <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
-         </value-group>
-         <value-group caption="Reference select" name="ADC_REFSEL">
-            <value caption="VDD" name="VDD" value="0x00"/>
-            <value caption="External Reference" name="VREFA" value="0x02"/>
-            <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
-            <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
-            <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
-            <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Window Mode Source select" name="ADC_WINSRC">
-            <value caption="Result register used as Window Comparator Source"
-                   name="RESULT"
-                   value="0x0"/>
-            <value caption="Sample register used as Window Comparator Source"
-                   name="SAMPLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
-            <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
-            <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x0"/>
-            <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
-            <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
-            <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
-            <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
-            <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
-            <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
-            <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
-            <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
-            <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
-            <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-            <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
-            <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
-         </value-group>
-         <value-group caption="VIA select" name="ADC_VIA">
-            <value caption="Inputs connected directly to ADC"
-                   name="DIRECT"
-                   value="0x0"/>
-            <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
-            <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-         </value-group>
-         <value-group caption="Gain select" name="ADC_GAIN">
-            <value caption="1x gain" name="1X" value="0x0"/>
-            <value caption="2x gain" name="2X" value="0x1"/>
-            <value caption="4x gain" name="4X" value="0x2"/>
-            <value caption="8x gain" name="8X" value="0x3"/>
-            <value caption="16x gain" name="16X" value="0x4"/>
-         </value-group>
-         <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
-            <value caption="100% BIAS current." name="100PCT" value="0x0"/>
-            <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
-                   name="75PCT"
-                   value="0x1"/>
-            <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
-                   name="50PCT"
-                   value="0x2"/>
-            <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
-                   name="25PCT"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="INSEL2 selection" name="IN2" value="0x1"/>
-            <value caption="Internal High Frequency oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="Internal 32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC0 output input source" name="AC0" value="0x6"/>
-            <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrea" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x11"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
-               <bitfield caption="CFD Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
-               <bitfield caption="Interrupt Type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="R"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="R"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="R"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="R"/>
-               <bitfield caption="External Clock status / XOSCHF status"
-                         mask="0x10"
-                         name="EXTS"
-                         rw="R"/>
-            </register>
-            <register caption="MCLK Timebase"
-                      initval="0x00"
-                      name="MCLKTIMEBASE"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Automatic Oscillator Tune"
-                         mask="0x03"
-                         name="AUTOTUNE"
-                         rw="RW"
-                         values="CLKCTRL_AUTOTUNE"/>
-               <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      initval="0x00"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSCHF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Start-Up Time"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="Divide by 2" name="DIV2" value="0x00"/>
-            <value caption="Divide by 4" name="DIV4" value="0x01"/>
-            <value caption="Divide by 8" name="DIV8" value="0x02"/>
-            <value caption="Divide by 16" name="DIV16" value="0x03"/>
-            <value caption="Divide by 32" name="DIV32" value="0x04"/>
-            <value caption="Divide by 64" name="DIV64" value="0x05"/>
-            <value caption="Divide by 6" name="DIV6" value="0x08"/>
-            <value caption="Divide by 10" name="DIV10" value="0x09"/>
-            <value caption="Divide by 12" name="DIV12" value="0x0A"/>
-            <value caption="Divide by 24" name="DIV24" value="0x0B"/>
-            <value caption="Divide by 48" name="DIV48" value="0x0C"/>
-         </value-group>
-         <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="High Frequency Crystal Oscillator"
-                   name="XOSCHF"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular interrupt" name="INT" value="0x0"/>
-            <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Tune against 32.768 kHz Crystal Oscillator"
-                   name="XOSC32K"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
-            <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
-            <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
-         </value-group>
-         <value-group caption="Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
-            <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_avr_v6"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Range"
-                         mask="0x30"
-                         name="OUTRANGE"
-                         rw="RW"
-                         values="DAC_OUTRANGE"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
-            <value caption="Output buffer automatically choose best range"
-                   name="AUTO"
-                   value="0x0"/>
-            <value caption="Output buffer configured to low range"
-                   name="LOW"
-                   value="0x2"/>
-            <value caption="Output buffer configured to high range"
-                   name="HIGH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Event System" id="avrea" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART2"
-                      initval="0x00"
-                      name="USERUSART2IRDA"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event A"
-                      initval="0x00"
-                      name="USERTCA1CNTA"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event B"
-                      initval="0x00"
-                      name="USERTCA1CNTB"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x39"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event A"
-                      initval="0x00"
-                      name="USERTCB3CAPT"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event B"
-                      initval="0x00"
-                      name="USERTCB3COUNT"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer Event 0"
-                   name="RTC_PITEV0"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer Event 1"
-                   name="RTC_PITEV1"
-                   value="0x9"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
-            <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
-            <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
-            <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
-            <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
-            <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
-            <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
-            <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
-            <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
-            <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
-            <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter A1 overflow / low byte timer underflow"
-                   name="TCA1_OVF_LUNF"
-                   value="0x88"/>
-            <value caption="Timer/Counter A1 high byte timer underflow"
-                   name="TCA1_HUNF"
-                   value="0x89"/>
-            <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
-                   name="TCA1_CMP0_LCMP0"
-                   value="0x8C"/>
-            <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
-                   name="TCA1_CMP1_LCMP1"
-                   value="0x8D"/>
-            <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
-                   name="TCA1_CMP2_LCMP2"
-                   value="0x8E"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
-            <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrea" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="High-frequency Oscillator Frequency"
-                         mask="0x08"
-                         name="OSCHFFRQ"
-                         rw="RW"
-                         values="FUSE_OSCHFFRQ"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save"
-                         mask="0x01"
-                         name="EESAVE"
-                         rw="RW"
-                         values="FUSE_EESAVE"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x07"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="High-frequency Oscillator Frequency select"
-                      name="FUSE_OSCHFFRQ">
-            <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
-            <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
-            <value caption="EEPROM content is erased during chip erase"
-                   name="DISABLE"
-                   value="0x0"/>
-            <value caption="EEPROM content is preserved during chip erase"
-                   name="ENABLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="No External Reset" name="NONE" value="0x0"/>
-            <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
-            <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrea" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrea" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v3"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
-               <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Data"
-                      initval="0x0000"
-                      name="DATA"
-                      offset="0x08"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Address"
-                      initval="0x00000000"
-                      name="ADDR"
-                      offset="0x0C"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NOCMD" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Page Write" name="FLPW" value="0x04"/>
-            <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
-            <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
-            <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
-            <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
-            <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
-            <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
-            <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
-            <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
-            <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
-            <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
-            <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command (UPDI only)"
-                   name="EECHER"
-                   value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Attempt to program write protected area"
-                   name="WRITEPROTECT"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="CMDCOLLISION"
-                   value="0x3"/>
-            <value caption="Address cannot be written with selected command"
-                   name="WRONGSECTION"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      initval="0x00"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      initval="0x00"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      initval="0x00"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      initval="0x00"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      initval="0x00"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      initval="0x00"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Event Generation Control"
-                      initval="0x00"
-                      name="EVGENCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generator 0 Select"
-                         mask="0x07"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="PORT_EVGEN0SEL"/>
-               <bitfield caption="Event Generator 1 Select"
-                         mask="0x70"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="PORT_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Input Level Select" name="PORT_INLVL">
-            <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
-            <value caption="TTL Input level" name="TTL" value="0x1"/>
-         </value-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Routing"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Routing"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="USART route B"
-                      initval="0x00"
-                      name="USARTROUTEB"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART2 Routing"
-                         mask="0x30"
-                         name="USART2"
-                         rw="RW"
-                         values="PORTMUX_USART2"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-               <bitfield caption="TCA1 Signals"
-                         mask="0x38"
-                         name="TCA1"
-                         rw="RW"
-                         values="PORTMUX_TCA1"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-               <bitfield caption="TCB3 Output"
-                         mask="0x08"
-                         name="TCB3"
-                         rw="RW"
-                         values="PORTMUX_TCB3"/>
-            </register>
-            <register caption="AC route A"
-                      initval="0x00"
-                      name="ACROUTEA"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator 0 Output"
-                         mask="0x01"
-                         name="AC0"
-                         rw="RW"
-                         values="PORTMUX_AC0"/>
-               <bitfield caption="Analog Comparator 1 Output"
-                         mask="0x02"
-                         name="AC1"
-                         rw="RW"
-                         values="PORTMUX_AC1"/>
-            </register>
-         </register-group>
-         <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-         </value-group>
-         <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
-            <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
-            <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="PA2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="PA3" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="PC0" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
-            <value caption="PC1" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
-            <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
-            <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
-            <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
-            <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
-            <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
-            <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
-            <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller"
-              id="rst_integration_avr_v2"
-              name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="PIT Event Generation Control A"
-                      initval="0x00"
-                      name="PITEVGENCTRLA"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generation 0 Select"
-                         mask="0x0F"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="RTC_EVGEN0SEL"/>
-               <bitfield caption="Event Generation 1 Select"
-                         mask="0xF0"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="RTC_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
-            <value caption="Internal 32.768 kHz Oscillator Divided by 32"
-                   name="OSC1K"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-         <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-         <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrea" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2"/>
-            <register caption="Serial Number Byte 0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 6"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 7"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 8"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 9"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 10"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 11"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 12"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 13"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 14"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 15"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v1"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
-               <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
-            </register>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
-            </register>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Enable"
-                         mask="0x01"
-                         name="FMEN"
-                         rw="RW"
-                         values="TWI_FMEN"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
-            <value caption="SCL duty cycle operating according to Sm specification"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="SCL duty cycle operating according to Fm specification"
-                   name="ON"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrea" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x40">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 32"
-                      name="USERROW32"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 33"
-                      name="USERROW33"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 34"
-                      name="USERROW34"
-                      offset="0x22"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 35"
-                      name="USERROW35"
-                      offset="0x23"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 36"
-                      name="USERROW36"
-                      offset="0x24"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 37"
-                      name="USERROW37"
-                      offset="0x25"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 38"
-                      name="USERROW38"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 39"
-                      name="USERROW39"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 40"
-                      name="USERROW40"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 41"
-                      name="USERROW41"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 42"
-                      name="USERROW42"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 43"
-                      name="USERROW43"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 44"
-                      name="USERROW44"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 45"
-                      name="USERROW45"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 46"
-                      name="USERROW46"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 47"
-                      name="USERROW47"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 48"
-                      name="USERROW48"
-                      offset="0x30"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 49"
-                      name="USERROW49"
-                      offset="0x31"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 50"
-                      name="USERROW50"
-                      offset="0x32"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 51"
-                      name="USERROW51"
-                      offset="0x33"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 52"
-                      name="USERROW52"
-                      offset="0x34"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 53"
-                      name="USERROW53"
-                      offset="0x35"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 54"
-                      name="USERROW54"
-                      offset="0x36"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 55"
-                      name="USERROW55"
-                      offset="0x37"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 56"
-                      name="USERROW56"
-                      offset="0x38"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 57"
-                      name="USERROW57"
-                      offset="0x39"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 58"
-                      name="USERROW58"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 59"
-                      name="USERROW59"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 60"
-                      name="USERROW60"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 61"
-                      name="USERROW61"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 62"
-                      name="USERROW62"
-                      offset="0x3E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 63"
-                      name="USERROW63"
-                      offset="0x3F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrea" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
-            <value caption="VDD as reference" name="VDD" value="0x5"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="SOIC28">
-         <pin pad="PA7" position="1"/>
-         <pin pad="PC0" position="2"/>
-         <pin pad="PC1" position="3"/>
-         <pin pad="PC2" position="4"/>
-         <pin pad="PC3" position="5"/>
-         <pin pad="PD0" position="6"/>
-         <pin pad="PD1" position="7"/>
-         <pin pad="PD2" position="8"/>
-         <pin pad="PD3" position="9"/>
-         <pin pad="PD4" position="10"/>
-         <pin pad="PD5" position="11"/>
-         <pin pad="PD6" position="12"/>
-         <pin pad="PD7" position="13"/>
-         <pin pad="VDD" position="14"/>
-         <pin pad="GND" position="15"/>
-         <pin pad="PF0" position="16"/>
-         <pin pad="PF1" position="17"/>
-         <pin pad="PF6" position="18"/>
-         <pin pad="PF7" position="19"/>
-         <pin pad="VDD1" position="20"/>
-         <pin pad="GND1" position="21"/>
-         <pin pad="PA0" position="22"/>
-         <pin pad="PA1" position="23"/>
-         <pin pad="PA2" position="24"/>
-         <pin pad="PA3" position="25"/>
-         <pin pad="PA4" position="26"/>
-         <pin pad="PA5" position="27"/>
-         <pin pad="PA6" position="28"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window selection mode"
+                              mask="0x03"
+                              name="WINSEL"
+                              rw="RW"
+                              values="AC_WINSEL"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
+                    <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="WINDOW"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_WINDOW_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                    <bitfield caption="Analog Comparator Window State"
+                              mask="0xC0"
+                              name="WINSTATE"
+                              rw="R"
+                              values="AC_WINSTATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Fastest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+            </value-group>
+            <value-group caption="Window selection mode" name="AC_WINSEL">
+                <value caption="Window function disabled" name="DISABLED" value="0x0"/>
+                <value caption="Select ACn+1 as upper limit in window compare"
+                       name="UPSEL1"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
+                <value caption="Window interrupt when input above both references"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="Window interrupt when input betweeen references"
+                       name="INSIDE"
+                       value="0x1"/>
+                <value caption="Window interrupt when input below both references"
+                       name="BELOW"
+                       value="0x2"/>
+                <value caption="Window interrupt when input outside reference"
+                       name="OUTSIDE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
+                <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
+                <value caption="Above window" name="ABOVE" value="0x0"/>
+                <value caption="Inside window" name="INSIDE" value="0x1"/>
+                <value caption="Below window" name="BELOW" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_avr_v2"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler Value"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="ADC_REFSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                    <bitfield caption="Window Mode Source"
+                              mask="0x08"
+                              name="WINSRC"
+                              rw="RW"
+                              values="ADC_WINSRC"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Enable"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Enable"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Enable"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Enable"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Flag"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Flag"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Flag"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Flag"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Flag"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Flag"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Status register"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
+                </register>
+                <register caption="Control F"
+                          initval="0x00"
+                          name="CTRLF"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample numbers"
+                              mask="0x0F"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                    <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Sign Chopping"
+                              mask="0x40"
+                              name="CHOPPING"
+                              rw="RW"
+                              values="ADC_CHOPPING"/>
+                </register>
+                <register caption="Command register"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start command"
+                              mask="0x07"
+                              name="START"
+                              rw="RW"
+                              values="ADC_START"/>
+                    <bitfield caption="Mode"
+                              mask="0x70"
+                              name="MODE"
+                              rw="RW"
+                              values="ADC_MODE"/>
+                    <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
+                </register>
+                <register caption="PGA Control"
+                          initval="0x00"
+                          name="PGACTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
+                    <bitfield caption="PGA BIAS Select"
+                              mask="0x18"
+                              name="PGABIASSEL"
+                              rw="RW"
+                              values="ADC_PGABIASSEL"/>
+                    <bitfield caption="Gain"
+                              mask="0xE0"
+                              name="GAIN"
+                              rw="RW"
+                              values="ADC_GAIN"/>
+                </register>
+                <register caption="Positive Input Multiplexer"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Negative Input Multiplexer"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Result"
+                          initval="0x00000000"
+                          name="RESULT"
+                          offset="0x10"
+                          rw="R"
+                          size="4"/>
+                <register caption="Sample"
+                          initval="0x0000"
+                          name="SAMPLE"
+                          offset="0x14"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temporary Data 0"
+                          initval="0x00"
+                          name="TEMP0"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 1"
+                          initval="0x00"
+                          name="TEMP1"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 2"
+                          initval="0x00"
+                          name="TEMP2"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Window Low Threshold"
+                          initval="0x0000"
+                          name="WINLT"
+                          offset="0x1C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window High Threshold"
+                          initval="0x0000"
+                          name="WINHT"
+                          offset="0x1E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Mode select" name="ADC_MODE">
+                <value caption="Single Conversion with 8-bit resolution"
+                       name="SINGLE_8BIT"
+                       value="0x00"/>
+                <value caption="Single Conversion with 12-bit resolution"
+                       name="SINGLE_12BIT"
+                       value="0x01"/>
+                <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
+                       name="SERIES"
+                       value="0x02"/>
+                <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
+                       name="SERIES_SCALING"
+                       value="0x03"/>
+                <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST"
+                       value="0x04"/>
+                <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST_SCALING"
+                       value="0x05"/>
+            </value-group>
+            <value-group caption="Start command select" name="ADC_START">
+                <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
+                <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
+                       name="IMMEDIATE"
+                       value="0x01"/>
+                <value caption="Start when MUXPOS register is written"
+                       name="MUXPOS_WRITE"
+                       value="0x02"/>
+                <value caption="Start when MUXNEG register is written"
+                       name="MUXNEG_WRITE"
+                       value="0x03"/>
+                <value caption="Start when an event is received"
+                       name="EVENT_TRIGGER"
+                       value="0x04"/>
+            </value-group>
+            <value-group caption="Prescaler Value select" name="ADC_PRESC">
+                <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
+                <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
+                <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
+                <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
+                <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
+                <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
+                <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
+                <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
+                <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
+                <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
+                <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
+                <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
+                <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
+                <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
+                <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
+            </value-group>
+            <value-group caption="Reference select" name="ADC_REFSEL">
+                <value caption="VDD" name="VDD" value="0x00"/>
+                <value caption="External Reference" name="VREFA" value="0x02"/>
+                <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
+                <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
+                <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
+                <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Window Mode Source select" name="ADC_WINSRC">
+                <value caption="Result register used as Window Comparator Source"
+                       name="RESULT"
+                       value="0x0"/>
+                <value caption="Sample register used as Window Comparator Source"
+                       name="SAMPLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
+                <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
+                <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x0"/>
+                <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
+                <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
+                <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
+                <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
+                <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
+                <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
+                <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
+                <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
+                <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
+                <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+                <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
+                <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
+            </value-group>
+            <value-group caption="VIA select" name="ADC_VIA">
+                <value caption="Inputs connected directly to ADC"
+                       name="DIRECT"
+                       value="0x0"/>
+                <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
+                <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+            </value-group>
+            <value-group caption="Gain select" name="ADC_GAIN">
+                <value caption="1x gain" name="1X" value="0x0"/>
+                <value caption="2x gain" name="2X" value="0x1"/>
+                <value caption="4x gain" name="4X" value="0x2"/>
+                <value caption="8x gain" name="8X" value="0x3"/>
+                <value caption="16x gain" name="16X" value="0x4"/>
+            </value-group>
+            <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
+                <value caption="100% BIAS current." name="100PCT" value="0x0"/>
+                <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
+                       name="75PCT"
+                       value="0x1"/>
+                <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
+                       name="50PCT"
+                       value="0x2"/>
+                <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
+                       name="25PCT"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="INSEL2 selection" name="IN2" value="0x1"/>
+                <value caption="Internal High Frequency oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="Internal 32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC0 output input source" name="AC0" value="0x6"/>
+                <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrea" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x11"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
+                    <bitfield caption="CFD Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
+                    <bitfield caption="Interrupt Type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="R"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="R"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="R"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="R"/>
+                    <bitfield caption="External Clock status / XOSCHF status"
+                              mask="0x10"
+                              name="EXTS"
+                              rw="R"/>
+                </register>
+                <register caption="MCLK Timebase"
+                          initval="0x00"
+                          name="MCLKTIMEBASE"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Automatic Oscillator Tune"
+                              mask="0x03"
+                              name="AUTOTUNE"
+                              rw="RW"
+                              values="CLKCTRL_AUTOTUNE"/>
+                    <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          initval="0x00"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSCHF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Start-Up Time"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="Divide by 2" name="DIV2" value="0x00"/>
+                <value caption="Divide by 4" name="DIV4" value="0x01"/>
+                <value caption="Divide by 8" name="DIV8" value="0x02"/>
+                <value caption="Divide by 16" name="DIV16" value="0x03"/>
+                <value caption="Divide by 32" name="DIV32" value="0x04"/>
+                <value caption="Divide by 64" name="DIV64" value="0x05"/>
+                <value caption="Divide by 6" name="DIV6" value="0x08"/>
+                <value caption="Divide by 10" name="DIV10" value="0x09"/>
+                <value caption="Divide by 12" name="DIV12" value="0x0A"/>
+                <value caption="Divide by 24" name="DIV24" value="0x0B"/>
+                <value caption="Divide by 48" name="DIV48" value="0x0C"/>
+            </value-group>
+            <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="High Frequency Crystal Oscillator"
+                       name="XOSCHF"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular interrupt" name="INT" value="0x0"/>
+                <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Tune against 32.768 kHz Crystal Oscillator"
+                       name="XOSC32K"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
+                <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
+                <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
+            </value-group>
+            <value-group caption="Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
+                <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_avr_v6"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Range"
+                              mask="0x30"
+                              name="OUTRANGE"
+                              rw="RW"
+                              values="DAC_OUTRANGE"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
+                <value caption="Output buffer automatically choose best range"
+                       name="AUTO"
+                       value="0x0"/>
+                <value caption="Output buffer configured to low range"
+                       name="LOW"
+                       value="0x2"/>
+                <value caption="Output buffer configured to high range"
+                       name="HIGH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Event System" id="avrea" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART2"
+                          initval="0x00"
+                          name="USERUSART2IRDA"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event A"
+                          initval="0x00"
+                          name="USERTCA1CNTA"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event B"
+                          initval="0x00"
+                          name="USERTCA1CNTB"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x39"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event A"
+                          initval="0x00"
+                          name="USERTCB3CAPT"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event B"
+                          initval="0x00"
+                          name="USERTCB3COUNT"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer Event 0"
+                       name="RTC_PITEV0"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer Event 1"
+                       name="RTC_PITEV1"
+                       value="0x9"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
+                <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
+                <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
+                <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
+                <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
+                <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
+                <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
+                <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
+                <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
+                <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
+                <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter A1 overflow / low byte timer underflow"
+                       name="TCA1_OVF_LUNF"
+                       value="0x88"/>
+                <value caption="Timer/Counter A1 high byte timer underflow"
+                       name="TCA1_HUNF"
+                       value="0x89"/>
+                <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
+                       name="TCA1_CMP0_LCMP0"
+                       value="0x8C"/>
+                <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
+                       name="TCA1_CMP1_LCMP1"
+                       value="0x8D"/>
+                <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
+                       name="TCA1_CMP2_LCMP2"
+                       value="0x8E"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
+                <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrea" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="High-frequency Oscillator Frequency"
+                              mask="0x08"
+                              name="OSCHFFRQ"
+                              rw="RW"
+                              values="FUSE_OSCHFFRQ"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save"
+                              mask="0x01"
+                              name="EESAVE"
+                              rw="RW"
+                              values="FUSE_EESAVE"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x07"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="High-frequency Oscillator Frequency select"
+                         name="FUSE_OSCHFFRQ">
+                <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
+                <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
+                <value caption="EEPROM content is erased during chip erase"
+                       name="DISABLE"
+                       value="0x0"/>
+                <value caption="EEPROM content is preserved during chip erase"
+                       name="ENABLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="No External Reset" name="NONE" value="0x0"/>
+                <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
+                <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrea" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrea" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v3"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Data"
+                          initval="0x0000"
+                          name="DATA"
+                          offset="0x08"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Address"
+                          initval="0x00000000"
+                          name="ADDR"
+                          offset="0x0C"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NOCMD" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Page Write" name="FLPW" value="0x04"/>
+                <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
+                <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
+                <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
+                <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
+                <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
+                <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
+                <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
+                <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
+                <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
+                <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
+                <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command (UPDI only)"
+                       name="EECHER"
+                       value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Attempt to program write protected area"
+                       name="WRITEPROTECT"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="CMDCOLLISION"
+                       value="0x3"/>
+                <value caption="Address cannot be written with selected command"
+                       name="WRONGSECTION"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          initval="0x00"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          initval="0x00"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          initval="0x00"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          initval="0x00"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          initval="0x00"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          initval="0x00"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Event Generation Control"
+                          initval="0x00"
+                          name="EVGENCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generator 0 Select"
+                              mask="0x07"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="PORT_EVGEN0SEL"/>
+                    <bitfield caption="Event Generator 1 Select"
+                              mask="0x70"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="PORT_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Input Level Select" name="PORT_INLVL">
+                <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
+                <value caption="TTL Input level" name="TTL" value="0x1"/>
+            </value-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Routing"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Routing"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="USART route B"
+                          initval="0x00"
+                          name="USARTROUTEB"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART2 Routing"
+                              mask="0x30"
+                              name="USART2"
+                              rw="RW"
+                              values="PORTMUX_USART2"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                    <bitfield caption="TCA1 Signals"
+                              mask="0x38"
+                              name="TCA1"
+                              rw="RW"
+                              values="PORTMUX_TCA1"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                    <bitfield caption="TCB3 Output"
+                              mask="0x08"
+                              name="TCB3"
+                              rw="RW"
+                              values="PORTMUX_TCB3"/>
+                </register>
+                <register caption="AC route A"
+                          initval="0x00"
+                          name="ACROUTEA"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator 0 Output"
+                              mask="0x01"
+                              name="AC0"
+                              rw="RW"
+                              values="PORTMUX_AC0"/>
+                    <bitfield caption="Analog Comparator 1 Output"
+                              mask="0x02"
+                              name="AC1"
+                              rw="RW"
+                              values="PORTMUX_AC1"/>
+                </register>
+            </register-group>
+            <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+            </value-group>
+            <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
+                <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
+                <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="PA2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="PA3" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="PC0" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
+                <value caption="PC1" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
+                <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
+                <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
+                <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
+                <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
+                <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
+                <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
+                <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller"
+                id="rst_integration_avr_v2"
+                name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="PIT Event Generation Control A"
+                          initval="0x00"
+                          name="PITEVGENCTRLA"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generation 0 Select"
+                              mask="0x0F"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="RTC_EVGEN0SEL"/>
+                    <bitfield caption="Event Generation 1 Select"
+                              mask="0xF0"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="RTC_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
+                <value caption="Internal 32.768 kHz Oscillator Divided by 32"
+                       name="OSC1K"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+            <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+            <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrea" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2"/>
+                <register caption="Serial Number Byte 0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 6"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 7"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 8"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 9"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 10"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 11"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 12"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 13"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 14"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 15"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v1"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
+                    <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
+                </register>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
+                </register>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Enable"
+                              mask="0x01"
+                              name="FMEN"
+                              rw="RW"
+                              values="TWI_FMEN"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
+                <value caption="SCL duty cycle operating according to Sm specification"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="SCL duty cycle operating according to Fm specification"
+                       name="ON"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrea" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x40">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 32"
+                          name="USERROW32"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 33"
+                          name="USERROW33"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 34"
+                          name="USERROW34"
+                          offset="0x22"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 35"
+                          name="USERROW35"
+                          offset="0x23"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 36"
+                          name="USERROW36"
+                          offset="0x24"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 37"
+                          name="USERROW37"
+                          offset="0x25"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 38"
+                          name="USERROW38"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 39"
+                          name="USERROW39"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 40"
+                          name="USERROW40"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 41"
+                          name="USERROW41"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 42"
+                          name="USERROW42"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 43"
+                          name="USERROW43"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 44"
+                          name="USERROW44"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 45"
+                          name="USERROW45"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 46"
+                          name="USERROW46"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 47"
+                          name="USERROW47"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 48"
+                          name="USERROW48"
+                          offset="0x30"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 49"
+                          name="USERROW49"
+                          offset="0x31"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 50"
+                          name="USERROW50"
+                          offset="0x32"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 51"
+                          name="USERROW51"
+                          offset="0x33"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 52"
+                          name="USERROW52"
+                          offset="0x34"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 53"
+                          name="USERROW53"
+                          offset="0x35"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 54"
+                          name="USERROW54"
+                          offset="0x36"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 55"
+                          name="USERROW55"
+                          offset="0x37"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 56"
+                          name="USERROW56"
+                          offset="0x38"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 57"
+                          name="USERROW57"
+                          offset="0x39"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 58"
+                          name="USERROW58"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 59"
+                          name="USERROW59"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 60"
+                          name="USERROW60"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 61"
+                          name="USERROW61"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 62"
+                          name="USERROW62"
+                          offset="0x3E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 63"
+                          name="USERROW63"
+                          offset="0x3F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrea" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
+                <value caption="VDD as reference" name="VDD" value="0x5"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="SOIC28">
+            <pin pad="PA7" position="1"/>
+            <pin pad="PC0" position="2"/>
+            <pin pad="PC1" position="3"/>
+            <pin pad="PC2" position="4"/>
+            <pin pad="PC3" position="5"/>
+            <pin pad="PD0" position="6"/>
+            <pin pad="PD1" position="7"/>
+            <pin pad="PD2" position="8"/>
+            <pin pad="PD3" position="9"/>
+            <pin pad="PD4" position="10"/>
+            <pin pad="PD5" position="11"/>
+            <pin pad="PD6" position="12"/>
+            <pin pad="PD7" position="13"/>
+            <pin pad="VDD" position="14"/>
+            <pin pad="GND" position="15"/>
+            <pin pad="PF0" position="16"/>
+            <pin pad="PF1" position="17"/>
+            <pin pad="PF6" position="18"/>
+            <pin pad="PF7" position="19"/>
+            <pin pad="VDD1" position="20"/>
+            <pin pad="GND1" position="21"/>
+            <pin pad="PA0" position="22"/>
+            <pin pad="PA1" position="23"/>
+            <pin pad="PA2" position="24"/>
+            <pin pad="PA3" position="25"/>
+            <pin pad="PA4" position="26"/>
+            <pin pad="PA5" position="27"/>
+            <pin pad="PA6" position="28"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA32.xml
index fa46fcd9..72798766 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA32.xml
@@ -1,1039 +1,1039 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR64EA32"
-               package="VQFN32"
-               pinout="QFN32"
-               speedmax="20000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR EA" name="AVR64EA32" family="AVR8">
-         <address-spaces>
+    <variants>
+        <variant ordercode="AVR64EA32"
+                 package="VQFN32"
+                 pinout="QFN32"
+                 speedmax="20000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR64EA32" family="AVR8" architecture="AVR8X" avr-family="AVR EA">
+        <address-spaces>
             <address-space endianness="little"
                            id="data"
                            name="data"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="0"
-                               name="IO"
-                               rw="RW"
-                               size="0x103F"
-                               start="0x00"
-                               type="io"/>
-               <memory-segment exec="0"
-                               name="LOCKBITS"
-                               pagesize="0x4"
-                               rw="RW"
-                               size="0x04"
-                               start="0x1040"
-                               type="lockbits"/>
-               <memory-segment exec="0"
-                               name="FUSES"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x10"
-                               start="0x1050"
-                               type="fuses"/>
-               <memory-segment exec="0"
-                               name="USER_SIGNATURES"
-                               pagesize="0x40"
-                               rw="RW"
-                               size="0x40"
-                               start="0x1080"
-                               type="user_signatures"/>
-               <memory-segment exec="0"
-                               name="SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x03"
-                               start="0x1100"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="PROD_SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x7D"
-                               start="0x1103"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="EEPROM"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x200"
-                               start="0x1400"
-                               type="eeprom"/>
-               <memory-segment exec="0"
-                               name="INTERNAL_SRAM"
-                               rw="RW"
-                               size="0x1800"
-                               start="0x6800"
-                               type="ram"/>
-               <memory-segment exec="0"
-                               name="MAPPED_PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x8000"
-                               start="0x8000"
-                               type="other"/>
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x4"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x40"
+                                rw="RW"
+                                size="0x40"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x200"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1800"
+                                start="0x6800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
             </address-space>
             <address-space endianness="little"
                            id="prog"
                            name="prog"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="1"
-                               name="PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x10000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_NRWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x2000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_RWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0xE000"
-                               start="0x2000"
-                               type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x10000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_NRWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x2000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_RWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0xE000"
+                                start="0x2000"
+                                type="flash"/>
             </address-space>
-         </address-spaces>
-         <peripherals>
+        </address-spaces>
+        <peripherals>
             <module id="cmp_control_v8" name="AC">
-               <instance name="AC0">
-                  <register-group address-space="data"
-                                  name="AC0"
-                                  name-in-module="AC"
-                                  offset="0x0680"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC0"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="AC1">
-                  <register-group address-space="data"
-                                  name="AC1"
-                                  name-in-module="AC"
-                                  offset="0x0688"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC1"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="AC1">
+                    <register-group address-space="data"
+                                    name="AC1"
+                                    name-in-module="AC"
+                                    offset="0x0688"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC1"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="adc_12b_diff_ctrl_avr_v2" name="ADC">
-               <instance name="ADC0">
-                  <register-group address-space="data"
-                                  name="ADC0"
-                                  name-in-module="ADC"
-                                  offset="0x0600"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD1"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD2"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="4" pad="PD4"/>
-                     <signal function="AINN" group="AINN" index="5" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="6" pad="PD6"/>
-                     <signal function="AINN" group="AINN" index="7" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="16" pad="PF0"/>
-                     <signal function="AINN" group="AINN" index="17" pad="PF1"/>
-                     <signal function="AINN" group="AINN" index="18" pad="PF2"/>
-                     <signal function="AINN" group="AINN" index="19" pad="PF3"/>
-                     <signal function="AINN" group="AINN" index="20" pad="PF4"/>
-                     <signal function="AINN" group="AINN" index="21" pad="PF5"/>
-                     <signal function="AINN" group="AINN" index="22" pad="PA2"/>
-                     <signal function="AINN" group="AINN" index="23" pad="PA3"/>
-                     <signal function="AINN" group="AINN" index="24" pad="PA4"/>
-                     <signal function="AINN" group="AINN" index="25" pad="PA5"/>
-                     <signal function="AINN" group="AINN" index="26" pad="PA6"/>
-                     <signal function="AINN" group="AINN" index="27" pad="PA7"/>
-                     <signal function="AINN" group="AINN" index="28" pad="PC0"/>
-                     <signal function="AINN" group="AINN" index="29" pad="PC1"/>
-                     <signal function="AINN" group="AINN" index="30" pad="PC2"/>
-                     <signal function="AINN" group="AINN" index="31" pad="PC3"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD0"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD1"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="5" pad="PD5"/>
-                     <signal function="AINP" group="AINP" index="6" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="7" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="16" pad="PF0"/>
-                     <signal function="AINP" group="AINP" index="17" pad="PF1"/>
-                     <signal function="AINP" group="AINP" index="18" pad="PF2"/>
-                     <signal function="AINP" group="AINP" index="19" pad="PF3"/>
-                     <signal function="AINP" group="AINP" index="20" pad="PF4"/>
-                     <signal function="AINP" group="AINP" index="21" pad="PF5"/>
-                     <signal function="AINP" group="AINP" index="22" pad="PA2"/>
-                     <signal function="AINP" group="AINP" index="23" pad="PA3"/>
-                     <signal function="AINP" group="AINP" index="24" pad="PA4"/>
-                     <signal function="AINP" group="AINP" index="25" pad="PA5"/>
-                     <signal function="AINP" group="AINP" index="26" pad="PA6"/>
-                     <signal function="AINP" group="AINP" index="27" pad="PA7"/>
-                     <signal function="AINP" group="AINP" index="28" pad="PC0"/>
-                     <signal function="AINP" group="AINP" index="29" pad="PC1"/>
-                     <signal function="AINP" group="AINP" index="30" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="31" pad="PC3"/>
-                  </signals>
-               </instance>
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD1"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD2"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="4" pad="PD4"/>
+                        <signal function="AINN" group="AINN" index="5" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="6" pad="PD6"/>
+                        <signal function="AINN" group="AINN" index="7" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="16" pad="PF0"/>
+                        <signal function="AINN" group="AINN" index="17" pad="PF1"/>
+                        <signal function="AINN" group="AINN" index="18" pad="PF2"/>
+                        <signal function="AINN" group="AINN" index="19" pad="PF3"/>
+                        <signal function="AINN" group="AINN" index="20" pad="PF4"/>
+                        <signal function="AINN" group="AINN" index="21" pad="PF5"/>
+                        <signal function="AINN" group="AINN" index="22" pad="PA2"/>
+                        <signal function="AINN" group="AINN" index="23" pad="PA3"/>
+                        <signal function="AINN" group="AINN" index="24" pad="PA4"/>
+                        <signal function="AINN" group="AINN" index="25" pad="PA5"/>
+                        <signal function="AINN" group="AINN" index="26" pad="PA6"/>
+                        <signal function="AINN" group="AINN" index="27" pad="PA7"/>
+                        <signal function="AINN" group="AINN" index="28" pad="PC0"/>
+                        <signal function="AINN" group="AINN" index="29" pad="PC1"/>
+                        <signal function="AINN" group="AINN" index="30" pad="PC2"/>
+                        <signal function="AINN" group="AINN" index="31" pad="PC3"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD0"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD1"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="5" pad="PD5"/>
+                        <signal function="AINP" group="AINP" index="6" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="7" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="16" pad="PF0"/>
+                        <signal function="AINP" group="AINP" index="17" pad="PF1"/>
+                        <signal function="AINP" group="AINP" index="18" pad="PF2"/>
+                        <signal function="AINP" group="AINP" index="19" pad="PF3"/>
+                        <signal function="AINP" group="AINP" index="20" pad="PF4"/>
+                        <signal function="AINP" group="AINP" index="21" pad="PF5"/>
+                        <signal function="AINP" group="AINP" index="22" pad="PA2"/>
+                        <signal function="AINP" group="AINP" index="23" pad="PA3"/>
+                        <signal function="AINP" group="AINP" index="24" pad="PA4"/>
+                        <signal function="AINP" group="AINP" index="25" pad="PA5"/>
+                        <signal function="AINP" group="AINP" index="26" pad="PA6"/>
+                        <signal function="AINP" group="AINP" index="27" pad="PA7"/>
+                        <signal function="AINP" group="AINP" index="28" pad="PC0"/>
+                        <signal function="AINP" group="AINP" index="29" pad="PC1"/>
+                        <signal function="AINP" group="AINP" index="30" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="bor_lvd_ctrl_avr_v2" name="BOD">
-               <instance name="BOD">
-                  <register-group address-space="data"
-                                  name="BOD"
-                                  name-in-module="BOD"
-                                  offset="0x00A0"/>
-               </instance>
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
             </module>
             <module id="cla_ccl_v1" name="CCL">
-               <instance name="CCL">
-                  <register-group address-space="data"
-                                  name="CCL"
-                                  name-in-module="CCL"
-                                  offset="0x01C0"/>
-                  <signals>
-                     <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
-                     <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
-                     <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
-                     <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
-                     <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
-                     <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
-                     <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
-                     <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
-                     <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
-                     <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
-                     <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
-                     <signal function="IN" group="LUT3_IN" index="2" pad="PF2"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="ALT1"
-                             group="LUT0_OUT"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="DEFAULT"
-                             group="LUT0_OUT"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT1"
-                             function="DEFAULT"
-                             group="LUT1_OUT"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="ALT1"
-                             group="LUT2_OUT"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="DEFAULT"
-                             group="LUT2_OUT"
-                             pad="PD3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT3"
-                             function="DEFAULT"
-                             group="LUT3_OUT"
-                             pad="PF3"/>
-                  </signals>
-               </instance>
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
+                        <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
+                        <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
+                        <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
+                        <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
+                        <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
+                        <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
+                        <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
+                        <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
+                        <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
+                        <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
+                        <signal function="IN" group="LUT3_IN" index="2" pad="PF2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="ALT1"
+                                group="LUT0_OUT"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="DEFAULT"
+                                group="LUT0_OUT"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="DEFAULT"
+                                group="LUT1_OUT"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="ALT1"
+                                group="LUT2_OUT"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="DEFAULT"
+                                group="LUT2_OUT"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="DEFAULT"
+                                group="LUT3_OUT"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="CLKCTRL">
-               <instance name="CLKCTRL">
-                  <register-group address-space="data"
-                                  name="CLKCTRL"
-                                  name-in-module="CLKCTRL"
-                                  offset="0x0060"/>
-                  <signals>
-                     <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
-                     <signal function="OUT" group="CLKOUT" pad="PA7"/>
-                     <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
-                     <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
-                     <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
-                     <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
-                  </signals>
-               </instance>
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
+                        <signal function="OUT" group="CLKOUT" pad="PA7"/>
+                        <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
+                        <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
+                        <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
+                        <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
+                    </signals>
+                </instance>
             </module>
             <module id="cpu_avr_xt_v1" name="CPU">
-               <instance name="CPU">
-                  <register-group address-space="data"
-                                  name="CPU"
-                                  name-in-module="CPU"
-                                  offset="0x0030"/>
-                  <parameters>
-                     <param name="CORE_VERSION" value="V4S"/>
-                  </parameters>
-               </instance>
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
             </module>
             <module id="int_8bit_v3" name="CPUINT">
-               <instance name="CPUINT">
-                  <register-group address-space="data"
-                                  name="CPUINT"
-                                  name-in-module="CPUINT"
-                                  offset="0x0110"/>
-               </instance>
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
             </module>
             <module id="math_pdi_crc_v1" name="CRCSCAN">
-               <instance name="CRCSCAN">
-                  <register-group address-space="data"
-                                  name="CRCSCAN"
-                                  name-in-module="CRCSCAN"
-                                  offset="0x0120"/>
-               </instance>
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
             </module>
             <module id="dac_nbit_ctrl_avr_v6" name="DAC">
-               <instance name="DAC0">
-                  <register-group address-space="data"
-                                  name="DAC0"
-                                  name-in-module="DAC"
-                                  offset="0x06A0"/>
-                  <signals>
-                     <signal function="VOUT" group="OUT" pad="PD6"/>
-                  </signals>
-               </instance>
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="VOUT" group="OUT" pad="PD6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="EVSYS">
-               <instance name="EVSYS">
-                  <register-group address-space="data"
-                                  name="EVSYS"
-                                  name-in-module="EVSYS"
-                                  offset="0x0200"/>
-                  <signals>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="5"
-                             pad="PF7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="5"
-                             pad="PF2"/>
-                  </signals>
-               </instance>
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF2"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="FUSE">
-               <instance name="FUSE">
-                  <register-group address-space="data"
-                                  name="FUSE"
-                                  name-in-module="FUSE"
-                                  offset="0x1050"/>
-               </instance>
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
             </module>
             <module id="avrea" name="GPR">
-               <instance name="GPR">
-                  <register-group address-space="data"
-                                  name="GPR"
-                                  name-in-module="GPR"
-                                  offset="0x001C"/>
-               </instance>
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
             </module>
             <module id="avrea" name="LOCK">
-               <instance name="LOCK">
-                  <register-group address-space="data"
-                                  name="LOCK"
-                                  name-in-module="LOCK"
-                                  offset="0x1040"/>
-               </instance>
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
             </module>
             <module id="nvm_ctrl_avr_v3" name="NVMCTRL">
-               <instance name="NVMCTRL">
-                  <register-group address-space="data"
-                                  name="NVMCTRL"
-                                  name-in-module="NVMCTRL"
-                                  offset="0x1000"/>
-               </instance>
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3" name="PORT">
-               <instance name="PORTA">
-                  <register-group address-space="data"
-                                  name="PORTA"
-                                  name-in-module="PORT"
-                                  offset="0x0400"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTC">
-                  <register-group address-space="data"
-                                  name="PORTC"
-                                  name-in-module="PORT"
-                                  offset="0x0440"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-                  </signals>
-               </instance>
-               <instance name="PORTD">
-                  <register-group address-space="data"
-                                  name="PORTD"
-                                  name-in-module="PORT"
-                                  offset="0x0460"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTF">
-                  <register-group address-space="data"
-                                  name="PORTF"
-                                  name-in-module="PORT"
-                                  offset="0x04A0"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-                  </signals>
-               </instance>
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="PORTMUX">
-               <instance name="PORTMUX">
-                  <register-group address-space="data"
-                                  name="PORTMUX"
-                                  name-in-module="PORTMUX"
-                                  offset="0x05E0"/>
-               </instance>
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
             </module>
             <module id="rst_integration_avr_v2" name="RSTCTRL">
-               <instance name="RSTCTRL">
-                  <register-group address-space="data"
-                                  name="RSTCTRL"
-                                  name-in-module="RSTCTRL"
-                                  offset="0x0040"/>
-                  <signals>
-                     <signal function="OTHER" group="RESET" pad="PF6"/>
-                  </signals>
-               </instance>
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_rtc_avr_v2" name="RTC">
-               <instance name="RTC">
-                  <register-group address-space="data"
-                                  name="RTC"
-                                  name-in-module="RTC"
-                                  offset="0x0140"/>
-               </instance>
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
             </module>
             <module id="avrea" name="SIGROW">
-               <instance name="SIGROW">
-                  <register-group address-space="data"
-                                  name="SIGROW"
-                                  name-in-module="SIGROW"
-                                  offset="0x1100"/>
-               </instance>
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
             </module>
             <module id="clk_sleep_ctrl_avr_v1" name="SLPCTRL">
-               <instance name="SLPCTRL">
-                  <register-group address-space="data"
-                                  name="SLPCTRL"
-                                  name-in-module="SLPCTRL"
-                                  offset="0x0050"/>
-               </instance>
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
             </module>
             <module id="spi_8bit_v2" name="SPI">
-               <instance name="SPI0">
-                  <register-group address-space="data"
-                                  name="SPI0"
-                                  name-in-module="SPI"
-                                  offset="0x0940"/>
-                  <signals>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MISO"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MOSI"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SCK"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SS"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MISO"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MOSI"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SCK"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SS"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MOSI"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SS"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MOSI"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SCK"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SS"
-                             pad="PF7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MISO"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MOSI"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SCK"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SS"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MOSI"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SS"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="SYSCFG">
-               <instance name="SYSCFG">
-                  <register-group address-space="data"
-                                  name="SYSCFG"
-                                  name-in-module="SYSCFG"
-                                  offset="0x0F00"/>
-               </instance>
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
             </module>
             <module id="tmr_16b_pwm_v1" name="TCA">
-               <instance name="TCA0">
-                  <register-group address-space="data"
-                                  name="TCA0"
-                                  name-in-module="TCA"
-                                  offset="0x0A00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="1"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="3"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="0"
-                             pad="PD0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="1"
-                             pad="PD1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="2"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="3"
-                             pad="PD3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="4"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="5"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="0"
-                             pad="PF0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="1"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="2"
-                             pad="PF2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="3"
-                             pad="PF3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="4"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="5"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="1"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="3"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="4"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="5"
-                             pad="PA5"/>
-                  </signals>
-               </instance>
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="0"
+                                pad="PD0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="4"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="5"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_capture_v1" name="TCB">
-               <instance name="TCB0">
-                  <register-group address-space="data"
-                                  name="TCB0"
-                                  name-in-module="TCB"
-                                  offset="0x0B00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB0"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA2"/>
-                  </signals>
-               </instance>
-               <instance name="TCB1">
-                  <register-group address-space="data"
-                                  name="TCB1"
-                                  name-in-module="TCB"
-                                  offset="0x0B10"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB1"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="TCB2">
-                  <register-group address-space="data"
-                                  name="TCB2"
-                                  name-in-module="TCB"
-                                  offset="0x0B20"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB2"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                  </signals>
-               </instance>
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
             </module>
             <module id="i2c_8bit_avr_v3" name="TWI">
-               <instance name="TWI0">
-                  <register-group address-space="data"
-                                  name="TWI0"
-                                  name-in-module="TWI"
-                                  offset="0x0900"/>
-                  <signals>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SCL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SDA"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                  </signals>
-               </instance>
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
             </module>
             <module id="uart_autobd_v4" name="USART">
-               <instance name="USART0">
-                  <register-group address-space="data"
-                                  name="USART0"
-                                  name-in-module="USART"
-                                  offset="0x0800"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="RXD"
-                             index="1"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="TXD"
-                             index="1"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XCK"
-                             index="1"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XDIR"
-                             index="1"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="RXD"
-                             index="2"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="TXD"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="RXD"
-                             index="3"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="TXD"
-                             index="3"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XCK"
-                             index="3"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XDIR"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="RXD"
-                             index="4"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="TXD"
-                             index="4"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="XCK"
-                             index="4"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="USART1">
-                  <register-group address-space="data"
-                                  name="USART1"
-                                  name-in-module="USART"
-                                  offset="0x0820"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="RXD"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="TXD"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PC3"/>
-                  </signals>
-               </instance>
-               <instance name="USART2">
-                  <register-group address-space="data"
-                                  name="USART2"
-                                  name-in-module="USART"
-                                  offset="0x0840"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="ALT1"
-                             group="RXD"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="ALT1"
-                             group="TXD"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PF0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PF2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PF3"/>
-                  </signals>
-               </instance>
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="RXD"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="TXD"
+                                index="1"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XCK"
+                                index="1"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XDIR"
+                                index="1"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="RXD"
+                                index="2"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="TXD"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="RXD"
+                                index="3"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="TXD"
+                                index="3"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XCK"
+                                index="3"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XDIR"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="RXD"
+                                index="4"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="TXD"
+                                index="4"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="XCK"
+                                index="4"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART2">
+                    <register-group address-space="data"
+                                    name="USART2"
+                                    name-in-module="USART"
+                                    offset="0x0840"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="ALT1"
+                                group="RXD"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="ALT1"
+                                group="TXD"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="USERROW">
-               <instance name="USERROW">
-                  <register-group address-space="data"
-                                  name="USERROW"
-                                  name-in-module="USERROW"
-                                  offset="0x1080"/>
-               </instance>
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3_vport" name="VPORT">
-               <instance name="VPORTA">
-                  <register-group address-space="data"
-                                  name="VPORTA"
-                                  name-in-module="VPORT"
-                                  offset="0x0000"/>
-               </instance>
-               <instance name="VPORTC">
-                  <register-group address-space="data"
-                                  name="VPORTC"
-                                  name-in-module="VPORT"
-                                  offset="0x0008"/>
-               </instance>
-               <instance name="VPORTD">
-                  <register-group address-space="data"
-                                  name="VPORTD"
-                                  name-in-module="VPORT"
-                                  offset="0x000C"/>
-               </instance>
-               <instance name="VPORTF">
-                  <register-group address-space="data"
-                                  name="VPORTF"
-                                  name-in-module="VPORT"
-                                  offset="0x0014"/>
-               </instance>
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
             </module>
             <module id="avrea" name="VREF">
-               <instance name="VREF">
-                  <register-group address-space="data"
-                                  name="VREF"
-                                  name-in-module="VREF"
-                                  offset="0x00B0"/>
-                  <signals>
-                     <signal function="VREF" group="VREFA" pad="PD7"/>
-                  </signals>
-               </instance>
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                    <signals>
+                        <signal function="VREF" group="VREFA" pad="PD7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="wdt_windowed_v2" name="WDT">
-               <instance name="WDT">
-                  <register-group address-space="data"
-                                  name="WDT"
-                                  name-in-module="WDT"
-                                  offset="0x0100"/>
-               </instance>
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
             </module>
-         </peripherals>
-         <interrupts>
+        </peripherals>
+        <interrupts>
             <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
             <interrupt index="2" module-instance="BOD" name="VLM"/>
             <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
@@ -1076,5484 +1076,5484 @@
             <interrupt index="34" module-instance="USART2" name="RXC"/>
             <interrupt index="35" module-instance="USART2" name="DRE"/>
             <interrupt index="36" module-instance="USART2" name="TXC"/>
-         </interrupts>
-         <interfaces>
+        </interrupts>
+        <interfaces>
             <interface name="UPDI" type="updi"/>
-         </interfaces>
-         <property-groups>
+        </interfaces>
+        <property-groups>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x96"/>
-               <property name="SIGNATURE2" value="0x1F"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x96"/>
+                <property name="SIGNATURE2" value="0x1F"/>
             </property-group>
-         </property-groups>
-      </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window selection mode"
-                         mask="0x03"
-                         name="WINSEL"
-                         rw="RW"
-                         values="AC_WINSEL"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
-               <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="WINDOW"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_WINDOW_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-               <bitfield caption="Analog Comparator Window State"
-                         mask="0xC0"
-                         name="WINSTATE"
-                         rw="R"
-                         values="AC_WINSTATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Fastest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-         </value-group>
-         <value-group caption="Window selection mode" name="AC_WINSEL">
-            <value caption="Window function disabled" name="DISABLED" value="0x0"/>
-            <value caption="Select ACn+1 as upper limit in window compare"
-                   name="UPSEL1"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
-            <value caption="Window interrupt when input above both references"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="Window interrupt when input betweeen references"
-                   name="INSIDE"
-                   value="0x1"/>
-            <value caption="Window interrupt when input below both references"
-                   name="BELOW"
-                   value="0x2"/>
-            <value caption="Window interrupt when input outside reference"
-                   name="OUTSIDE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
-            <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
-            <value caption="Above window" name="ABOVE" value="0x0"/>
-            <value caption="Inside window" name="INSIDE" value="0x1"/>
-            <value caption="Below window" name="BELOW" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_avr_v2"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler Value"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="ADC_REFSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-               <bitfield caption="Window Mode Source"
-                         mask="0x08"
-                         name="WINSRC"
-                         rw="RW"
-                         values="ADC_WINSRC"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Enable"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Enable"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Enable"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Enable"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Flag"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Flag"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Flag"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Flag"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Flag"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Flag"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Status register"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
-            </register>
-            <register caption="Control F"
-                      initval="0x00"
-                      name="CTRLF"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample numbers"
-                         mask="0x0F"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-               <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
-               <bitfield caption="Sign Chopping"
-                         mask="0x40"
-                         name="CHOPPING"
-                         rw="RW"
-                         values="ADC_CHOPPING"/>
-            </register>
-            <register caption="Command register"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start command"
-                         mask="0x07"
-                         name="START"
-                         rw="RW"
-                         values="ADC_START"/>
-               <bitfield caption="Mode"
-                         mask="0x70"
-                         name="MODE"
-                         rw="RW"
-                         values="ADC_MODE"/>
-               <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
-            </register>
-            <register caption="PGA Control"
-                      initval="0x00"
-                      name="PGACTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
-               <bitfield caption="PGA BIAS Select"
-                         mask="0x18"
-                         name="PGABIASSEL"
-                         rw="RW"
-                         values="ADC_PGABIASSEL"/>
-               <bitfield caption="Gain"
-                         mask="0xE0"
-                         name="GAIN"
-                         rw="RW"
-                         values="ADC_GAIN"/>
-            </register>
-            <register caption="Positive Input Multiplexer"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Negative Input Multiplexer"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Result"
-                      initval="0x00000000"
-                      name="RESULT"
-                      offset="0x10"
-                      rw="R"
-                      size="4"/>
-            <register caption="Sample"
-                      initval="0x0000"
-                      name="SAMPLE"
-                      offset="0x14"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temporary Data 0"
-                      initval="0x00"
-                      name="TEMP0"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 1"
-                      initval="0x00"
-                      name="TEMP1"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 2"
-                      initval="0x00"
-                      name="TEMP2"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Window Low Threshold"
-                      initval="0x0000"
-                      name="WINLT"
-                      offset="0x1C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window High Threshold"
-                      initval="0x0000"
-                      name="WINHT"
-                      offset="0x1E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Mode select" name="ADC_MODE">
-            <value caption="Single Conversion with 8-bit resolution"
-                   name="SINGLE_8BIT"
-                   value="0x00"/>
-            <value caption="Single Conversion with 12-bit resolution"
-                   name="SINGLE_12BIT"
-                   value="0x01"/>
-            <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
-                   name="SERIES"
-                   value="0x02"/>
-            <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
-                   name="SERIES_SCALING"
-                   value="0x03"/>
-            <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST"
-                   value="0x04"/>
-            <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST_SCALING"
-                   value="0x05"/>
-         </value-group>
-         <value-group caption="Start command select" name="ADC_START">
-            <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
-            <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
-                   name="IMMEDIATE"
-                   value="0x01"/>
-            <value caption="Start when MUXPOS register is written"
-                   name="MUXPOS_WRITE"
-                   value="0x02"/>
-            <value caption="Start when MUXNEG register is written"
-                   name="MUXNEG_WRITE"
-                   value="0x03"/>
-            <value caption="Start when an event is received"
-                   name="EVENT_TRIGGER"
-                   value="0x04"/>
-         </value-group>
-         <value-group caption="Prescaler Value select" name="ADC_PRESC">
-            <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
-            <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
-            <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
-            <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
-            <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
-            <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
-            <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
-            <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
-            <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
-            <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
-            <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
-            <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
-            <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
-            <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
-            <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
-         </value-group>
-         <value-group caption="Reference select" name="ADC_REFSEL">
-            <value caption="VDD" name="VDD" value="0x00"/>
-            <value caption="External Reference" name="VREFA" value="0x02"/>
-            <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
-            <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
-            <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
-            <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Window Mode Source select" name="ADC_WINSRC">
-            <value caption="Result register used as Window Comparator Source"
-                   name="RESULT"
-                   value="0x0"/>
-            <value caption="Sample register used as Window Comparator Source"
-                   name="SAMPLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
-            <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
-            <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x0"/>
-            <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
-            <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
-            <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
-            <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
-            <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
-            <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
-            <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
-            <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
-            <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
-            <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-            <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
-            <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
-         </value-group>
-         <value-group caption="VIA select" name="ADC_VIA">
-            <value caption="Inputs connected directly to ADC"
-                   name="DIRECT"
-                   value="0x0"/>
-            <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
-            <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-         </value-group>
-         <value-group caption="Gain select" name="ADC_GAIN">
-            <value caption="1x gain" name="1X" value="0x0"/>
-            <value caption="2x gain" name="2X" value="0x1"/>
-            <value caption="4x gain" name="4X" value="0x2"/>
-            <value caption="8x gain" name="8X" value="0x3"/>
-            <value caption="16x gain" name="16X" value="0x4"/>
-         </value-group>
-         <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
-            <value caption="100% BIAS current." name="100PCT" value="0x0"/>
-            <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
-                   name="75PCT"
-                   value="0x1"/>
-            <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
-                   name="50PCT"
-                   value="0x2"/>
-            <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
-                   name="25PCT"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="INSEL2 selection" name="IN2" value="0x1"/>
-            <value caption="Internal High Frequency oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="Internal 32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC0 output input source" name="AC0" value="0x6"/>
-            <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrea" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x11"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
-               <bitfield caption="CFD Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
-               <bitfield caption="Interrupt Type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="R"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="R"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="R"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="R"/>
-               <bitfield caption="External Clock status / XOSCHF status"
-                         mask="0x10"
-                         name="EXTS"
-                         rw="R"/>
-            </register>
-            <register caption="MCLK Timebase"
-                      initval="0x00"
-                      name="MCLKTIMEBASE"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Automatic Oscillator Tune"
-                         mask="0x03"
-                         name="AUTOTUNE"
-                         rw="RW"
-                         values="CLKCTRL_AUTOTUNE"/>
-               <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      initval="0x00"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSCHF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Start-Up Time"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="Divide by 2" name="DIV2" value="0x00"/>
-            <value caption="Divide by 4" name="DIV4" value="0x01"/>
-            <value caption="Divide by 8" name="DIV8" value="0x02"/>
-            <value caption="Divide by 16" name="DIV16" value="0x03"/>
-            <value caption="Divide by 32" name="DIV32" value="0x04"/>
-            <value caption="Divide by 64" name="DIV64" value="0x05"/>
-            <value caption="Divide by 6" name="DIV6" value="0x08"/>
-            <value caption="Divide by 10" name="DIV10" value="0x09"/>
-            <value caption="Divide by 12" name="DIV12" value="0x0A"/>
-            <value caption="Divide by 24" name="DIV24" value="0x0B"/>
-            <value caption="Divide by 48" name="DIV48" value="0x0C"/>
-         </value-group>
-         <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="High Frequency Crystal Oscillator"
-                   name="XOSCHF"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular interrupt" name="INT" value="0x0"/>
-            <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Tune against 32.768 kHz Crystal Oscillator"
-                   name="XOSC32K"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
-            <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
-            <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
-         </value-group>
-         <value-group caption="Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
-            <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_avr_v6"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Range"
-                         mask="0x30"
-                         name="OUTRANGE"
-                         rw="RW"
-                         values="DAC_OUTRANGE"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
-            <value caption="Output buffer automatically choose best range"
-                   name="AUTO"
-                   value="0x0"/>
-            <value caption="Output buffer configured to low range"
-                   name="LOW"
-                   value="0x2"/>
-            <value caption="Output buffer configured to high range"
-                   name="HIGH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Event System" id="avrea" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART2"
-                      initval="0x00"
-                      name="USERUSART2IRDA"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event A"
-                      initval="0x00"
-                      name="USERTCA1CNTA"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event B"
-                      initval="0x00"
-                      name="USERTCA1CNTB"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x39"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event A"
-                      initval="0x00"
-                      name="USERTCB3CAPT"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event B"
-                      initval="0x00"
-                      name="USERTCB3COUNT"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer Event 0"
-                   name="RTC_PITEV0"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer Event 1"
-                   name="RTC_PITEV1"
-                   value="0x9"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
-            <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
-            <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
-            <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
-            <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
-            <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
-            <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
-            <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
-            <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
-            <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
-            <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter A1 overflow / low byte timer underflow"
-                   name="TCA1_OVF_LUNF"
-                   value="0x88"/>
-            <value caption="Timer/Counter A1 high byte timer underflow"
-                   name="TCA1_HUNF"
-                   value="0x89"/>
-            <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
-                   name="TCA1_CMP0_LCMP0"
-                   value="0x8C"/>
-            <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
-                   name="TCA1_CMP1_LCMP1"
-                   value="0x8D"/>
-            <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
-                   name="TCA1_CMP2_LCMP2"
-                   value="0x8E"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
-            <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrea" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="High-frequency Oscillator Frequency"
-                         mask="0x08"
-                         name="OSCHFFRQ"
-                         rw="RW"
-                         values="FUSE_OSCHFFRQ"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save"
-                         mask="0x01"
-                         name="EESAVE"
-                         rw="RW"
-                         values="FUSE_EESAVE"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x07"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="High-frequency Oscillator Frequency select"
-                      name="FUSE_OSCHFFRQ">
-            <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
-            <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
-            <value caption="EEPROM content is erased during chip erase"
-                   name="DISABLE"
-                   value="0x0"/>
-            <value caption="EEPROM content is preserved during chip erase"
-                   name="ENABLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="No External Reset" name="NONE" value="0x0"/>
-            <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
-            <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrea" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrea" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v3"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
-               <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Data"
-                      initval="0x0000"
-                      name="DATA"
-                      offset="0x08"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Address"
-                      initval="0x00000000"
-                      name="ADDR"
-                      offset="0x0C"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NOCMD" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Page Write" name="FLPW" value="0x04"/>
-            <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
-            <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
-            <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
-            <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
-            <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
-            <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
-            <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
-            <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
-            <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
-            <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
-            <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command (UPDI only)"
-                   name="EECHER"
-                   value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Attempt to program write protected area"
-                   name="WRITEPROTECT"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="CMDCOLLISION"
-                   value="0x3"/>
-            <value caption="Address cannot be written with selected command"
-                   name="WRONGSECTION"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      initval="0x00"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      initval="0x00"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      initval="0x00"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      initval="0x00"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      initval="0x00"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      initval="0x00"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Event Generation Control"
-                      initval="0x00"
-                      name="EVGENCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generator 0 Select"
-                         mask="0x07"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="PORT_EVGEN0SEL"/>
-               <bitfield caption="Event Generator 1 Select"
-                         mask="0x70"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="PORT_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Input Level Select" name="PORT_INLVL">
-            <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
-            <value caption="TTL Input level" name="TTL" value="0x1"/>
-         </value-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Routing"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Routing"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="USART route B"
-                      initval="0x00"
-                      name="USARTROUTEB"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART2 Routing"
-                         mask="0x30"
-                         name="USART2"
-                         rw="RW"
-                         values="PORTMUX_USART2"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-               <bitfield caption="TCA1 Signals"
-                         mask="0x38"
-                         name="TCA1"
-                         rw="RW"
-                         values="PORTMUX_TCA1"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-               <bitfield caption="TCB3 Output"
-                         mask="0x08"
-                         name="TCB3"
-                         rw="RW"
-                         values="PORTMUX_TCB3"/>
-            </register>
-            <register caption="AC route A"
-                      initval="0x00"
-                      name="ACROUTEA"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator 0 Output"
-                         mask="0x01"
-                         name="AC0"
-                         rw="RW"
-                         values="PORTMUX_AC0"/>
-               <bitfield caption="Analog Comparator 1 Output"
-                         mask="0x02"
-                         name="AC1"
-                         rw="RW"
-                         values="PORTMUX_AC1"/>
-            </register>
-         </register-group>
-         <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-         </value-group>
-         <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
-            <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
-            <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="PA2" name="DEFAULT" value="0x0"/>
-            <value caption="PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="PC0" name="DEFAULT" value="0x0"/>
-         </value-group>
-         <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
-            <value caption="PC1" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
-            <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
-            <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
-            <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
-            <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
-            <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
-            <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
-            <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PF4, PF5,- , -}" name="ALT1" value="0x1"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller"
-              id="rst_integration_avr_v2"
-              name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="PIT Event Generation Control A"
-                      initval="0x00"
-                      name="PITEVGENCTRLA"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generation 0 Select"
-                         mask="0x0F"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="RTC_EVGEN0SEL"/>
-               <bitfield caption="Event Generation 1 Select"
-                         mask="0xF0"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="RTC_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
-            <value caption="Internal 32.768 kHz Oscillator Divided by 32"
-                   name="OSC1K"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-         <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-         <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrea" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2"/>
-            <register caption="Serial Number Byte 0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 6"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 7"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 8"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 9"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 10"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 11"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 12"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 13"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 14"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 15"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v1"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
-               <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
-            </register>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
-            </register>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Enable"
-                         mask="0x01"
-                         name="FMEN"
-                         rw="RW"
-                         values="TWI_FMEN"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
-            <value caption="SCL duty cycle operating according to Sm specification"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="SCL duty cycle operating according to Fm specification"
-                   name="ON"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrea" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x40">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 32"
-                      name="USERROW32"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 33"
-                      name="USERROW33"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 34"
-                      name="USERROW34"
-                      offset="0x22"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 35"
-                      name="USERROW35"
-                      offset="0x23"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 36"
-                      name="USERROW36"
-                      offset="0x24"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 37"
-                      name="USERROW37"
-                      offset="0x25"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 38"
-                      name="USERROW38"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 39"
-                      name="USERROW39"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 40"
-                      name="USERROW40"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 41"
-                      name="USERROW41"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 42"
-                      name="USERROW42"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 43"
-                      name="USERROW43"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 44"
-                      name="USERROW44"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 45"
-                      name="USERROW45"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 46"
-                      name="USERROW46"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 47"
-                      name="USERROW47"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 48"
-                      name="USERROW48"
-                      offset="0x30"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 49"
-                      name="USERROW49"
-                      offset="0x31"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 50"
-                      name="USERROW50"
-                      offset="0x32"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 51"
-                      name="USERROW51"
-                      offset="0x33"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 52"
-                      name="USERROW52"
-                      offset="0x34"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 53"
-                      name="USERROW53"
-                      offset="0x35"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 54"
-                      name="USERROW54"
-                      offset="0x36"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 55"
-                      name="USERROW55"
-                      offset="0x37"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 56"
-                      name="USERROW56"
-                      offset="0x38"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 57"
-                      name="USERROW57"
-                      offset="0x39"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 58"
-                      name="USERROW58"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 59"
-                      name="USERROW59"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 60"
-                      name="USERROW60"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 61"
-                      name="USERROW61"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 62"
-                      name="USERROW62"
-                      offset="0x3E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 63"
-                      name="USERROW63"
-                      offset="0x3F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrea" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
-            <value caption="VDD as reference" name="VDD" value="0x5"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN32">
-         <pin pad="PA3" position="1"/>
-         <pin pad="PA4" position="2"/>
-         <pin pad="PA5" position="3"/>
-         <pin pad="PA6" position="4"/>
-         <pin pad="PA7" position="5"/>
-         <pin pad="PC0" position="6"/>
-         <pin pad="PC1" position="7"/>
-         <pin pad="PC2" position="8"/>
-         <pin pad="PC3" position="9"/>
-         <pin pad="PD0" position="10"/>
-         <pin pad="PD1" position="11"/>
-         <pin pad="PD2" position="12"/>
-         <pin pad="PD3" position="13"/>
-         <pin pad="PD4" position="14"/>
-         <pin pad="PD5" position="15"/>
-         <pin pad="PD6" position="16"/>
-         <pin pad="PD7" position="17"/>
-         <pin pad="VDD" position="18"/>
-         <pin pad="GND" position="19"/>
-         <pin pad="PF0" position="20"/>
-         <pin pad="PF1" position="21"/>
-         <pin pad="PF2" position="22"/>
-         <pin pad="PF3" position="23"/>
-         <pin pad="PF4" position="24"/>
-         <pin pad="PF5" position="25"/>
-         <pin pad="PF6" position="26"/>
-         <pin pad="PF7" position="27"/>
-         <pin pad="VDD1" position="28"/>
-         <pin pad="GND1" position="29"/>
-         <pin pad="PA0" position="30"/>
-         <pin pad="PA1" position="31"/>
-         <pin pad="PA2" position="32"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window selection mode"
+                              mask="0x03"
+                              name="WINSEL"
+                              rw="RW"
+                              values="AC_WINSEL"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
+                    <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="WINDOW"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_WINDOW_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                    <bitfield caption="Analog Comparator Window State"
+                              mask="0xC0"
+                              name="WINSTATE"
+                              rw="R"
+                              values="AC_WINSTATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Fastest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+            </value-group>
+            <value-group caption="Window selection mode" name="AC_WINSEL">
+                <value caption="Window function disabled" name="DISABLED" value="0x0"/>
+                <value caption="Select ACn+1 as upper limit in window compare"
+                       name="UPSEL1"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
+                <value caption="Window interrupt when input above both references"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="Window interrupt when input betweeen references"
+                       name="INSIDE"
+                       value="0x1"/>
+                <value caption="Window interrupt when input below both references"
+                       name="BELOW"
+                       value="0x2"/>
+                <value caption="Window interrupt when input outside reference"
+                       name="OUTSIDE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
+                <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
+                <value caption="Above window" name="ABOVE" value="0x0"/>
+                <value caption="Inside window" name="INSIDE" value="0x1"/>
+                <value caption="Below window" name="BELOW" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_avr_v2"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler Value"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="ADC_REFSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                    <bitfield caption="Window Mode Source"
+                              mask="0x08"
+                              name="WINSRC"
+                              rw="RW"
+                              values="ADC_WINSRC"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Enable"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Enable"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Enable"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Enable"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Flag"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Flag"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Flag"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Flag"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Flag"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Flag"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Status register"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
+                </register>
+                <register caption="Control F"
+                          initval="0x00"
+                          name="CTRLF"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample numbers"
+                              mask="0x0F"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                    <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Sign Chopping"
+                              mask="0x40"
+                              name="CHOPPING"
+                              rw="RW"
+                              values="ADC_CHOPPING"/>
+                </register>
+                <register caption="Command register"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start command"
+                              mask="0x07"
+                              name="START"
+                              rw="RW"
+                              values="ADC_START"/>
+                    <bitfield caption="Mode"
+                              mask="0x70"
+                              name="MODE"
+                              rw="RW"
+                              values="ADC_MODE"/>
+                    <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
+                </register>
+                <register caption="PGA Control"
+                          initval="0x00"
+                          name="PGACTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
+                    <bitfield caption="PGA BIAS Select"
+                              mask="0x18"
+                              name="PGABIASSEL"
+                              rw="RW"
+                              values="ADC_PGABIASSEL"/>
+                    <bitfield caption="Gain"
+                              mask="0xE0"
+                              name="GAIN"
+                              rw="RW"
+                              values="ADC_GAIN"/>
+                </register>
+                <register caption="Positive Input Multiplexer"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Negative Input Multiplexer"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Result"
+                          initval="0x00000000"
+                          name="RESULT"
+                          offset="0x10"
+                          rw="R"
+                          size="4"/>
+                <register caption="Sample"
+                          initval="0x0000"
+                          name="SAMPLE"
+                          offset="0x14"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temporary Data 0"
+                          initval="0x00"
+                          name="TEMP0"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 1"
+                          initval="0x00"
+                          name="TEMP1"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 2"
+                          initval="0x00"
+                          name="TEMP2"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Window Low Threshold"
+                          initval="0x0000"
+                          name="WINLT"
+                          offset="0x1C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window High Threshold"
+                          initval="0x0000"
+                          name="WINHT"
+                          offset="0x1E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Mode select" name="ADC_MODE">
+                <value caption="Single Conversion with 8-bit resolution"
+                       name="SINGLE_8BIT"
+                       value="0x00"/>
+                <value caption="Single Conversion with 12-bit resolution"
+                       name="SINGLE_12BIT"
+                       value="0x01"/>
+                <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
+                       name="SERIES"
+                       value="0x02"/>
+                <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
+                       name="SERIES_SCALING"
+                       value="0x03"/>
+                <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST"
+                       value="0x04"/>
+                <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST_SCALING"
+                       value="0x05"/>
+            </value-group>
+            <value-group caption="Start command select" name="ADC_START">
+                <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
+                <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
+                       name="IMMEDIATE"
+                       value="0x01"/>
+                <value caption="Start when MUXPOS register is written"
+                       name="MUXPOS_WRITE"
+                       value="0x02"/>
+                <value caption="Start when MUXNEG register is written"
+                       name="MUXNEG_WRITE"
+                       value="0x03"/>
+                <value caption="Start when an event is received"
+                       name="EVENT_TRIGGER"
+                       value="0x04"/>
+            </value-group>
+            <value-group caption="Prescaler Value select" name="ADC_PRESC">
+                <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
+                <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
+                <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
+                <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
+                <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
+                <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
+                <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
+                <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
+                <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
+                <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
+                <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
+                <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
+                <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
+                <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
+                <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
+            </value-group>
+            <value-group caption="Reference select" name="ADC_REFSEL">
+                <value caption="VDD" name="VDD" value="0x00"/>
+                <value caption="External Reference" name="VREFA" value="0x02"/>
+                <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
+                <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
+                <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
+                <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Window Mode Source select" name="ADC_WINSRC">
+                <value caption="Result register used as Window Comparator Source"
+                       name="RESULT"
+                       value="0x0"/>
+                <value caption="Sample register used as Window Comparator Source"
+                       name="SAMPLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
+                <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
+                <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x0"/>
+                <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
+                <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
+                <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
+                <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
+                <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
+                <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
+                <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
+                <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
+                <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
+                <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+                <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
+                <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
+            </value-group>
+            <value-group caption="VIA select" name="ADC_VIA">
+                <value caption="Inputs connected directly to ADC"
+                       name="DIRECT"
+                       value="0x0"/>
+                <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
+                <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+            </value-group>
+            <value-group caption="Gain select" name="ADC_GAIN">
+                <value caption="1x gain" name="1X" value="0x0"/>
+                <value caption="2x gain" name="2X" value="0x1"/>
+                <value caption="4x gain" name="4X" value="0x2"/>
+                <value caption="8x gain" name="8X" value="0x3"/>
+                <value caption="16x gain" name="16X" value="0x4"/>
+            </value-group>
+            <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
+                <value caption="100% BIAS current." name="100PCT" value="0x0"/>
+                <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
+                       name="75PCT"
+                       value="0x1"/>
+                <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
+                       name="50PCT"
+                       value="0x2"/>
+                <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
+                       name="25PCT"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="INSEL2 selection" name="IN2" value="0x1"/>
+                <value caption="Internal High Frequency oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="Internal 32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC0 output input source" name="AC0" value="0x6"/>
+                <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrea" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x11"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
+                    <bitfield caption="CFD Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
+                    <bitfield caption="Interrupt Type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="R"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="R"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="R"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="R"/>
+                    <bitfield caption="External Clock status / XOSCHF status"
+                              mask="0x10"
+                              name="EXTS"
+                              rw="R"/>
+                </register>
+                <register caption="MCLK Timebase"
+                          initval="0x00"
+                          name="MCLKTIMEBASE"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Automatic Oscillator Tune"
+                              mask="0x03"
+                              name="AUTOTUNE"
+                              rw="RW"
+                              values="CLKCTRL_AUTOTUNE"/>
+                    <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          initval="0x00"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSCHF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Start-Up Time"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="Divide by 2" name="DIV2" value="0x00"/>
+                <value caption="Divide by 4" name="DIV4" value="0x01"/>
+                <value caption="Divide by 8" name="DIV8" value="0x02"/>
+                <value caption="Divide by 16" name="DIV16" value="0x03"/>
+                <value caption="Divide by 32" name="DIV32" value="0x04"/>
+                <value caption="Divide by 64" name="DIV64" value="0x05"/>
+                <value caption="Divide by 6" name="DIV6" value="0x08"/>
+                <value caption="Divide by 10" name="DIV10" value="0x09"/>
+                <value caption="Divide by 12" name="DIV12" value="0x0A"/>
+                <value caption="Divide by 24" name="DIV24" value="0x0B"/>
+                <value caption="Divide by 48" name="DIV48" value="0x0C"/>
+            </value-group>
+            <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="High Frequency Crystal Oscillator"
+                       name="XOSCHF"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular interrupt" name="INT" value="0x0"/>
+                <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Tune against 32.768 kHz Crystal Oscillator"
+                       name="XOSC32K"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
+                <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
+                <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
+            </value-group>
+            <value-group caption="Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
+                <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_avr_v6"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Range"
+                              mask="0x30"
+                              name="OUTRANGE"
+                              rw="RW"
+                              values="DAC_OUTRANGE"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
+                <value caption="Output buffer automatically choose best range"
+                       name="AUTO"
+                       value="0x0"/>
+                <value caption="Output buffer configured to low range"
+                       name="LOW"
+                       value="0x2"/>
+                <value caption="Output buffer configured to high range"
+                       name="HIGH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Event System" id="avrea" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART2"
+                          initval="0x00"
+                          name="USERUSART2IRDA"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event A"
+                          initval="0x00"
+                          name="USERTCA1CNTA"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event B"
+                          initval="0x00"
+                          name="USERTCA1CNTB"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x39"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event A"
+                          initval="0x00"
+                          name="USERTCB3CAPT"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event B"
+                          initval="0x00"
+                          name="USERTCB3COUNT"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer Event 0"
+                       name="RTC_PITEV0"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer Event 1"
+                       name="RTC_PITEV1"
+                       value="0x9"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
+                <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
+                <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
+                <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
+                <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
+                <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
+                <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
+                <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
+                <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
+                <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
+                <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter A1 overflow / low byte timer underflow"
+                       name="TCA1_OVF_LUNF"
+                       value="0x88"/>
+                <value caption="Timer/Counter A1 high byte timer underflow"
+                       name="TCA1_HUNF"
+                       value="0x89"/>
+                <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
+                       name="TCA1_CMP0_LCMP0"
+                       value="0x8C"/>
+                <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
+                       name="TCA1_CMP1_LCMP1"
+                       value="0x8D"/>
+                <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
+                       name="TCA1_CMP2_LCMP2"
+                       value="0x8E"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
+                <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrea" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="High-frequency Oscillator Frequency"
+                              mask="0x08"
+                              name="OSCHFFRQ"
+                              rw="RW"
+                              values="FUSE_OSCHFFRQ"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save"
+                              mask="0x01"
+                              name="EESAVE"
+                              rw="RW"
+                              values="FUSE_EESAVE"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x07"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="High-frequency Oscillator Frequency select"
+                         name="FUSE_OSCHFFRQ">
+                <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
+                <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
+                <value caption="EEPROM content is erased during chip erase"
+                       name="DISABLE"
+                       value="0x0"/>
+                <value caption="EEPROM content is preserved during chip erase"
+                       name="ENABLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="No External Reset" name="NONE" value="0x0"/>
+                <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
+                <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrea" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrea" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v3"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Data"
+                          initval="0x0000"
+                          name="DATA"
+                          offset="0x08"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Address"
+                          initval="0x00000000"
+                          name="ADDR"
+                          offset="0x0C"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NOCMD" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Page Write" name="FLPW" value="0x04"/>
+                <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
+                <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
+                <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
+                <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
+                <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
+                <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
+                <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
+                <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
+                <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
+                <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
+                <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command (UPDI only)"
+                       name="EECHER"
+                       value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Attempt to program write protected area"
+                       name="WRITEPROTECT"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="CMDCOLLISION"
+                       value="0x3"/>
+                <value caption="Address cannot be written with selected command"
+                       name="WRONGSECTION"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          initval="0x00"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          initval="0x00"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          initval="0x00"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          initval="0x00"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          initval="0x00"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          initval="0x00"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Event Generation Control"
+                          initval="0x00"
+                          name="EVGENCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generator 0 Select"
+                              mask="0x07"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="PORT_EVGEN0SEL"/>
+                    <bitfield caption="Event Generator 1 Select"
+                              mask="0x70"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="PORT_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Input Level Select" name="PORT_INLVL">
+                <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
+                <value caption="TTL Input level" name="TTL" value="0x1"/>
+            </value-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Routing"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Routing"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="USART route B"
+                          initval="0x00"
+                          name="USARTROUTEB"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART2 Routing"
+                              mask="0x30"
+                              name="USART2"
+                              rw="RW"
+                              values="PORTMUX_USART2"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                    <bitfield caption="TCA1 Signals"
+                              mask="0x38"
+                              name="TCA1"
+                              rw="RW"
+                              values="PORTMUX_TCA1"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                    <bitfield caption="TCB3 Output"
+                              mask="0x08"
+                              name="TCB3"
+                              rw="RW"
+                              values="PORTMUX_TCB3"/>
+                </register>
+                <register caption="AC route A"
+                          initval="0x00"
+                          name="ACROUTEA"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator 0 Output"
+                              mask="0x01"
+                              name="AC0"
+                              rw="RW"
+                              values="PORTMUX_AC0"/>
+                    <bitfield caption="Analog Comparator 1 Output"
+                              mask="0x02"
+                              name="AC1"
+                              rw="RW"
+                              values="PORTMUX_AC1"/>
+                </register>
+            </register-group>
+            <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+            </value-group>
+            <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
+                <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
+                <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="PA2" name="DEFAULT" value="0x0"/>
+                <value caption="PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="PC0" name="DEFAULT" value="0x0"/>
+            </value-group>
+            <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
+                <value caption="PC1" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
+                <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
+                <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
+                <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
+                <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
+                <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
+                <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
+                <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PF4, PF5,- , -}" name="ALT1" value="0x1"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller"
+                id="rst_integration_avr_v2"
+                name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="PIT Event Generation Control A"
+                          initval="0x00"
+                          name="PITEVGENCTRLA"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generation 0 Select"
+                              mask="0x0F"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="RTC_EVGEN0SEL"/>
+                    <bitfield caption="Event Generation 1 Select"
+                              mask="0xF0"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="RTC_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
+                <value caption="Internal 32.768 kHz Oscillator Divided by 32"
+                       name="OSC1K"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+            <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+            <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrea" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2"/>
+                <register caption="Serial Number Byte 0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 6"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 7"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 8"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 9"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 10"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 11"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 12"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 13"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 14"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 15"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v1"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
+                    <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
+                </register>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
+                </register>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Enable"
+                              mask="0x01"
+                              name="FMEN"
+                              rw="RW"
+                              values="TWI_FMEN"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
+                <value caption="SCL duty cycle operating according to Sm specification"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="SCL duty cycle operating according to Fm specification"
+                       name="ON"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrea" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x40">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 32"
+                          name="USERROW32"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 33"
+                          name="USERROW33"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 34"
+                          name="USERROW34"
+                          offset="0x22"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 35"
+                          name="USERROW35"
+                          offset="0x23"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 36"
+                          name="USERROW36"
+                          offset="0x24"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 37"
+                          name="USERROW37"
+                          offset="0x25"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 38"
+                          name="USERROW38"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 39"
+                          name="USERROW39"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 40"
+                          name="USERROW40"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 41"
+                          name="USERROW41"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 42"
+                          name="USERROW42"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 43"
+                          name="USERROW43"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 44"
+                          name="USERROW44"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 45"
+                          name="USERROW45"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 46"
+                          name="USERROW46"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 47"
+                          name="USERROW47"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 48"
+                          name="USERROW48"
+                          offset="0x30"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 49"
+                          name="USERROW49"
+                          offset="0x31"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 50"
+                          name="USERROW50"
+                          offset="0x32"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 51"
+                          name="USERROW51"
+                          offset="0x33"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 52"
+                          name="USERROW52"
+                          offset="0x34"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 53"
+                          name="USERROW53"
+                          offset="0x35"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 54"
+                          name="USERROW54"
+                          offset="0x36"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 55"
+                          name="USERROW55"
+                          offset="0x37"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 56"
+                          name="USERROW56"
+                          offset="0x38"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 57"
+                          name="USERROW57"
+                          offset="0x39"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 58"
+                          name="USERROW58"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 59"
+                          name="USERROW59"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 60"
+                          name="USERROW60"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 61"
+                          name="USERROW61"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 62"
+                          name="USERROW62"
+                          offset="0x3E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 63"
+                          name="USERROW63"
+                          offset="0x3F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrea" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
+                <value caption="VDD as reference" name="VDD" value="0x5"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN32">
+            <pin pad="PA3" position="1"/>
+            <pin pad="PA4" position="2"/>
+            <pin pad="PA5" position="3"/>
+            <pin pad="PA6" position="4"/>
+            <pin pad="PA7" position="5"/>
+            <pin pad="PC0" position="6"/>
+            <pin pad="PC1" position="7"/>
+            <pin pad="PC2" position="8"/>
+            <pin pad="PC3" position="9"/>
+            <pin pad="PD0" position="10"/>
+            <pin pad="PD1" position="11"/>
+            <pin pad="PD2" position="12"/>
+            <pin pad="PD3" position="13"/>
+            <pin pad="PD4" position="14"/>
+            <pin pad="PD5" position="15"/>
+            <pin pad="PD6" position="16"/>
+            <pin pad="PD7" position="17"/>
+            <pin pad="VDD" position="18"/>
+            <pin pad="GND" position="19"/>
+            <pin pad="PF0" position="20"/>
+            <pin pad="PF1" position="21"/>
+            <pin pad="PF2" position="22"/>
+            <pin pad="PF3" position="23"/>
+            <pin pad="PF4" position="24"/>
+            <pin pad="PF5" position="25"/>
+            <pin pad="PF6" position="26"/>
+            <pin pad="PF7" position="27"/>
+            <pin pad="VDD1" position="28"/>
+            <pin pad="GND1" position="29"/>
+            <pin pad="PA0" position="30"/>
+            <pin pad="PA1" position="31"/>
+            <pin pad="PA2" position="32"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA48.xml
index 3b1b5dca..54ecdc4f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/E-SERIES/AVR64EA48.xml
@@ -1,1332 +1,1332 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <target-description-file>
-   <variants>
-      <variant ordercode="AVR64EA48"
-               package="VQFN48"
-               pinout="QFN48"
-               speedmax="20000000"
-               tempmax="125"
-               tempmin="-40"
-               vccmax="5.5"
-               vccmin="1.8"/>
-   </variants>
-   <device architecture="AVR8X" avr-family="AVR EA" name="AVR64EA48" family="AVR8">
-         <address-spaces>
+    <variants>
+        <variant ordercode="AVR64EA48"
+                 package="VQFN48"
+                 pinout="QFN48"
+                 speedmax="20000000"
+                 tempmax="125"
+                 tempmin="-40"
+                 vccmax="5.5"
+                 vccmin="1.8"/>
+    </variants>
+    <device name="AVR64EA48" family="AVR8" architecture="AVR8X" avr-family="AVR EA">
+        <address-spaces>
             <address-space endianness="little"
                            id="data"
                            name="data"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="0"
-                               name="IO"
-                               rw="RW"
-                               size="0x103F"
-                               start="0x00"
-                               type="io"/>
-               <memory-segment exec="0"
-                               name="LOCKBITS"
-                               pagesize="0x4"
-                               rw="RW"
-                               size="0x04"
-                               start="0x1040"
-                               type="lockbits"/>
-               <memory-segment exec="0"
-                               name="FUSES"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x10"
-                               start="0x1050"
-                               type="fuses"/>
-               <memory-segment exec="0"
-                               name="USER_SIGNATURES"
-                               pagesize="0x40"
-                               rw="RW"
-                               size="0x40"
-                               start="0x1080"
-                               type="user_signatures"/>
-               <memory-segment exec="0"
-                               name="SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x03"
-                               start="0x1100"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="PROD_SIGNATURES"
-                               pagesize="0x80"
-                               rw="R"
-                               size="0x7D"
-                               start="0x1103"
-                               type="signatures"/>
-               <memory-segment exec="0"
-                               name="EEPROM"
-                               pagesize="0x8"
-                               rw="RW"
-                               size="0x200"
-                               start="0x1400"
-                               type="eeprom"/>
-               <memory-segment exec="0"
-                               name="INTERNAL_SRAM"
-                               rw="RW"
-                               size="0x1800"
-                               start="0x6800"
-                               type="ram"/>
-               <memory-segment exec="0"
-                               name="MAPPED_PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x8000"
-                               start="0x8000"
-                               type="other"/>
+                <memory-segment exec="0"
+                                name="IO"
+                                rw="RW"
+                                size="0x103F"
+                                start="0x00"
+                                type="io"/>
+                <memory-segment exec="0"
+                                name="LOCKBITS"
+                                pagesize="0x4"
+                                rw="RW"
+                                size="0x04"
+                                start="0x1040"
+                                type="lockbits"/>
+                <memory-segment exec="0"
+                                name="FUSES"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x10"
+                                start="0x1050"
+                                type="fuses"/>
+                <memory-segment exec="0"
+                                name="USER_SIGNATURES"
+                                pagesize="0x40"
+                                rw="RW"
+                                size="0x40"
+                                start="0x1080"
+                                type="user_signatures"/>
+                <memory-segment exec="0"
+                                name="SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x03"
+                                start="0x1100"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="PROD_SIGNATURES"
+                                pagesize="0x80"
+                                rw="R"
+                                size="0x7D"
+                                start="0x1103"
+                                type="signatures"/>
+                <memory-segment exec="0"
+                                name="EEPROM"
+                                pagesize="0x8"
+                                rw="RW"
+                                size="0x200"
+                                start="0x1400"
+                                type="eeprom"/>
+                <memory-segment exec="0"
+                                name="INTERNAL_SRAM"
+                                rw="RW"
+                                size="0x1800"
+                                start="0x6800"
+                                type="ram"/>
+                <memory-segment exec="0"
+                                name="MAPPED_PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x8000"
+                                start="0x8000"
+                                type="other"/>
             </address-space>
             <address-space endianness="little"
                            id="prog"
                            name="prog"
                            size="0x10000"
                            start="0x0000">
-               <memory-segment exec="1"
-                               name="PROGMEM"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x10000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_NRWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0x2000"
-                               start="0x00"
-                               type="flash"/>
-               <memory-segment exec="1"
-                               name="PROGMEM_RWW"
-                               pagesize="0x80"
-                               rw="RW"
-                               size="0xE000"
-                               start="0x2000"
-                               type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x10000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_NRWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0x2000"
+                                start="0x00"
+                                type="flash"/>
+                <memory-segment exec="1"
+                                name="PROGMEM_RWW"
+                                pagesize="0x80"
+                                rw="RW"
+                                size="0xE000"
+                                start="0x2000"
+                                type="flash"/>
             </address-space>
-         </address-spaces>
-         <peripherals>
+        </address-spaces>
+        <peripherals>
             <module id="cmp_control_v8" name="AC">
-               <instance name="AC0">
-                  <register-group address-space="data"
-                                  name="AC0"
-                                  name-in-module="AC"
-                                  offset="0x0680"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PE0"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PE2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC0"
-                             function="ALT1"
-                             group="OUT"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.ACROUTEA.AC0"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="AC1">
-                  <register-group address-space="data"
-                                  name="AC1"
-                                  name-in-module="AC"
-                                  offset="0x0688"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PC3"/>
-                     <signal field="PORTMUX.ACROUTEA.AC1"
-                             function="ALT1"
-                             group="OUT"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.ACROUTEA.AC1"
-                             function="DEFAULT"
-                             group="OUT"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="AC0">
+                    <register-group address-space="data"
+                                    name="AC0"
+                                    name-in-module="AC"
+                                    offset="0x0680"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PE0"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PE2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="ALT1"
+                                group="OUT"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.ACROUTEA.AC0"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="AC1">
+                    <register-group address-space="data"
+                                    name="AC1"
+                                    name-in-module="AC"
+                                    offset="0x0688"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PC3"/>
+                        <signal field="PORTMUX.ACROUTEA.AC1"
+                                function="ALT1"
+                                group="OUT"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.ACROUTEA.AC1"
+                                function="DEFAULT"
+                                group="OUT"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="adc_12b_diff_ctrl_avr_v2" name="ADC">
-               <instance name="ADC0">
-                  <register-group address-space="data"
-                                  name="ADC0"
-                                  name-in-module="ADC"
-                                  offset="0x0600"/>
-                  <signals>
-                     <signal function="AINN" group="AINN" index="0" pad="PD0"/>
-                     <signal function="AINN" group="AINN" index="1" pad="PD1"/>
-                     <signal function="AINN" group="AINN" index="2" pad="PD2"/>
-                     <signal function="AINN" group="AINN" index="3" pad="PD3"/>
-                     <signal function="AINN" group="AINN" index="4" pad="PD4"/>
-                     <signal function="AINN" group="AINN" index="5" pad="PD5"/>
-                     <signal function="AINN" group="AINN" index="6" pad="PD6"/>
-                     <signal function="AINN" group="AINN" index="7" pad="PD7"/>
-                     <signal function="AINN" group="AINN" index="8" pad="PE0"/>
-                     <signal function="AINN" group="AINN" index="9" pad="PE1"/>
-                     <signal function="AINN" group="AINN" index="10" pad="PE2"/>
-                     <signal function="AINN" group="AINN" index="11" pad="PE3"/>
-                     <signal function="AINN" group="AINN" index="16" pad="PF0"/>
-                     <signal function="AINN" group="AINN" index="17" pad="PF1"/>
-                     <signal function="AINN" group="AINN" index="18" pad="PF2"/>
-                     <signal function="AINN" group="AINN" index="19" pad="PF3"/>
-                     <signal function="AINN" group="AINN" index="20" pad="PF4"/>
-                     <signal function="AINN" group="AINN" index="21" pad="PF5"/>
-                     <signal function="AINN" group="AINN" index="22" pad="PA2"/>
-                     <signal function="AINN" group="AINN" index="23" pad="PA3"/>
-                     <signal function="AINN" group="AINN" index="24" pad="PA4"/>
-                     <signal function="AINN" group="AINN" index="25" pad="PA5"/>
-                     <signal function="AINN" group="AINN" index="26" pad="PA6"/>
-                     <signal function="AINN" group="AINN" index="27" pad="PA7"/>
-                     <signal function="AINN" group="AINN" index="28" pad="PC0"/>
-                     <signal function="AINN" group="AINN" index="29" pad="PC1"/>
-                     <signal function="AINN" group="AINN" index="30" pad="PC2"/>
-                     <signal function="AINN" group="AINN" index="31" pad="PC3"/>
-                     <signal function="AINP" group="AINP" index="0" pad="PD0"/>
-                     <signal function="AINP" group="AINP" index="1" pad="PD1"/>
-                     <signal function="AINP" group="AINP" index="2" pad="PD2"/>
-                     <signal function="AINP" group="AINP" index="3" pad="PD3"/>
-                     <signal function="AINP" group="AINP" index="4" pad="PD4"/>
-                     <signal function="AINP" group="AINP" index="5" pad="PD5"/>
-                     <signal function="AINP" group="AINP" index="6" pad="PD6"/>
-                     <signal function="AINP" group="AINP" index="7" pad="PD7"/>
-                     <signal function="AINP" group="AINP" index="8" pad="PE0"/>
-                     <signal function="AINP" group="AINP" index="9" pad="PE1"/>
-                     <signal function="AINP" group="AINP" index="10" pad="PE2"/>
-                     <signal function="AINP" group="AINP" index="11" pad="PE3"/>
-                     <signal function="AINP" group="AINP" index="16" pad="PF0"/>
-                     <signal function="AINP" group="AINP" index="17" pad="PF1"/>
-                     <signal function="AINP" group="AINP" index="18" pad="PF2"/>
-                     <signal function="AINP" group="AINP" index="19" pad="PF3"/>
-                     <signal function="AINP" group="AINP" index="20" pad="PF4"/>
-                     <signal function="AINP" group="AINP" index="21" pad="PF5"/>
-                     <signal function="AINP" group="AINP" index="22" pad="PA2"/>
-                     <signal function="AINP" group="AINP" index="23" pad="PA3"/>
-                     <signal function="AINP" group="AINP" index="24" pad="PA4"/>
-                     <signal function="AINP" group="AINP" index="25" pad="PA5"/>
-                     <signal function="AINP" group="AINP" index="26" pad="PA6"/>
-                     <signal function="AINP" group="AINP" index="27" pad="PA7"/>
-                     <signal function="AINP" group="AINP" index="28" pad="PC0"/>
-                     <signal function="AINP" group="AINP" index="29" pad="PC1"/>
-                     <signal function="AINP" group="AINP" index="30" pad="PC2"/>
-                     <signal function="AINP" group="AINP" index="31" pad="PC3"/>
-                  </signals>
-               </instance>
+                <instance name="ADC0">
+                    <register-group address-space="data"
+                                    name="ADC0"
+                                    name-in-module="ADC"
+                                    offset="0x0600"/>
+                    <signals>
+                        <signal function="AINN" group="AINN" index="0" pad="PD0"/>
+                        <signal function="AINN" group="AINN" index="1" pad="PD1"/>
+                        <signal function="AINN" group="AINN" index="2" pad="PD2"/>
+                        <signal function="AINN" group="AINN" index="3" pad="PD3"/>
+                        <signal function="AINN" group="AINN" index="4" pad="PD4"/>
+                        <signal function="AINN" group="AINN" index="5" pad="PD5"/>
+                        <signal function="AINN" group="AINN" index="6" pad="PD6"/>
+                        <signal function="AINN" group="AINN" index="7" pad="PD7"/>
+                        <signal function="AINN" group="AINN" index="8" pad="PE0"/>
+                        <signal function="AINN" group="AINN" index="9" pad="PE1"/>
+                        <signal function="AINN" group="AINN" index="10" pad="PE2"/>
+                        <signal function="AINN" group="AINN" index="11" pad="PE3"/>
+                        <signal function="AINN" group="AINN" index="16" pad="PF0"/>
+                        <signal function="AINN" group="AINN" index="17" pad="PF1"/>
+                        <signal function="AINN" group="AINN" index="18" pad="PF2"/>
+                        <signal function="AINN" group="AINN" index="19" pad="PF3"/>
+                        <signal function="AINN" group="AINN" index="20" pad="PF4"/>
+                        <signal function="AINN" group="AINN" index="21" pad="PF5"/>
+                        <signal function="AINN" group="AINN" index="22" pad="PA2"/>
+                        <signal function="AINN" group="AINN" index="23" pad="PA3"/>
+                        <signal function="AINN" group="AINN" index="24" pad="PA4"/>
+                        <signal function="AINN" group="AINN" index="25" pad="PA5"/>
+                        <signal function="AINN" group="AINN" index="26" pad="PA6"/>
+                        <signal function="AINN" group="AINN" index="27" pad="PA7"/>
+                        <signal function="AINN" group="AINN" index="28" pad="PC0"/>
+                        <signal function="AINN" group="AINN" index="29" pad="PC1"/>
+                        <signal function="AINN" group="AINN" index="30" pad="PC2"/>
+                        <signal function="AINN" group="AINN" index="31" pad="PC3"/>
+                        <signal function="AINP" group="AINP" index="0" pad="PD0"/>
+                        <signal function="AINP" group="AINP" index="1" pad="PD1"/>
+                        <signal function="AINP" group="AINP" index="2" pad="PD2"/>
+                        <signal function="AINP" group="AINP" index="3" pad="PD3"/>
+                        <signal function="AINP" group="AINP" index="4" pad="PD4"/>
+                        <signal function="AINP" group="AINP" index="5" pad="PD5"/>
+                        <signal function="AINP" group="AINP" index="6" pad="PD6"/>
+                        <signal function="AINP" group="AINP" index="7" pad="PD7"/>
+                        <signal function="AINP" group="AINP" index="8" pad="PE0"/>
+                        <signal function="AINP" group="AINP" index="9" pad="PE1"/>
+                        <signal function="AINP" group="AINP" index="10" pad="PE2"/>
+                        <signal function="AINP" group="AINP" index="11" pad="PE3"/>
+                        <signal function="AINP" group="AINP" index="16" pad="PF0"/>
+                        <signal function="AINP" group="AINP" index="17" pad="PF1"/>
+                        <signal function="AINP" group="AINP" index="18" pad="PF2"/>
+                        <signal function="AINP" group="AINP" index="19" pad="PF3"/>
+                        <signal function="AINP" group="AINP" index="20" pad="PF4"/>
+                        <signal function="AINP" group="AINP" index="21" pad="PF5"/>
+                        <signal function="AINP" group="AINP" index="22" pad="PA2"/>
+                        <signal function="AINP" group="AINP" index="23" pad="PA3"/>
+                        <signal function="AINP" group="AINP" index="24" pad="PA4"/>
+                        <signal function="AINP" group="AINP" index="25" pad="PA5"/>
+                        <signal function="AINP" group="AINP" index="26" pad="PA6"/>
+                        <signal function="AINP" group="AINP" index="27" pad="PA7"/>
+                        <signal function="AINP" group="AINP" index="28" pad="PC0"/>
+                        <signal function="AINP" group="AINP" index="29" pad="PC1"/>
+                        <signal function="AINP" group="AINP" index="30" pad="PC2"/>
+                        <signal function="AINP" group="AINP" index="31" pad="PC3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="bor_lvd_ctrl_avr_v2" name="BOD">
-               <instance name="BOD">
-                  <register-group address-space="data"
-                                  name="BOD"
-                                  name-in-module="BOD"
-                                  offset="0x00A0"/>
-               </instance>
+                <instance name="BOD">
+                    <register-group address-space="data"
+                                    name="BOD"
+                                    name-in-module="BOD"
+                                    offset="0x00A0"/>
+                </instance>
             </module>
             <module id="cla_ccl_v1" name="CCL">
-               <instance name="CCL">
-                  <register-group address-space="data"
-                                  name="CCL"
-                                  name-in-module="CCL"
-                                  offset="0x01C0"/>
-                  <signals>
-                     <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
-                     <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
-                     <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
-                     <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
-                     <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
-                     <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
-                     <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
-                     <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
-                     <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
-                     <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
-                     <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
-                     <signal function="IN" group="LUT3_IN" index="2" pad="PF2"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="ALT1"
-                             group="LUT0_OUT"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT0"
-                             function="DEFAULT"
-                             group="LUT0_OUT"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT1"
-                             function="ALT1"
-                             group="LUT1_OUT"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT1"
-                             function="DEFAULT"
-                             group="LUT1_OUT"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="ALT1"
-                             group="LUT2_OUT"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT2"
-                             function="DEFAULT"
-                             group="LUT2_OUT"
-                             pad="PD3"/>
-                     <signal field="PORTMUX.CCLROUTEA.LUT3"
-                             function="DEFAULT"
-                             group="LUT3_OUT"
-                             pad="PF3"/>
-                  </signals>
-               </instance>
+                <instance name="CCL">
+                    <register-group address-space="data"
+                                    name="CCL"
+                                    name-in-module="CCL"
+                                    offset="0x01C0"/>
+                    <signals>
+                        <signal function="IN" group="LUT0_IN" index="0" pad="PA0"/>
+                        <signal function="IN" group="LUT0_IN" index="1" pad="PA1"/>
+                        <signal function="IN" group="LUT0_IN" index="2" pad="PA2"/>
+                        <signal function="IN" group="LUT1_IN" index="0" pad="PC0"/>
+                        <signal function="IN" group="LUT1_IN" index="1" pad="PC1"/>
+                        <signal function="IN" group="LUT1_IN" index="2" pad="PC2"/>
+                        <signal function="IN" group="LUT2_IN" index="0" pad="PD0"/>
+                        <signal function="IN" group="LUT2_IN" index="1" pad="PD1"/>
+                        <signal function="IN" group="LUT2_IN" index="2" pad="PD2"/>
+                        <signal function="IN" group="LUT3_IN" index="0" pad="PF0"/>
+                        <signal function="IN" group="LUT3_IN" index="1" pad="PF1"/>
+                        <signal function="IN" group="LUT3_IN" index="2" pad="PF2"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="ALT1"
+                                group="LUT0_OUT"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT0"
+                                function="DEFAULT"
+                                group="LUT0_OUT"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="ALT1"
+                                group="LUT1_OUT"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT1"
+                                function="DEFAULT"
+                                group="LUT1_OUT"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="ALT1"
+                                group="LUT2_OUT"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT2"
+                                function="DEFAULT"
+                                group="LUT2_OUT"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.CCLROUTEA.LUT3"
+                                function="DEFAULT"
+                                group="LUT3_OUT"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="CLKCTRL">
-               <instance name="CLKCTRL">
-                  <register-group address-space="data"
-                                  name="CLKCTRL"
-                                  name-in-module="CLKCTRL"
-                                  offset="0x0060"/>
-                  <signals>
-                     <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
-                     <signal function="OUT" group="CLKOUT" pad="PA7"/>
-                     <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
-                     <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
-                     <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
-                     <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
-                  </signals>
-               </instance>
+                <instance name="CLKCTRL">
+                    <register-group address-space="data"
+                                    name="CLKCTRL"
+                                    name-in-module="CLKCTRL"
+                                    offset="0x0060"/>
+                    <signals>
+                        <signal function="EXTCLK" group="EXTCLK" pad="PA0"/>
+                        <signal function="OUT" group="CLKOUT" pad="PA7"/>
+                        <signal function="XTAL" group="XTAL32K" index="1" pad="PF0"/>
+                        <signal function="XTAL" group="XTAL32K" index="2" pad="PF1"/>
+                        <signal function="XTAL" group="XTALHF" index="1" pad="PA0"/>
+                        <signal function="XTAL" group="XTALHF" index="2" pad="PA1"/>
+                    </signals>
+                </instance>
             </module>
             <module id="cpu_avr_xt_v1" name="CPU">
-               <instance name="CPU">
-                  <register-group address-space="data"
-                                  name="CPU"
-                                  name-in-module="CPU"
-                                  offset="0x0030"/>
-                  <parameters>
-                     <param name="CORE_VERSION" value="V4S"/>
-                  </parameters>
-               </instance>
+                <instance name="CPU">
+                    <register-group address-space="data"
+                                    name="CPU"
+                                    name-in-module="CPU"
+                                    offset="0x0030"/>
+                    <parameters>
+                        <param name="CORE_VERSION" value="V4S"/>
+                    </parameters>
+                </instance>
             </module>
             <module id="int_8bit_v3" name="CPUINT">
-               <instance name="CPUINT">
-                  <register-group address-space="data"
-                                  name="CPUINT"
-                                  name-in-module="CPUINT"
-                                  offset="0x0110"/>
-               </instance>
+                <instance name="CPUINT">
+                    <register-group address-space="data"
+                                    name="CPUINT"
+                                    name-in-module="CPUINT"
+                                    offset="0x0110"/>
+                </instance>
             </module>
             <module id="math_pdi_crc_v1" name="CRCSCAN">
-               <instance name="CRCSCAN">
-                  <register-group address-space="data"
-                                  name="CRCSCAN"
-                                  name-in-module="CRCSCAN"
-                                  offset="0x0120"/>
-               </instance>
+                <instance name="CRCSCAN">
+                    <register-group address-space="data"
+                                    name="CRCSCAN"
+                                    name-in-module="CRCSCAN"
+                                    offset="0x0120"/>
+                </instance>
             </module>
             <module id="dac_nbit_ctrl_avr_v6" name="DAC">
-               <instance name="DAC0">
-                  <register-group address-space="data"
-                                  name="DAC0"
-                                  name-in-module="DAC"
-                                  offset="0x06A0"/>
-                  <signals>
-                     <signal function="VOUT" group="OUT" pad="PD6"/>
-                  </signals>
-               </instance>
+                <instance name="DAC0">
+                    <register-group address-space="data"
+                                    name="DAC0"
+                                    name-in-module="DAC"
+                                    offset="0x06A0"/>
+                    <signals>
+                        <signal function="VOUT" group="OUT" pad="PD6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="EVSYS">
-               <instance name="EVSYS">
-                  <register-group address-space="data"
-                                  name="EVSYS"
-                                  name-in-module="EVSYS"
-                                  offset="0x0200"/>
-                  <signals>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="0"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTB"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="1"
-                             pad="PB2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="2"
-                             pad="PC7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="3"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTE"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="4"
-                             pad="PE2"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                             function="ALT1"
-                             group="EVOUT"
-                             index="5"
-                             pad="PF7"/>
-                     <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
-                             function="DEFAULT"
-                             group="EVOUT"
-                             index="5"
-                             pad="PF2"/>
-                  </signals>
-               </instance>
+                <instance name="EVSYS">
+                    <register-group address-space="data"
+                                    name="EVSYS"
+                                    name-in-module="EVSYS"
+                                    offset="0x0200"/>
+                    <signals>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTA"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="0"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTB"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="1"
+                                pad="PB2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTC"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTD"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="3"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTE"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="4"
+                                pad="PE2"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="ALT1"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF7"/>
+                        <signal field="PORTMUX.EVSYSROUTEA.EVOUTF"
+                                function="DEFAULT"
+                                group="EVOUT"
+                                index="5"
+                                pad="PF2"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="FUSE">
-               <instance name="FUSE">
-                  <register-group address-space="data"
-                                  name="FUSE"
-                                  name-in-module="FUSE"
-                                  offset="0x1050"/>
-               </instance>
+                <instance name="FUSE">
+                    <register-group address-space="data"
+                                    name="FUSE"
+                                    name-in-module="FUSE"
+                                    offset="0x1050"/>
+                </instance>
             </module>
             <module id="avrea" name="GPR">
-               <instance name="GPR">
-                  <register-group address-space="data"
-                                  name="GPR"
-                                  name-in-module="GPR"
-                                  offset="0x001C"/>
-               </instance>
+                <instance name="GPR">
+                    <register-group address-space="data"
+                                    name="GPR"
+                                    name-in-module="GPR"
+                                    offset="0x001C"/>
+                </instance>
             </module>
             <module id="avrea" name="LOCK">
-               <instance name="LOCK">
-                  <register-group address-space="data"
-                                  name="LOCK"
-                                  name-in-module="LOCK"
-                                  offset="0x1040"/>
-               </instance>
+                <instance name="LOCK">
+                    <register-group address-space="data"
+                                    name="LOCK"
+                                    name-in-module="LOCK"
+                                    offset="0x1040"/>
+                </instance>
             </module>
             <module id="nvm_ctrl_avr_v3" name="NVMCTRL">
-               <instance name="NVMCTRL">
-                  <register-group address-space="data"
-                                  name="NVMCTRL"
-                                  name-in-module="NVMCTRL"
-                                  offset="0x1000"/>
-               </instance>
+                <instance name="NVMCTRL">
+                    <register-group address-space="data"
+                                    name="NVMCTRL"
+                                    name-in-module="NVMCTRL"
+                                    offset="0x1000"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3" name="PORT">
-               <instance name="PORTA">
-                  <register-group address-space="data"
-                                  name="PORTA"
-                                  name-in-module="PORT"
-                                  offset="0x0400"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTB">
-                  <register-group address-space="data"
-                                  name="PORTB"
-                                  name-in-module="PORT"
-                                  offset="0x0420"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PB0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PB1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PB2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PB3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PB4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PB5"/>
-                  </signals>
-               </instance>
-               <instance name="PORTC">
-                  <register-group address-space="data"
-                                  name="PORTC"
-                                  name-in-module="PORT"
-                                  offset="0x0440"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PC4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PC5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PC6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PC7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTD">
-                  <register-group address-space="data"
-                                  name="PORTD"
-                                  name-in-module="PORT"
-                                  offset="0x0460"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
-                  </signals>
-               </instance>
-               <instance name="PORTE">
-                  <register-group address-space="data"
-                                  name="PORTE"
-                                  name-in-module="PORT"
-                                  offset="0x0480"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PE0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PE1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PE2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PE3"/>
-                  </signals>
-               </instance>
-               <instance name="PORTF">
-                  <register-group address-space="data"
-                                  name="PORTF"
-                                  name-in-module="PORT"
-                                  offset="0x04A0"/>
-                  <signals>
-                     <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
-                     <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
-                     <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
-                     <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
-                     <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
-                     <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
-                     <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
-                     <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
-                  </signals>
-               </instance>
+                <instance name="PORTA">
+                    <register-group address-space="data"
+                                    name="PORTA"
+                                    name-in-module="PORT"
+                                    offset="0x0400"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PA0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PA1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PA2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PA3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PA4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PA5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PA6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PA7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTB">
+                    <register-group address-space="data"
+                                    name="PORTB"
+                                    name-in-module="PORT"
+                                    offset="0x0420"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PB0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PB1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PB2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PB3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PB4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PB5"/>
+                    </signals>
+                </instance>
+                <instance name="PORTC">
+                    <register-group address-space="data"
+                                    name="PORTC"
+                                    name-in-module="PORT"
+                                    offset="0x0440"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PC0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PC1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PC2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PC3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PC4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PC5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PC6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PC7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTD">
+                    <register-group address-space="data"
+                                    name="PORTD"
+                                    name-in-module="PORT"
+                                    offset="0x0460"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PD0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PD1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PD2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PD3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PD4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PD5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PD6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PD7"/>
+                    </signals>
+                </instance>
+                <instance name="PORTE">
+                    <register-group address-space="data"
+                                    name="PORTE"
+                                    name-in-module="PORT"
+                                    offset="0x0480"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PE0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PE1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PE2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PE3"/>
+                    </signals>
+                </instance>
+                <instance name="PORTF">
+                    <register-group address-space="data"
+                                    name="PORTF"
+                                    name-in-module="PORT"
+                                    offset="0x04A0"/>
+                    <signals>
+                        <signal function="IOPORT" group="PIN" index="0" pad="PF0"/>
+                        <signal function="IOPORT" group="PIN" index="1" pad="PF1"/>
+                        <signal function="IOPORT" group="PIN" index="2" pad="PF2"/>
+                        <signal function="IOPORT" group="PIN" index="3" pad="PF3"/>
+                        <signal function="IOPORT" group="PIN" index="4" pad="PF4"/>
+                        <signal function="IOPORT" group="PIN" index="5" pad="PF5"/>
+                        <signal function="IOPORT" group="PIN" index="6" pad="PF6"/>
+                        <signal function="IOPORT" group="PIN" index="7" pad="PF7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="PORTMUX">
-               <instance name="PORTMUX">
-                  <register-group address-space="data"
-                                  name="PORTMUX"
-                                  name-in-module="PORTMUX"
-                                  offset="0x05E0"/>
-               </instance>
+                <instance name="PORTMUX">
+                    <register-group address-space="data"
+                                    name="PORTMUX"
+                                    name-in-module="PORTMUX"
+                                    offset="0x05E0"/>
+                </instance>
             </module>
             <module id="rst_integration_avr_v2" name="RSTCTRL">
-               <instance name="RSTCTRL">
-                  <register-group address-space="data"
-                                  name="RSTCTRL"
-                                  name-in-module="RSTCTRL"
-                                  offset="0x0040"/>
-                  <signals>
-                     <signal function="OTHER" group="RESET" pad="PF6"/>
-                  </signals>
-               </instance>
+                <instance name="RSTCTRL">
+                    <register-group address-space="data"
+                                    name="RSTCTRL"
+                                    name-in-module="RSTCTRL"
+                                    offset="0x0040"/>
+                    <signals>
+                        <signal function="OTHER" group="RESET" pad="PF6"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_rtc_avr_v2" name="RTC">
-               <instance name="RTC">
-                  <register-group address-space="data"
-                                  name="RTC"
-                                  name-in-module="RTC"
-                                  offset="0x0140"/>
-               </instance>
+                <instance name="RTC">
+                    <register-group address-space="data"
+                                    name="RTC"
+                                    name-in-module="RTC"
+                                    offset="0x0140"/>
+                </instance>
             </module>
             <module id="avrea" name="SIGROW">
-               <instance name="SIGROW">
-                  <register-group address-space="data"
-                                  name="SIGROW"
-                                  name-in-module="SIGROW"
-                                  offset="0x1100"/>
-               </instance>
+                <instance name="SIGROW">
+                    <register-group address-space="data"
+                                    name="SIGROW"
+                                    name-in-module="SIGROW"
+                                    offset="0x1100"/>
+                </instance>
             </module>
             <module id="clk_sleep_ctrl_avr_v1" name="SLPCTRL">
-               <instance name="SLPCTRL">
-                  <register-group address-space="data"
-                                  name="SLPCTRL"
-                                  name-in-module="SLPCTRL"
-                                  offset="0x0050"/>
-               </instance>
+                <instance name="SLPCTRL">
+                    <register-group address-space="data"
+                                    name="SLPCTRL"
+                                    name-in-module="SLPCTRL"
+                                    offset="0x0050"/>
+                </instance>
             </module>
             <module id="spi_8bit_v2" name="SPI">
-               <instance name="SPI0">
-                  <register-group address-space="data"
-                                  name="SPI0"
-                                  name-in-module="SPI"
-                                  offset="0x0940"/>
-                  <signals>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT1"
-                             group="MISO"
-                             pad="PE1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT1"
-                             group="MOSI"
-                             pad="PE0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT1"
-                             group="SCK"
-                             pad="PE2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT1"
-                             group="SS"
-                             pad="PE3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MISO"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="MOSI"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SCK"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT3"
-                             group="SS"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MISO"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="MOSI"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SCK"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT4"
-                             group="SS"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="MOSI"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT5"
-                             group="SS"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MISO"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="MOSI"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SCK"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="ALT6"
-                             group="SS"
-                             pad="PF7"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MISO"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="MOSI"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SCK"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.SPIROUTEA.SPI0"
-                             function="DEFAULT"
-                             group="SS"
-                             pad="PA7"/>
-                  </signals>
-               </instance>
+                <instance name="SPI0">
+                    <register-group address-space="data"
+                                    name="SPI0"
+                                    name-in-module="SPI"
+                                    offset="0x0940"/>
+                    <signals>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT1"
+                                group="MISO"
+                                pad="PE1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT1"
+                                group="MOSI"
+                                pad="PE0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT1"
+                                group="SCK"
+                                pad="PE2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT1"
+                                group="SS"
+                                pad="PE3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MISO"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="MOSI"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SCK"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT3"
+                                group="SS"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MISO"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="MOSI"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SCK"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT4"
+                                group="SS"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="MOSI"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT5"
+                                group="SS"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MISO"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="MOSI"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SCK"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="ALT6"
+                                group="SS"
+                                pad="PF7"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MISO"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="MOSI"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SCK"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.SPIROUTEA.SPI0"
+                                function="DEFAULT"
+                                group="SS"
+                                pad="PA7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="SYSCFG">
-               <instance name="SYSCFG">
-                  <register-group address-space="data"
-                                  name="SYSCFG"
-                                  name-in-module="SYSCFG"
-                                  offset="0x0F00"/>
-               </instance>
+                <instance name="SYSCFG">
+                    <register-group address-space="data"
+                                    name="SYSCFG"
+                                    name-in-module="SYSCFG"
+                                    offset="0x0F00"/>
+                </instance>
             </module>
             <module id="tmr_16b_pwm_v1" name="TCA">
-               <instance name="TCA0">
-                  <register-group address-space="data"
-                                  name="TCA0"
-                                  name-in-module="TCA"
-                                  offset="0x0A00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PB0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="1"
-                             pad="PB1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="2"
-                             pad="PB2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="3"
-                             pad="PB3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="4"
-                             pad="PB4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT1"
-                             group="WO"
-                             index="5"
-                             pad="PB5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="1"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="2"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="3"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="4"
-                             pad="PC4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT2"
-                             group="WO"
-                             index="5"
-                             pad="PC5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="0"
-                             pad="PD0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="1"
-                             pad="PD1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="2"
-                             pad="PD2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="3"
-                             pad="PD3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="4"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT3"
-                             group="WO"
-                             index="5"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT4"
-                             group="WO"
-                             index="0"
-                             pad="PE0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT4"
-                             group="WO"
-                             index="1"
-                             pad="PE1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT4"
-                             group="WO"
-                             index="2"
-                             pad="PE2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT4"
-                             group="WO"
-                             index="3"
-                             pad="PE3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="0"
-                             pad="PF0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="1"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="2"
-                             pad="PF2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="3"
-                             pad="PF3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="4"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="ALT5"
-                             group="WO"
-                             index="5"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="1"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="3"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="4"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="5"
-                             pad="PA5"/>
-                  </signals>
-               </instance>
-               <instance name="TCA1">
-                  <register-group address-space="data"
-                                  name="TCA1"
-                                  name-in-module="TCA"
-                                  offset="0x0A40"/>
-                  <signals>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PC4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT1"
-                             group="WO"
-                             index="1"
-                             pad="PC5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT1"
-                             group="WO"
-                             index="2"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT4"
-                             group="WO"
-                             index="0"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT4"
-                             group="WO"
-                             index="1"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT4"
-                             group="WO"
-                             index="2"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT5"
-                             group="WO"
-                             index="0"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT5"
-                             group="WO"
-                             index="1"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="ALT5"
-                             group="WO"
-                             index="2"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PB0"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="1"
-                             pad="PB1"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="2"
-                             pad="PB2"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="3"
-                             pad="PB3"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="4"
-                             pad="PB4"/>
-                     <signal field="PORTMUX.TCAROUTEA.TCA1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="5"
-                             pad="PB5"/>
-                  </signals>
-               </instance>
+                <instance name="TCA0">
+                    <register-group address-space="data"
+                                    name="TCA0"
+                                    name-in-module="TCA"
+                                    offset="0x0A00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PB0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="1"
+                                pad="PB1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="2"
+                                pad="PB2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="3"
+                                pad="PB3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="4"
+                                pad="PB4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT1"
+                                group="WO"
+                                index="5"
+                                pad="PB5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="1"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="2"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="3"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="4"
+                                pad="PC4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT2"
+                                group="WO"
+                                index="5"
+                                pad="PC5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="0"
+                                pad="PD0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="1"
+                                pad="PD1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="2"
+                                pad="PD2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="3"
+                                pad="PD3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="4"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT3"
+                                group="WO"
+                                index="5"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT4"
+                                group="WO"
+                                index="0"
+                                pad="PE0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT4"
+                                group="WO"
+                                index="1"
+                                pad="PE1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT4"
+                                group="WO"
+                                index="2"
+                                pad="PE2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT4"
+                                group="WO"
+                                index="3"
+                                pad="PE3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="2"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="3"
+                                pad="PF3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="4"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="ALT5"
+                                group="WO"
+                                index="5"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="1"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="3"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="4"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="5"
+                                pad="PA5"/>
+                    </signals>
+                </instance>
+                <instance name="TCA1">
+                    <register-group address-space="data"
+                                    name="TCA1"
+                                    name-in-module="TCA"
+                                    offset="0x0A40"/>
+                    <signals>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PC4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT1"
+                                group="WO"
+                                index="1"
+                                pad="PC5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT1"
+                                group="WO"
+                                index="2"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT4"
+                                group="WO"
+                                index="0"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT4"
+                                group="WO"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT4"
+                                group="WO"
+                                index="2"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT5"
+                                group="WO"
+                                index="0"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT5"
+                                group="WO"
+                                index="1"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="ALT5"
+                                group="WO"
+                                index="2"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PB0"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="1"
+                                pad="PB1"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="2"
+                                pad="PB2"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="3"
+                                pad="PB3"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="4"
+                                pad="PB4"/>
+                        <signal field="PORTMUX.TCAROUTEA.TCA1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="5"
+                                pad="PB5"/>
+                    </signals>
+                </instance>
             </module>
             <module id="tmr_16b_capture_v1" name="TCB">
-               <instance name="TCB0">
-                  <register-group address-space="data"
-                                  name="TCB0"
-                                  name-in-module="TCB"
-                                  offset="0x0B00"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB0"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB0"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA2"/>
-                  </signals>
-               </instance>
-               <instance name="TCB1">
-                  <register-group address-space="data"
-                                  name="TCB1"
-                                  name-in-module="TCB"
-                                  offset="0x0B10"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB1"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB1"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="TCB2">
-                  <register-group address-space="data"
-                                  name="TCB2"
-                                  name-in-module="TCB"
-                                  offset="0x0B20"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB2"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PB4"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB2"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PC0"/>
-                  </signals>
-               </instance>
-               <instance name="TCB3">
-                  <register-group address-space="data"
-                                  name="TCB3"
-                                  name-in-module="TCB"
-                                  offset="0x0B30"/>
-                  <signals>
-                     <signal field="PORTMUX.TCBROUTEA.TCB3"
-                             function="ALT1"
-                             group="WO"
-                             index="0"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.TCBROUTEA.TCB3"
-                             function="DEFAULT"
-                             group="WO"
-                             index="0"
-                             pad="PB5"/>
-                  </signals>
-               </instance>
+                <instance name="TCB0">
+                    <register-group address-space="data"
+                                    name="TCB0"
+                                    name-in-module="TCB"
+                                    offset="0x0B00"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB0"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA2"/>
+                    </signals>
+                </instance>
+                <instance name="TCB1">
+                    <register-group address-space="data"
+                                    name="TCB1"
+                                    name-in-module="TCB"
+                                    offset="0x0B10"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB1"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="TCB2">
+                    <register-group address-space="data"
+                                    name="TCB2"
+                                    name-in-module="TCB"
+                                    offset="0x0B20"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PB4"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB2"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PC0"/>
+                    </signals>
+                </instance>
+                <instance name="TCB3">
+                    <register-group address-space="data"
+                                    name="TCB3"
+                                    name-in-module="TCB"
+                                    offset="0x0B30"/>
+                    <signals>
+                        <signal field="PORTMUX.TCBROUTEA.TCB3"
+                                function="ALT1"
+                                group="WO"
+                                index="0"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.TCBROUTEA.TCB3"
+                                function="DEFAULT"
+                                group="WO"
+                                index="0"
+                                pad="PB5"/>
+                    </signals>
+                </instance>
             </module>
             <module id="i2c_8bit_avr_v3" name="TWI">
-               <instance name="TWI0">
-                  <register-group address-space="data"
-                                  name="TWI0"
-                                  name-in-module="TWI"
-                                  offset="0x0900"/>
-                  <signals>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SCL_DUAL"
-                             pad="PC7"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT1"
-                             group="SDA_DUAL"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SCL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SCL_DUAL"
-                             pad="PC7"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SDA"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT2"
-                             group="SDA_DUAL"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="ALT3"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SCL_DUAL"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.TWIROUTEA.TWI0"
-                             function="DEFAULT"
-                             group="SDA_DUAL"
-                             pad="PC2"/>
-                  </signals>
-               </instance>
+                <instance name="TWI0">
+                    <register-group address-space="data"
+                                    name="TWI0"
+                                    name-in-module="TWI"
+                                    offset="0x0900"/>
+                    <signals>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SCL_DUAL"
+                                pad="PC7"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT1"
+                                group="SDA_DUAL"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SCL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SCL_DUAL"
+                                pad="PC7"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SDA"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT2"
+                                group="SDA_DUAL"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="ALT3"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SCL_DUAL"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.TWIROUTEA.TWI0"
+                                function="DEFAULT"
+                                group="SDA_DUAL"
+                                pad="PC2"/>
+                    </signals>
+                </instance>
             </module>
             <module id="uart_autobd_v4" name="USART">
-               <instance name="USART0">
-                  <register-group address-space="data"
-                                  name="USART0"
-                                  name-in-module="USART"
-                                  offset="0x0800"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="RXD"
-                             index="1"
-                             pad="PA5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="TXD"
-                             index="1"
-                             pad="PA4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XCK"
-                             index="1"
-                             pad="PA6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT1"
-                             group="XDIR"
-                             index="1"
-                             pad="PA7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="RXD"
-                             index="2"
-                             pad="PA3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT2"
-                             group="TXD"
-                             index="2"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="RXD"
-                             index="3"
-                             pad="PD5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="TXD"
-                             index="3"
-                             pad="PD4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XCK"
-                             index="3"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT3"
-                             group="XDIR"
-                             index="3"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="RXD"
-                             index="4"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="TXD"
-                             index="4"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="ALT4"
-                             group="XCK"
-                             index="4"
-                             pad="PC3"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PA1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PA0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PA2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART0"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PA3"/>
-                  </signals>
-               </instance>
-               <instance name="USART1">
-                  <register-group address-space="data"
-                                  name="USART1"
-                                  name-in-module="USART"
-                                  offset="0x0820"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT1"
-                             group="RXD"
-                             pad="PC5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT1"
-                             group="TXD"
-                             pad="PC4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT1"
-                             group="XCK"
-                             pad="PC6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT1"
-                             group="XDIR"
-                             pad="PC7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="RXD"
-                             pad="PD7"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="ALT2"
-                             group="TXD"
-                             pad="PD6"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PC1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PC0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PC2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART1"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PC3"/>
-                  </signals>
-               </instance>
-               <instance name="USART2">
-                  <register-group address-space="data"
-                                  name="USART2"
-                                  name-in-module="USART"
-                                  offset="0x0840"/>
-                  <signals>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="ALT1"
-                             group="RXD"
-                             pad="PF5"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="ALT1"
-                             group="TXD"
-                             pad="PF4"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="RXD"
-                             pad="PF1"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="TXD"
-                             pad="PF0"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="XCK"
-                             pad="PF2"/>
-                     <signal field="PORTMUX.USARTROUTEA.USART2"
-                             function="DEFAULT"
-                             group="XDIR"
-                             pad="PF3"/>
-                  </signals>
-               </instance>
+                <instance name="USART0">
+                    <register-group address-space="data"
+                                    name="USART0"
+                                    name-in-module="USART"
+                                    offset="0x0800"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="RXD"
+                                index="1"
+                                pad="PA5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="TXD"
+                                index="1"
+                                pad="PA4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XCK"
+                                index="1"
+                                pad="PA6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT1"
+                                group="XDIR"
+                                index="1"
+                                pad="PA7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="RXD"
+                                index="2"
+                                pad="PA3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT2"
+                                group="TXD"
+                                index="2"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="RXD"
+                                index="3"
+                                pad="PD5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="TXD"
+                                index="3"
+                                pad="PD4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XCK"
+                                index="3"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT3"
+                                group="XDIR"
+                                index="3"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="RXD"
+                                index="4"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="TXD"
+                                index="4"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="ALT4"
+                                group="XCK"
+                                index="4"
+                                pad="PC3"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PA1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PA0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PA2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART0"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PA3"/>
+                    </signals>
+                </instance>
+                <instance name="USART1">
+                    <register-group address-space="data"
+                                    name="USART1"
+                                    name-in-module="USART"
+                                    offset="0x0820"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT1"
+                                group="RXD"
+                                pad="PC5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT1"
+                                group="TXD"
+                                pad="PC4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT1"
+                                group="XCK"
+                                pad="PC6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT1"
+                                group="XDIR"
+                                pad="PC7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="RXD"
+                                pad="PD7"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="ALT2"
+                                group="TXD"
+                                pad="PD6"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PC1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PC0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PC2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART1"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PC3"/>
+                    </signals>
+                </instance>
+                <instance name="USART2">
+                    <register-group address-space="data"
+                                    name="USART2"
+                                    name-in-module="USART"
+                                    offset="0x0840"/>
+                    <signals>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="ALT1"
+                                group="RXD"
+                                pad="PF5"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="ALT1"
+                                group="TXD"
+                                pad="PF4"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="RXD"
+                                pad="PF1"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="TXD"
+                                pad="PF0"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="XCK"
+                                pad="PF2"/>
+                        <signal field="PORTMUX.USARTROUTEA.USART2"
+                                function="DEFAULT"
+                                group="XDIR"
+                                pad="PF3"/>
+                    </signals>
+                </instance>
             </module>
             <module id="avrea" name="USERROW">
-               <instance name="USERROW">
-                  <register-group address-space="data"
-                                  name="USERROW"
-                                  name-in-module="USERROW"
-                                  offset="0x1080"/>
-               </instance>
+                <instance name="USERROW">
+                    <register-group address-space="data"
+                                    name="USERROW"
+                                    name-in-module="USERROW"
+                                    offset="0x1080"/>
+                </instance>
             </module>
             <module id="gpio_ports_avr_v3_vport" name="VPORT">
-               <instance name="VPORTA">
-                  <register-group address-space="data"
-                                  name="VPORTA"
-                                  name-in-module="VPORT"
-                                  offset="0x0000"/>
-               </instance>
-               <instance name="VPORTB">
-                  <register-group address-space="data"
-                                  name="VPORTB"
-                                  name-in-module="VPORT"
-                                  offset="0x0004"/>
-               </instance>
-               <instance name="VPORTC">
-                  <register-group address-space="data"
-                                  name="VPORTC"
-                                  name-in-module="VPORT"
-                                  offset="0x0008"/>
-               </instance>
-               <instance name="VPORTD">
-                  <register-group address-space="data"
-                                  name="VPORTD"
-                                  name-in-module="VPORT"
-                                  offset="0x000C"/>
-               </instance>
-               <instance name="VPORTE">
-                  <register-group address-space="data"
-                                  name="VPORTE"
-                                  name-in-module="VPORT"
-                                  offset="0x0010"/>
-               </instance>
-               <instance name="VPORTF">
-                  <register-group address-space="data"
-                                  name="VPORTF"
-                                  name-in-module="VPORT"
-                                  offset="0x0014"/>
-               </instance>
+                <instance name="VPORTA">
+                    <register-group address-space="data"
+                                    name="VPORTA"
+                                    name-in-module="VPORT"
+                                    offset="0x0000"/>
+                </instance>
+                <instance name="VPORTB">
+                    <register-group address-space="data"
+                                    name="VPORTB"
+                                    name-in-module="VPORT"
+                                    offset="0x0004"/>
+                </instance>
+                <instance name="VPORTC">
+                    <register-group address-space="data"
+                                    name="VPORTC"
+                                    name-in-module="VPORT"
+                                    offset="0x0008"/>
+                </instance>
+                <instance name="VPORTD">
+                    <register-group address-space="data"
+                                    name="VPORTD"
+                                    name-in-module="VPORT"
+                                    offset="0x000C"/>
+                </instance>
+                <instance name="VPORTE">
+                    <register-group address-space="data"
+                                    name="VPORTE"
+                                    name-in-module="VPORT"
+                                    offset="0x0010"/>
+                </instance>
+                <instance name="VPORTF">
+                    <register-group address-space="data"
+                                    name="VPORTF"
+                                    name-in-module="VPORT"
+                                    offset="0x0014"/>
+                </instance>
             </module>
             <module id="avrea" name="VREF">
-               <instance name="VREF">
-                  <register-group address-space="data"
-                                  name="VREF"
-                                  name-in-module="VREF"
-                                  offset="0x00B0"/>
-                  <signals>
-                     <signal function="VREF" group="VREFA" pad="PD7"/>
-                  </signals>
-               </instance>
+                <instance name="VREF">
+                    <register-group address-space="data"
+                                    name="VREF"
+                                    name-in-module="VREF"
+                                    offset="0x00B0"/>
+                    <signals>
+                        <signal function="VREF" group="VREFA" pad="PD7"/>
+                    </signals>
+                </instance>
             </module>
             <module id="wdt_windowed_v2" name="WDT">
-               <instance name="WDT">
-                  <register-group address-space="data"
-                                  name="WDT"
-                                  name-in-module="WDT"
-                                  offset="0x0100"/>
-               </instance>
+                <instance name="WDT">
+                    <register-group address-space="data"
+                                    name="WDT"
+                                    name-in-module="WDT"
+                                    offset="0x0100"/>
+                </instance>
             </module>
-         </peripherals>
-         <interrupts>
+        </peripherals>
+        <interrupts>
             <interrupt index="1" module-instance="CRCSCAN" name="NMI"/>
             <interrupt index="2" module-instance="BOD" name="VLM"/>
             <interrupt index="3" module-instance="CLKCTRL" name="CFD"/>
@@ -1381,5557 +1381,5557 @@
             <interrupt index="42" module-instance="TCA1" name="LCMP2"/>
             <interrupt index="43" module-instance="PORTE" name="PORT"/>
             <interrupt index="44" module-instance="PORTB" name="PORT"/>
-         </interrupts>
-         <interfaces>
+        </interrupts>
+        <interfaces>
             <interface name="UPDI" type="updi"/>
-         </interfaces>
-         <property-groups>
+        </interfaces>
+        <property-groups>
             <property-group name="PROGRAMMING_INFO">
-               <property name="FUSE_ENABLED_VALUE" value="1"/>
+                <property name="FUSE_ENABLED_VALUE" value="1"/>
             </property-group>
             <property-group name="UPDI_INTERFACE">
-               <property name="OCD_BASE_ADDR" value="0x00000F80"/>
-               <property name="HV_IMPLEMENTATION" value="2"/>
-               <property name="PROGMEM_OFFSET" value="0x00800000"/>
+                <property name="OCD_BASE_ADDR" value="0x00000F80"/>
+                <property name="HV_IMPLEMENTATION" value="2"/>
+                <property name="PROGMEM_OFFSET" value="0x00800000"/>
             </property-group>
             <property-group name="SIGNATURES">
-               <property name="SIGNATURE0" value="0x1E"/>
-               <property name="SIGNATURE1" value="0x96"/>
-               <property name="SIGNATURE2" value="0x1E"/>
+                <property name="SIGNATURE0" value="0x1E"/>
+                <property name="SIGNATURE1" value="0x96"/>
+                <property name="SIGNATURE2" value="0x1E"/>
             </property-group>
-         </property-groups>
-      </device>
-   <modules>
-      <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
-         <register-group caption="Analog Comparator" name="AC" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Hysteresis Mode"
-                         mask="0x06"
-                         name="HYSMODE"
-                         rw="RW"
-                         values="AC_HYSMODE"/>
-               <bitfield caption="Power profile"
-                         mask="0x18"
-                         name="POWER"
-                         rw="RW"
-                         values="AC_POWER"/>
-               <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window selection mode"
-                         mask="0x03"
-                         name="WINSEL"
-                         rw="RW"
-                         values="AC_WINSEL"/>
-            </register>
-            <register caption="Mux Control A"
-                      initval="0x00"
-                      name="MUXCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Negative Input MUX Selection"
-                         mask="0x07"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="AC_MUXNEG"/>
-               <bitfield caption="Positive Input MUX Selection"
-                         mask="0x38"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="AC_MUXPOS"/>
-               <bitfield caption="AC Output Initial Value"
-                         mask="0x40"
-                         name="INITVAL"
-                         rw="RW"
-                         values="AC_INITVAL"/>
-               <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
-            </register>
-            <register caption="DAC Voltage Reference"
-                      initval="0xFF"
-                      name="DACREF"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
-               <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_NORMAL_INTMODE"/>
-               <bitfield caption="Interrupt Mode"
-                         mask="0x30"
-                         modes="WINDOW"
-                         name="INTMODE"
-                         rw="RW"
-                         values="AC_WINDOW_INTMODE"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator Interrupt Flag"
-                         mask="0x01"
-                         name="CMPIF"
-                         rw="RW"/>
-               <bitfield caption="Analog Comparator State"
-                         mask="0x10"
-                         name="CMPSTATE"
-                         rw="R"/>
-               <bitfield caption="Analog Comparator Window State"
-                         mask="0xC0"
-                         name="WINSTATE"
-                         rw="R"
-                         values="AC_WINSTATE"/>
-            </register>
-         </register-group>
-         <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
-            <value caption="No hysteresis" name="NONE" value="0x00"/>
-            <value caption="Small hysteresis" name="SMALL" value="0x01"/>
-            <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
-            <value caption="Large hysteresis" name="LARGE" value="0x03"/>
-         </value-group>
-         <value-group caption="Power profile select" name="AC_POWER">
-            <value caption="Power profile 0, Fastest response time, highest consumption"
-                   name="PROFILE0"
-                   value="0x0"/>
-            <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
-         </value-group>
-         <value-group caption="Window selection mode" name="AC_WINSEL">
-            <value caption="Window function disabled" name="DISABLED" value="0x0"/>
-            <value caption="Select ACn+1 as upper limit in window compare"
-                   name="UPSEL1"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
-            <value caption="Positive and negative inputs crosses"
-                   name="BOTHEDGE"
-                   value="0x0"/>
-            <value caption="Positive input goes below negative input"
-                   name="NEGEDGE"
-                   value="0x2"/>
-            <value caption="Positive input goes above negative input"
-                   name="POSEDGE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
-            <value caption="Window interrupt when input above both references"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="Window interrupt when input betweeen references"
-                   name="INSIDE"
-                   value="0x1"/>
-            <value caption="Window interrupt when input below both references"
-                   name="BELOW"
-                   value="0x2"/>
-            <value caption="Window interrupt when input outside reference"
-                   name="OUTSIDE"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
-            <value caption="Output initialized to 0" name="LOW" value="0x0"/>
-            <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
-         </value-group>
-         <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
-            <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
-            <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
-            <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
-            <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
-            <value caption="DAC Reference" name="DACREF" value="0x04"/>
-         </value-group>
-         <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
-            <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
-            <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
-            <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
-            <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
-            <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
-         </value-group>
-         <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
-            <value caption="Above window" name="ABOVE" value="0x0"/>
-            <value caption="Inside window" name="INSIDE" value="0x1"/>
-            <value caption="Below window" name="BELOW" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Analog to Digital Converter"
-              id="adc_12b_diff_ctrl_avr_v2"
-              name="ADC">
-         <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler Value"
-                         mask="0x0F"
-                         name="PRESC"
-                         rw="RW"
-                         values="ADC_PRESC"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="ADC_REFSEL"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Window Comparator Mode"
-                         mask="0x07"
-                         name="WINCM"
-                         rw="RW"
-                         values="ADC_WINCM"/>
-               <bitfield caption="Window Mode Source"
-                         mask="0x08"
-                         name="WINSRC"
-                         rw="RW"
-                         values="ADC_WINSRC"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Enable"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Enable"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Enable"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Enable"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Enable"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Enable"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Result Ready Interrupt Flag"
-                         mask="0x01"
-                         name="RESRDY"
-                         rw="RW"/>
-               <bitfield caption="Sample Ready Interrupt Flag"
-                         mask="0x02"
-                         name="SAMPRDY"
-                         rw="RW"/>
-               <bitfield caption="Window Comparator Interrupt Flag"
-                         mask="0x04"
-                         name="WCMP"
-                         rw="RW"/>
-               <bitfield caption="Result Overwrite Interrupt Flag"
-                         mask="0x08"
-                         name="RESOVR"
-                         rw="RW"/>
-               <bitfield caption="Sample Overwrite Interrupt Flag"
-                         mask="0x10"
-                         name="SAMPOVR"
-                         rw="RW"/>
-               <bitfield caption="Trigger Overrun Interrupt Flag"
-                         mask="0x20"
-                         name="TRIGOVR"
-                         rw="RW"/>
-            </register>
-            <register caption="Status register"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Control E"
-                      initval="0x00"
-                      name="CTRLE"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
-            </register>
-            <register caption="Control F"
-                      initval="0x00"
-                      name="CTRLF"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sample numbers"
-                         mask="0x0F"
-                         name="SAMPNUM"
-                         rw="RW"
-                         values="ADC_SAMPNUM"/>
-               <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
-               <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
-               <bitfield caption="Sign Chopping"
-                         mask="0x40"
-                         name="CHOPPING"
-                         rw="RW"
-                         values="ADC_CHOPPING"/>
-            </register>
-            <register caption="Command register"
-                      initval="0x00"
-                      name="COMMAND"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Start command"
-                         mask="0x07"
-                         name="START"
-                         rw="RW"
-                         values="ADC_START"/>
-               <bitfield caption="Mode"
-                         mask="0x70"
-                         name="MODE"
-                         rw="RW"
-                         values="ADC_MODE"/>
-               <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
-            </register>
-            <register caption="PGA Control"
-                      initval="0x00"
-                      name="PGACTRL"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
-               <bitfield caption="PGA BIAS Select"
-                         mask="0x18"
-                         name="PGABIASSEL"
-                         rw="RW"
-                         values="ADC_PGABIASSEL"/>
-               <bitfield caption="Gain"
-                         mask="0xE0"
-                         name="GAIN"
-                         rw="RW"
-                         values="ADC_GAIN"/>
-            </register>
-            <register caption="Positive Input Multiplexer"
-                      initval="0x00"
-                      name="MUXPOS"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXPOS"
-                         rw="RW"
-                         values="ADC_MUXPOS"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Negative Input Multiplexer"
-                      initval="0x00"
-                      name="MUXNEG"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Channel Selection Bits"
-                         mask="0x3F"
-                         name="MUXNEG"
-                         rw="RW"
-                         values="ADC_MUXNEG"/>
-               <bitfield caption="VIA"
-                         mask="0xC0"
-                         name="VIA"
-                         rw="RW"
-                         values="ADC_VIA"/>
-            </register>
-            <register caption="Result"
-                      initval="0x00000000"
-                      name="RESULT"
-                      offset="0x10"
-                      rw="R"
-                      size="4"/>
-            <register caption="Sample"
-                      initval="0x0000"
-                      name="SAMPLE"
-                      offset="0x14"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temporary Data 0"
-                      initval="0x00"
-                      name="TEMP0"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 1"
-                      initval="0x00"
-                      name="TEMP1"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Temporary Data 2"
-                      initval="0x00"
-                      name="TEMP2"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Window Low Threshold"
-                      initval="0x0000"
-                      name="WINLT"
-                      offset="0x1C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Window High Threshold"
-                      initval="0x0000"
-                      name="WINHT"
-                      offset="0x1E"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Mode select" name="ADC_MODE">
-            <value caption="Single Conversion with 8-bit resolution"
-                   name="SINGLE_8BIT"
-                   value="0x00"/>
-            <value caption="Single Conversion with 12-bit resolution"
-                   name="SINGLE_12BIT"
-                   value="0x01"/>
-            <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
-                   name="SERIES"
-                   value="0x02"/>
-            <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
-                   name="SERIES_SCALING"
-                   value="0x03"/>
-            <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST"
-                   value="0x04"/>
-            <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
-                   name="BURST_SCALING"
-                   value="0x05"/>
-         </value-group>
-         <value-group caption="Start command select" name="ADC_START">
-            <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
-            <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
-                   name="IMMEDIATE"
-                   value="0x01"/>
-            <value caption="Start when MUXPOS register is written"
-                   name="MUXPOS_WRITE"
-                   value="0x02"/>
-            <value caption="Start when MUXNEG register is written"
-                   name="MUXNEG_WRITE"
-                   value="0x03"/>
-            <value caption="Start when an event is received"
-                   name="EVENT_TRIGGER"
-                   value="0x04"/>
-         </value-group>
-         <value-group caption="Prescaler Value select" name="ADC_PRESC">
-            <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
-            <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
-            <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
-            <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
-            <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
-            <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
-            <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
-            <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
-            <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
-            <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
-            <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
-            <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
-            <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
-            <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
-            <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
-            <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
-         </value-group>
-         <value-group caption="Reference select" name="ADC_REFSEL">
-            <value caption="VDD" name="VDD" value="0x00"/>
-            <value caption="External Reference" name="VREFA" value="0x02"/>
-            <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
-            <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
-            <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
-            <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
-         </value-group>
-         <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
-            <value caption="No Window Comparison" name="NONE" value="0x00"/>
-            <value caption="Below Window" name="BELOW" value="0x01"/>
-            <value caption="Above Window" name="ABOVE" value="0x02"/>
-            <value caption="Inside Window" name="INSIDE" value="0x03"/>
-            <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
-         </value-group>
-         <value-group caption="Window Mode Source select" name="ADC_WINSRC">
-            <value caption="Result register used as Window Comparator Source"
-                   name="RESULT"
-                   value="0x0"/>
-            <value caption="Sample register used as Window Comparator Source"
-                   name="SAMPLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
-            <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
-            <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
-            <value caption="No accumulation" name="NONE" value="0x0"/>
-            <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
-            <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
-            <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
-            <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
-            <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
-            <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
-            <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
-            <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
-            <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
-            <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 8" name="AIN8" value="0x08"/>
-            <value caption="ADC input pin 9" name="AIN9" value="0x09"/>
-            <value caption="ADC input pin 10" name="AIN10" value="0x0A"/>
-            <value caption="ADC input pin 11" name="AIN11" value="0x0B"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-            <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
-            <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
-         </value-group>
-         <value-group caption="VIA select" name="ADC_VIA">
-            <value caption="Inputs connected directly to ADC"
-                   name="DIRECT"
-                   value="0x0"/>
-            <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
-         </value-group>
-         <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
-            <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
-            <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
-            <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
-            <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
-            <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
-            <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
-            <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
-            <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
-            <value caption="ADC input pin 8" name="AIN8" value="0x08"/>
-            <value caption="ADC input pin 9" name="AIN9" value="0x09"/>
-            <value caption="ADC input pin 10" name="AIN10" value="0x0A"/>
-            <value caption="ADC input pin 11" name="AIN11" value="0x0B"/>
-            <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
-            <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
-            <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
-            <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
-            <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
-            <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
-            <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
-            <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
-            <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
-            <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
-            <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
-            <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
-            <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
-            <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
-            <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
-            <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
-            <value caption="Ground" name="GND" value="0x30"/>
-            <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
-            <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
-            <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
-         </value-group>
-         <value-group caption="Gain select" name="ADC_GAIN">
-            <value caption="1x gain" name="1X" value="0x0"/>
-            <value caption="2x gain" name="2X" value="0x1"/>
-            <value caption="4x gain" name="4X" value="0x2"/>
-            <value caption="8x gain" name="8X" value="0x3"/>
-            <value caption="16x gain" name="16X" value="0x4"/>
-         </value-group>
-         <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
-            <value caption="100% BIAS current." name="100PCT" value="0x0"/>
-            <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
-                   name="75PCT"
-                   value="0x1"/>
-            <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
-                   name="50PCT"
-                   value="0x2"/>
-            <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
-                   name="25PCT"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
-         <register-group caption="Bod interface" name="BOD" size="0x10">
-            <register caption="Control A"
-                      initval="0x01"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Operation in sleep mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="BOD_SLEEP"/>
-               <bitfield caption="Operation in active mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="R"
-                         values="BOD_ACTIVE"/>
-               <bitfield caption="Sample frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="R"
-                         values="BOD_SAMPFREQ"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bod level"
-                         mask="0x07"
-                         name="LVL"
-                         rw="R"
-                         values="BOD_LVL"/>
-            </register>
-            <register caption="Voltage level monitor Control"
-                      initval="0x00"
-                      name="VLMCTRLA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor level"
-                         mask="0x03"
-                         name="VLMLVL"
-                         rw="RW"
-                         values="BOD_VLMLVL"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="voltage level monitor interrrupt enable"
-                         mask="0x01"
-                         name="VLMIE"
-                         rw="RW"/>
-               <bitfield caption="Configuration"
-                         mask="0x06"
-                         name="VLMCFG"
-                         rw="RW"
-                         values="BOD_VLMCFG"/>
-            </register>
-            <register caption="Voltage level monitor interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor interrupt flag"
-                         mask="0x01"
-                         name="VLMIF"
-                         rw="RW"/>
-            </register>
-            <register caption="Voltage level monitor status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Voltage level monitor status"
-                         mask="0x01"
-                         name="VLMS"
-                         rw="R"
-                         values="BOD_VLMS"/>
-            </register>
-         </register-group>
-         <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="Bod level select" name="BOD_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="Configuration select" name="BOD_VLMCFG">
-            <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
-            <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
-            <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
-         </value-group>
-         <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
-            <value caption="The voltage is above the VLM threshold level"
-                   name="ABOVE"
-                   value="0x0"/>
-            <value caption="The voltage is below the VLM threshold level"
-                   name="BELOW"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
-            <value caption="VLM Disabled" name="OFF" value="0x0"/>
-            <value caption="VLM threshold 5% above BOD level"
-                   name="5ABOVE"
-                   value="0x1"/>
-            <value caption="VLM threshold 15% above BOD level"
-                   name="15ABOVE"
-                   value="0x2"/>
-            <value caption="VLM threshold 25% above BOD level"
-                   name="25ABOVE"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
-         <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Sequential Control 0"
-                      initval="0x00"
-                      name="SEQCTRL0"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Sequential Control 1"
-                      initval="0x00"
-                      name="SEQCTRL1"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sequential Selection"
-                         mask="0x07"
-                         name="SEQSEL"
-                         rw="RW"
-                         values="CCL_SEQSEL"/>
-            </register>
-            <register caption="Interrupt Control 0"
-                      initval="0x00"
-                      name="INTCTRL0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Mode for LUT0"
-                         mask="0x03"
-                         name="INTMODE0"
-                         rw="RW"
-                         values="CCL_INTMODE0"/>
-               <bitfield caption="Interrupt Mode for LUT1"
-                         mask="0x0C"
-                         name="INTMODE1"
-                         rw="RW"
-                         values="CCL_INTMODE1"/>
-               <bitfield caption="Interrupt Mode for LUT2"
-                         mask="0x30"
-                         name="INTMODE2"
-                         rw="RW"
-                         values="CCL_INTMODE2"/>
-               <bitfield caption="Interrupt Mode for LUT3"
-                         mask="0xC0"
-                         name="INTMODE3"
-                         rw="RW"
-                         values="CCL_INTMODE3"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
-            </register>
-            <register caption="LUT 0 Control A"
-                      initval="0x00"
-                      name="LUT0CTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 0 Control B"
-                      initval="0x00"
-                      name="LUT0CTRLB"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 0 Control C"
-                      initval="0x00"
-                      name="LUT0CTRLC"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 0"
-                      initval="0x00"
-                      name="TRUTH0"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 1 Control A"
-                      initval="0x00"
-                      name="LUT1CTRLA"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 1 Control B"
-                      initval="0x00"
-                      name="LUT1CTRLB"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 1 Control C"
-                      initval="0x00"
-                      name="LUT1CTRLC"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 1"
-                      initval="0x00"
-                      name="TRUTH1"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 2 Control A"
-                      initval="0x00"
-                      name="LUT2CTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 2 Control B"
-                      initval="0x00"
-                      name="LUT2CTRLB"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 2 Control C"
-                      initval="0x00"
-                      name="LUT2CTRLC"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 2"
-                      initval="0x00"
-                      name="TRUTH2"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-            <register caption="LUT 3 Control A"
-                      initval="0x00"
-                      name="LUT3CTRLA"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Source Selection"
-                         mask="0x0E"
-                         name="CLKSRC"
-                         rw="RW"
-                         values="CCL_CLKSRC"/>
-               <bitfield caption="Filter Selection"
-                         mask="0x30"
-                         name="FILTSEL"
-                         rw="RW"
-                         values="CCL_FILTSEL"/>
-               <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Edge Detection Enable"
-                         mask="0x80"
-                         name="EDGEDET"
-                         rw="RW"
-                         values="CCL_EDGEDET"/>
-            </register>
-            <register caption="LUT 3 Control B"
-                      initval="0x00"
-                      name="LUT3CTRLB"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 0 Source Selection"
-                         mask="0x0F"
-                         name="INSEL0"
-                         rw="RW"
-                         values="CCL_INSEL0"/>
-               <bitfield caption="LUT Input 1 Source Selection"
-                         mask="0xF0"
-                         name="INSEL1"
-                         rw="RW"
-                         values="CCL_INSEL1"/>
-            </register>
-            <register caption="LUT 3 Control C"
-                      initval="0x00"
-                      name="LUT3CTRLC"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="LUT Input 2 Source Selection"
-                         mask="0x0F"
-                         name="INSEL2"
-                         rw="RW"
-                         values="CCL_INSEL2"/>
-            </register>
-            <register caption="Truth 3"
-                      initval="0x00"
-                      name="TRUTH3"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
-            <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
-            <value caption="Sense rising edge" name="RISING" value="0x1"/>
-            <value caption="Sense falling edge" name="FALLING" value="0x2"/>
-            <value caption="Sense both edges" name="BOTH" value="0x3"/>
-         </value-group>
-         <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
-            <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
-            <value caption="INSEL2 selection" name="IN2" value="0x1"/>
-            <value caption="Internal High Frequency oscillator"
-                   name="OSCHF"
-                   value="0x4"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
-            <value caption="Internal 32.768 kHz oscillator divided by 32"
-                   name="OSC1K"
-                   value="0x6"/>
-         </value-group>
-         <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
-            <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
-            <value caption="Edge detector is enabled" name="EN" value="0x1"/>
-         </value-group>
-         <value-group caption="Filter Selection" name="CCL_FILTSEL">
-            <value caption="Filter disabled" name="DISABLE" value="0x0"/>
-            <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
-            <value caption="Filter enabled" name="FILTER" value="0x2"/>
-         </value-group>
-         <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC0 output input source" name="AC0" value="0x6"/>
-            <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
-         </value-group>
-         <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
-            <value caption="Masked input" name="MASK" value="0x0"/>
-            <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
-            <value caption="Output from LUT[n+1] as input source"
-                   name="LINK"
-                   value="0x2"/>
-            <value caption="Event A as input source" name="EVENTA" value="0x3"/>
-            <value caption="Event B as input source" name="EVENTB" value="0x4"/>
-            <value caption="IN0 input source" name="IO" value="0x5"/>
-            <value caption="AC1 output input source" name="AC1" value="0x6"/>
-            <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
-            <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
-            <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
-            <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
-            <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
-         </value-group>
-         <value-group caption="Sequential Selection" name="CCL_SEQSEL">
-            <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
-            <value caption="D FlipFlop" name="DFF" value="0x01"/>
-            <value caption="JK FlipFlop" name="JK" value="0x02"/>
-            <value caption="D Latch" name="LATCH" value="0x03"/>
-            <value caption="RS Latch" name="RS" value="0x04"/>
-         </value-group>
-      </module>
-      <module caption="Clock controller" id="avrea" name="CLKCTRL">
-         <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
-            <register caption="MCLK Control A"
-                      initval="0x00"
-                      name="MCLKCTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock select"
-                         mask="0x07"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="CLKCTRL_CLKSEL"/>
-               <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
-            </register>
-            <register caption="MCLK Control B"
-                      initval="0x11"
-                      name="MCLKCTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
-               <bitfield caption="Prescaler division"
-                         mask="0x1E"
-                         name="PDIV"
-                         rw="RW"
-                         values="CLKCTRL_PDIV"/>
-            </register>
-            <register caption="MCLK Control C"
-                      initval="0x00"
-                      name="MCLKCTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detect Enable"
-                         mask="0x01"
-                         name="CFDEN"
-                         rw="RW"/>
-               <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
-               <bitfield caption="CFD Source"
-                         mask="0x0C"
-                         name="CFDSRC"
-                         rw="RW"
-                         values="CLKCTRL_CFDSRC"/>
-            </register>
-            <register caption="MCLK Interrupt Control"
-                      initval="0x00"
-                      name="MCLKINTCTRL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
-               <bitfield caption="Interrupt Type"
-                         mask="0x80"
-                         name="INTTYPE"
-                         rw="RW"
-                         values="CLKCTRL_INTTYPE"/>
-            </register>
-            <register caption="MCLK Interrupt Flags"
-                      initval="0x00"
-                      name="MCLKINTFLAGS"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
-            </register>
-            <register caption="MCLK Status"
-                      initval="0x00"
-                      name="MCLKSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="System Oscillator changing"
-                         mask="0x01"
-                         name="SOSC"
-                         rw="R"/>
-               <bitfield caption="High frequency oscillator status"
-                         mask="0x02"
-                         name="OSCHFS"
-                         rw="R"/>
-               <bitfield caption="32KHz oscillator status"
-                         mask="0x04"
-                         name="OSC32KS"
-                         rw="R"/>
-               <bitfield caption="32.768 kHz Crystal Oscillator status"
-                         mask="0x08"
-                         name="XOSC32KS"
-                         rw="R"/>
-               <bitfield caption="External Clock status / XOSCHF status"
-                         mask="0x10"
-                         name="EXTS"
-                         rw="R"/>
-            </register>
-            <register caption="MCLK Timebase"
-                      initval="0x00"
-                      name="MCLKTIMEBASE"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
-            </register>
-            <register caption="OSCHF Control A"
-                      initval="0x0C"
-                      name="OSCHFCTRLA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Automatic Oscillator Tune"
-                         mask="0x03"
-                         name="AUTOTUNE"
-                         rw="RW"
-                         values="CLKCTRL_AUTOTUNE"/>
-               <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="OSCHF Tune"
-                      initval="0x00"
-                      name="OSCHFTUNE"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
-            </register>
-            <register caption="OSC32K Control A"
-                      initval="0x00"
-                      name="OSC32KCTRLA"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSC32K Control A"
-                      initval="0x00"
-                      name="XOSC32KCTRLA"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
-               <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
-               <bitfield caption="Crystal startup time"
-                         mask="0x30"
-                         name="CSUT"
-                         rw="RW"
-                         values="CLKCTRL_CSUT"/>
-               <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="XOSCHF Control A"
-                      initval="0x00"
-                      name="XOSCHFCTRLA"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Source Select"
-                         mask="0x02"
-                         name="SELHF"
-                         rw="RW"
-                         values="CLKCTRL_SELHF"/>
-               <bitfield caption="Start-Up Time"
-                         mask="0x30"
-                         name="CSUTHF"
-                         rw="RW"
-                         values="CLKCTRL_CSUTHF"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
-            <value caption="Internal high-frequency oscillator"
-                   name="OSCHF"
-                   value="0x0"/>
-            <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
-            <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
-            <value caption="Divide by 2" name="DIV2" value="0x00"/>
-            <value caption="Divide by 4" name="DIV4" value="0x01"/>
-            <value caption="Divide by 8" name="DIV8" value="0x02"/>
-            <value caption="Divide by 16" name="DIV16" value="0x03"/>
-            <value caption="Divide by 32" name="DIV32" value="0x04"/>
-            <value caption="Divide by 64" name="DIV64" value="0x05"/>
-            <value caption="Divide by 6" name="DIV6" value="0x08"/>
-            <value caption="Divide by 10" name="DIV10" value="0x09"/>
-            <value caption="Divide by 12" name="DIV12" value="0x0A"/>
-            <value caption="Divide by 24" name="DIV24" value="0x0B"/>
-            <value caption="Divide by 48" name="DIV48" value="0x0C"/>
-         </value-group>
-         <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
-            <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
-            <value caption="High Frequency Crystal Oscillator"
-                   name="XOSCHF"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-         </value-group>
-         <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
-            <value caption="Regular interrupt" name="INT" value="0x0"/>
-            <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
-         </value-group>
-         <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
-            <value caption="Disabled" name="OFF" value="0x0"/>
-            <value caption="Tune against 32.768 kHz Crystal Oscillator"
-                   name="XOSC32K"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
-            <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
-            <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
-            <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
-         </value-group>
-         <value-group caption="Source Select" name="CLKCTRL_SELHF">
-            <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
-            <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
-         </value-group>
-         <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
-            <value caption="1k cycles" name="1K" value="0x00"/>
-            <value caption="16k cycles" name="16K" value="0x01"/>
-            <value caption="32k cycles" name="32K" value="0x02"/>
-            <value caption="64k cycles" name="64K" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
-         <register-group caption="CPU" name="CPU" size="0x10">
-            <register caption="Configuration Change Protection"
-                      initval="0x00"
-                      name="CCP"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCP signature"
-                         mask="0xFF"
-                         name="CCP"
-                         rw="RW"
-                         values="CPU_CCP"/>
-            </register>
-            <register caption="Stack Pointer"
-                      initval="0x7FFF"
-                      name="SP"
-                      offset="0xD"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Status Register"
-                      initval="0x00"
-                      name="SREG"
-                      offset="0xF"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
-               <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
-               <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
-               <bitfield caption="Two's Complement Overflow Flag"
-                         mask="0x08"
-                         name="V"
-                         rw="RW"/>
-               <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
-               <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
-               <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
-               <bitfield caption="Global Interrupt Enable Flag"
-                         mask="0x80"
-                         name="I"
-                         rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="CCP signature select" name="CPU_CCP">
-            <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
-            <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
-         </value-group>
-      </module>
-      <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
-         <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Round-robin Scheduling Enable"
-                         mask="0x01"
-                         name="LVL0RR"
-                         rw="RW"/>
-               <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
-               <bitfield caption="Interrupt Vector Select"
-                         mask="0x40"
-                         name="IVSEL"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Level 0 Interrupt Executing"
-                         mask="0x01"
-                         name="LVL0EX"
-                         rw="R"/>
-               <bitfield caption="Level 1 Interrupt Executing"
-                         mask="0x02"
-                         name="LVL1EX"
-                         rw="R"/>
-               <bitfield caption="Non-maskable Interrupt Executing"
-                         mask="0x80"
-                         name="NMIEX"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Level 0 Priority"
-                      initval="0x00"
-                      name="LVL0PRI"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Level Priority"
-                         mask="0xFF"
-                         name="LVL0PRI"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Level 1 Priority Vector"
-                      initval="0x00"
-                      name="LVL1VEC"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Vector with High Priority"
-                         mask="0xFF"
-                         name="LVL1VEC"
-                         rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
-         <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
-               <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CRC Source"
-                         mask="0x03"
-                         name="SRC"
-                         rw="RW"
-                         values="CRCSCAN_SRC"/>
-            </register>
-            <register caption="Status"
-                      initval="0x02"
-                      name="STATUS"
-                      offset="0x2"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
-               <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
-            </register>
-         </register-group>
-         <value-group caption="CRC Source select" name="CRCSCAN_SRC">
-            <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
-            <value caption="CRC on boot and appl section of flash"
-                   name="APPLICATION"
-                   value="0x1"/>
-            <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
-         </value-group>
-      </module>
-      <module caption="Digital to Analog Converter"
-              id="dac_nbit_ctrl_avr_v6"
-              name="DAC">
-         <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
-            <register caption="Control Register A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Output Buffer Range"
-                         mask="0x30"
-                         name="OUTRANGE"
-                         rw="RW"
-                         values="DAC_OUTRANGE"/>
-               <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
-               <bitfield caption="Run in Standby Mode"
-                         mask="0x80"
-                         name="RUNSTDBY"
-                         rw="RW"/>
-            </register>
-            <register caption="DATA Register"
-                      name="DATA"
-                      offset="0x2"
-                      rw="RW"
-                      size="2">
-               <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
-            <value caption="Output buffer automatically choose best range"
-                   name="AUTO"
-                   value="0x0"/>
-            <value caption="Output buffer configured to low range"
-                   name="LOW"
-                   value="0x2"/>
-            <value caption="Output buffer configured to high range"
-                   name="HIGH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Event System" id="avrea" name="EVSYS">
-         <register-group caption="Event System" name="EVSYS" size="0x40">
-            <register caption="Software Event A"
-                      initval="0x00"
-                      name="SWEVENTA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software event on channel select"
-                         mask="0xFF"
-                         name="SWEVENTA"
-                         rw="W"
-                         values="EVSYS_SWEVENTA"/>
-            </register>
-            <register caption="Multiplexer Channel 0"
-                      initval="0x00"
-                      name="CHANNEL0"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 1"
-                      initval="0x00"
-                      name="CHANNEL1"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 2"
-                      initval="0x00"
-                      name="CHANNEL2"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 3"
-                      initval="0x00"
-                      name="CHANNEL3"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 4"
-                      initval="0x00"
-                      name="CHANNEL4"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="Multiplexer Channel 5"
-                      initval="0x00"
-                      name="CHANNEL5"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Channel generator select"
-                         mask="0xFF"
-                         name="CHANNEL"
-                         rw="RW"
-                         values="EVSYS_CHANNEL"/>
-            </register>
-            <register caption="CCL0 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT0A"
-                      offset="0x20"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL0 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT0B"
-                      offset="0x21"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT1A"
-                      offset="0x22"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL1 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT1B"
-                      offset="0x23"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT2A"
-                      offset="0x24"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL2 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT2B"
-                      offset="0x25"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event A"
-                      initval="0x00"
-                      name="USERCCLLUT3A"
-                      offset="0x26"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="CCL3 Event B"
-                      initval="0x00"
-                      name="USERCCLLUT3B"
-                      offset="0x27"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="ADC0"
-                      initval="0x00"
-                      name="USERADC0START"
-                      offset="0x28"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTA"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTA"
-                      offset="0x29"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTB"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTB"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTC"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTC"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTD"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTD"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTE"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTE"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="EVOUTF"
-                      initval="0x00"
-                      name="USEREVSYSEVOUTF"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART0"
-                      initval="0x00"
-                      name="USERUSART0IRDA"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART1"
-                      initval="0x00"
-                      name="USERUSART1IRDA"
-                      offset="0x30"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="USART2"
-                      initval="0x00"
-                      name="USERUSART2IRDA"
-                      offset="0x31"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event A"
-                      initval="0x00"
-                      name="USERTCA0CNTA"
-                      offset="0x32"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA0 Event B"
-                      initval="0x00"
-                      name="USERTCA0CNTB"
-                      offset="0x33"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event A"
-                      initval="0x00"
-                      name="USERTCA1CNTA"
-                      offset="0x34"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCA1 Event B"
-                      initval="0x00"
-                      name="USERTCA1CNTB"
-                      offset="0x35"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event A"
-                      initval="0x00"
-                      name="USERTCB0CAPT"
-                      offset="0x36"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB0 Event B"
-                      initval="0x00"
-                      name="USERTCB0COUNT"
-                      offset="0x37"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event A"
-                      initval="0x00"
-                      name="USERTCB1CAPT"
-                      offset="0x38"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB1 Event B"
-                      initval="0x00"
-                      name="USERTCB1COUNT"
-                      offset="0x39"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event A"
-                      initval="0x00"
-                      name="USERTCB2CAPT"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB2 Event B"
-                      initval="0x00"
-                      name="USERTCB2COUNT"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event A"
-                      initval="0x00"
-                      name="USERTCB3CAPT"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-            <register caption="TCB3 Event B"
-                      initval="0x00"
-                      name="USERTCB3COUNT"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="User channel select"
-                         mask="0xFF"
-                         name="USER"
-                         rw="RW"
-                         values="EVSYS_USER"/>
-            </register>
-         </register-group>
-         <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
-            <value caption="Off" name="OFF" value="0x0"/>
-            <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
-            <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
-            <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
-            <value caption="Periodic Interrupt Timer Event 0"
-                   name="RTC_PITEV0"
-                   value="0x8"/>
-            <value caption="Periodic Interrupt Timer Event 1"
-                   name="RTC_PITEV1"
-                   value="0x9"/>
-            <value caption="Configurable Custom Logic LUT0"
-                   name="CCL_LUT0"
-                   value="0x10"/>
-            <value caption="Configurable Custom Logic LUT1"
-                   name="CCL_LUT1"
-                   value="0x11"/>
-            <value caption="Configurable Custom Logic LUT2"
-                   name="CCL_LUT2"
-                   value="0x12"/>
-            <value caption="Configurable Custom Logic LUT3"
-                   name="CCL_LUT3"
-                   value="0x13"/>
-            <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
-            <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
-            <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
-            <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
-            <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
-            <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
-            <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
-            <value caption="Port B Event 0" name="PORTB_EV0" value="0x42"/>
-            <value caption="Port B Event 1" name="PORTB_EV1" value="0x43"/>
-            <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
-            <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
-            <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
-            <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
-            <value caption="Port E Event 0" name="PORTE_EV0" value="0x48"/>
-            <value caption="Port E Event 1" name="PORTE_EV1" value="0x49"/>
-            <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
-            <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
-            <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
-            <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
-            <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
-            <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
-            <value caption="Timer/Counter A0 overflow / low byte timer underflow"
-                   name="TCA0_OVF_LUNF"
-                   value="0x80"/>
-            <value caption="Timer/Counter A0 high byte timer underflow"
-                   name="TCA0_HUNF"
-                   value="0x81"/>
-            <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
-                   name="TCA0_CMP0_LCMP0"
-                   value="0x84"/>
-            <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
-                   name="TCA0_CMP1_LCMP1"
-                   value="0x85"/>
-            <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
-                   name="TCA0_CMP2_LCMP2"
-                   value="0x86"/>
-            <value caption="Timer/Counter A1 overflow / low byte timer underflow"
-                   name="TCA1_OVF_LUNF"
-                   value="0x88"/>
-            <value caption="Timer/Counter A1 high byte timer underflow"
-                   name="TCA1_HUNF"
-                   value="0x89"/>
-            <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
-                   name="TCA1_CMP0_LCMP0"
-                   value="0x8C"/>
-            <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
-                   name="TCA1_CMP1_LCMP1"
-                   value="0x8D"/>
-            <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
-                   name="TCA1_CMP2_LCMP2"
-                   value="0x8E"/>
-            <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
-            <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
-            <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
-            <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
-            <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
-            <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
-            <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
-            <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
-         </value-group>
-         <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
-            <value caption="Software event on channel 0" name="CH0" value="0x01"/>
-            <value caption="Software event on channel 1" name="CH1" value="0x02"/>
-            <value caption="Software event on channel 2" name="CH2" value="0x04"/>
-            <value caption="Software event on channel 3" name="CH3" value="0x08"/>
-            <value caption="Software event on channel 4" name="CH4" value="0x10"/>
-            <value caption="Software event on channel 5" name="CH5" value="0x20"/>
-            <value caption="Software event on channel 6" name="CH6" value="0x40"/>
-            <value caption="Software event on channel 7" name="CH7" value="0x80"/>
-         </value-group>
-         <value-group caption="User channel select" name="EVSYS_USER">
-            <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
-            <value caption="Connect user to event channel 0"
-                   name="CHANNEL0"
-                   value="0x1"/>
-            <value caption="Connect user to event channel 1"
-                   name="CHANNEL1"
-                   value="0x2"/>
-            <value caption="Connect user to event channel 2"
-                   name="CHANNEL2"
-                   value="0x3"/>
-            <value caption="Connect user to event channel 3"
-                   name="CHANNEL3"
-                   value="0x4"/>
-            <value caption="Connect user to event channel 4"
-                   name="CHANNEL4"
-                   value="0x5"/>
-            <value caption="Connect user to event channel 5"
-                   name="CHANNEL5"
-                   value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Fuses" id="avrea" name="FUSE">
-         <register-group caption="Fuses" name="FUSE" size="0x09">
-            <register caption="Watchdog Configuration"
-                      initval="0x00"
-                      name="WDTCFG"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Watchdog Timeout Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="FUSE_PERIOD"/>
-               <bitfield caption="Watchdog Window Timeout Period"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="FUSE_WINDOW"/>
-            </register>
-            <register caption="BOD Configuration"
-                      initval="0x00"
-                      name="BODCFG"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="BOD Operation in Sleep Mode"
-                         mask="0x03"
-                         name="SLEEP"
-                         rw="RW"
-                         values="FUSE_SLEEP"/>
-               <bitfield caption="BOD Operation in Active Mode"
-                         mask="0x0C"
-                         name="ACTIVE"
-                         rw="RW"
-                         values="FUSE_ACTIVE"/>
-               <bitfield caption="BOD Sample Frequency"
-                         mask="0x10"
-                         name="SAMPFREQ"
-                         rw="RW"
-                         values="FUSE_SAMPFREQ"/>
-               <bitfield caption="BOD Level"
-                         mask="0xE0"
-                         name="LVL"
-                         rw="RW"
-                         values="FUSE_LVL"/>
-            </register>
-            <register caption="Oscillator Configuration"
-                      initval="0x00"
-                      name="OSCCFG"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="High-frequency Oscillator Frequency"
-                         mask="0x08"
-                         name="OSCHFFRQ"
-                         rw="RW"
-                         values="FUSE_OSCHFFRQ"/>
-            </register>
-            <register caption="System Configuration 0"
-                      initval="0xD0"
-                      name="SYSCFG0"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Save"
-                         mask="0x01"
-                         name="EESAVE"
-                         rw="RW"
-                         values="FUSE_EESAVE"/>
-               <bitfield caption="Reset Pin Configuration"
-                         mask="0x08"
-                         name="RSTPINCFG"
-                         rw="RW"
-                         values="FUSE_RSTPINCFG"/>
-               <bitfield caption="UPDI Pin Configuration"
-                         mask="0x10"
-                         name="UPDIPINCFG"
-                         rw="RW"
-                         values="FUSE_UPDIPINCFG"/>
-               <bitfield caption="CRC Select"
-                         mask="0x20"
-                         name="CRCSEL"
-                         rw="RW"
-                         values="FUSE_CRCSEL"/>
-               <bitfield caption="CRC Source"
-                         mask="0xC0"
-                         name="CRCSRC"
-                         rw="RW"
-                         values="FUSE_CRCSRC"/>
-            </register>
-            <register caption="System Configuration 1"
-                      initval="0x07"
-                      name="SYSCFG1"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Startup Time"
-                         mask="0x07"
-                         name="SUT"
-                         rw="RW"
-                         values="FUSE_SUT"/>
-            </register>
-            <register caption="Code Section Size"
-                      initval="0x00"
-                      name="CODESIZE"
-                      offset="0x7"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Boot Section Size"
-                      initval="0x00"
-                      name="BOOTSIZE"
-                      offset="0x8"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
-            <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
-                   name="ENABLEWAIT"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Level select" name="FUSE_LVL">
-            <value caption="BOD Disabled during normal operation"
-                   name="BODLEVEL0"
-                   value="0x00"/>
-            <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
-            <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
-            <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
-         </value-group>
-         <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
-            <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
-            <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
-         </value-group>
-         <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
-            <value caption="Disabled" name="DISABLE" value="0x00"/>
-            <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
-            <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
-         </value-group>
-         <value-group caption="High-frequency Oscillator Frequency select"
-                      name="FUSE_OSCHFFRQ">
-            <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
-            <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Select" name="FUSE_CRCSEL">
-            <value caption="Enable CRC16" name="CRC16" value="0x0"/>
-            <value caption="Enable CRC32" name="CRC32" value="0x1"/>
-         </value-group>
-         <value-group caption="CRC Source select" name="FUSE_CRCSRC">
-            <value caption="CRC of full Flash (boot, application code and application data)"
-                   name="FLASH"
-                   value="0x0"/>
-            <value caption="CRC of boot section" name="BOOT" value="0x1"/>
-            <value caption="CRC of application code and boot sections"
-                   name="BOOTAPP"
-                   value="0x2"/>
-            <value caption="No CRC" name="NOCRC" value="0x3"/>
-         </value-group>
-         <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
-            <value caption="EEPROM content is erased during chip erase"
-                   name="DISABLE"
-                   value="0x0"/>
-            <value caption="EEPROM content is preserved during chip erase"
-                   name="ENABLE"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
-            <value caption="No External Reset" name="NONE" value="0x0"/>
-            <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
-         </value-group>
-         <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
-            <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
-            <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
-         </value-group>
-         <value-group caption="Startup Time select" name="FUSE_SUT">
-            <value caption="0 ms" name="0MS" value="0x00"/>
-            <value caption="1 ms" name="1MS" value="0x01"/>
-            <value caption="2 ms" name="2MS" value="0x02"/>
-            <value caption="4 ms" name="4MS" value="0x03"/>
-            <value caption="8 ms" name="8MS" value="0x04"/>
-            <value caption="16 ms" name="16MS" value="0x05"/>
-            <value caption="32 ms" name="32MS" value="0x06"/>
-            <value caption="64 ms" name="64MS" value="0x07"/>
-         </value-group>
-         <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
-            <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
-            <value caption="Window mode off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-      <module caption="General Purpose Registers" id="avrea" name="GPR">
-         <register-group caption="General Purpose Registers" name="GPR" size="0x4">
-            <register caption="General Purpose Register 0"
-                      name="GPR0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 1"
-                      name="GPR1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 2"
-                      name="GPR2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="General Purpose Register 3"
-                      name="GPR3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Lockbits" id="avrea" name="LOCK">
-         <register-group caption="Lockbits" name="LOCK" size="0x4">
-            <register caption="Lock Key Bits"
-                      initval="0x5CC5C55C"
-                      name="KEY"
-                      offset="0x0"
-                      rw="RW"
-                      size="4">
-               <bitfield caption="Lock Key"
-                         mask="0xFFFFFFFF"
-                         name="KEY"
-                         rw="RW"
-                         values="LOCK_KEY"/>
-            </register>
-         </register-group>
-         <value-group caption="Lock Key select" name="LOCK_KEY">
-            <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
-            <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
-         </value-group>
-      </module>
-      <module caption="Non-volatile Memory Controller"
-              id="nvm_ctrl_avr_v3"
-              name="NVMCTRL">
-         <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x7F"
-                         name="CMD"
-                         rw="RW"
-                         values="NVMCTRL_CMD"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x30"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Application Code Write Protect"
-                         mask="0x01"
-                         name="APPCODEWP"
-                         rw="RW"/>
-               <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
-               <bitfield caption="Application Data Write Protect"
-                         mask="0x04"
-                         name="APPDATAWP"
-                         rw="RW"/>
-               <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
-               <bitfield caption="Flash Mapping in Data space"
-                         mask="0x30"
-                         name="FLMAP"
-                         rw="RW"
-                         values="NVMCTRL_FLMAP"/>
-               <bitfield caption="Flash Mapping Lock"
-                         mask="0x80"
-                         name="FLMAPLOCK"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
-               <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x06"
-                      rw="R"
-                      size="1">
-               <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
-               <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
-               <bitfield caption="Write error"
-                         mask="0x70"
-                         name="ERROR"
-                         rw="R"
-                         values="NVMCTRL_ERROR"/>
-            </register>
-            <register caption="Data"
-                      initval="0x0000"
-                      name="DATA"
-                      offset="0x08"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Address"
-                      initval="0x00000000"
-                      name="ADDR"
-                      offset="0x0C"
-                      rw="RW"
-                      size="4"/>
-         </register-group>
-         <value-group caption="Command select" name="NVMCTRL_CMD">
-            <value caption="No Command" name="NOCMD" value="0x00"/>
-            <value caption="No Operation" name="NOOP" value="0x01"/>
-            <value caption="Flash Page Write" name="FLPW" value="0x04"/>
-            <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
-            <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
-            <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
-            <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
-            <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
-            <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
-            <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
-            <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
-            <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
-            <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
-            <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
-            <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
-            <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
-            <value caption="EEPROM Erase Command (UPDI only)"
-                   name="EECHER"
-                   value="0x30"/>
-         </value-group>
-         <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
-            <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
-            <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
-            <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
-            <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
-         </value-group>
-         <value-group caption="Write error select" name="NVMCTRL_ERROR">
-            <value caption="No Error" name="NOERROR" value="0x0"/>
-            <value caption="Attempt to program write protected area"
-                   name="WRITEPROTECT"
-                   value="0x2"/>
-            <value caption="Selecting new write command while write command already seleted"
-                   name="CMDCOLLISION"
-                   value="0x3"/>
-            <value caption="Address cannot be written with selected command"
-                   name="WRONGSECTION"
-                   value="0x4"/>
-         </value-group>
-      </module>
-      <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
-         <register-group caption="I/O Ports" name="PORT" size="0x20">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Set"
-                      initval="0x00"
-                      name="DIRSET"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Clear"
-                      initval="0x00"
-                      name="DIRCLR"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Data Direction Toggle"
-                      initval="0x00"
-                      name="DIRTGL"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Set"
-                      initval="0x00"
-                      name="OUTSET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Clear"
-                      initval="0x00"
-                      name="OUTCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value Toggle"
-                      initval="0x00"
-                      name="OUTTGL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-            <register caption="Port Control"
-                      initval="0x00"
-                      name="PORTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
-            </register>
-            <register caption="Pin Control Config"
-                      initval="0x00"
-                      name="PINCONFIG"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin Control Update"
-                      initval="0x00"
-                      name="PINCTRLUPD"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Set"
-                      initval="0x00"
-                      name="PINCTRLSET"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin Control Clear"
-                      initval="0x00"
-                      name="PINCTRLCLR"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Pin 0 Control"
-                      initval="0x00"
-                      name="PIN0CTRL"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 1 Control"
-                      initval="0x00"
-                      name="PIN1CTRL"
-                      offset="0x11"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 2 Control"
-                      initval="0x00"
-                      name="PIN2CTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 3 Control"
-                      initval="0x00"
-                      name="PIN3CTRL"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 4 Control"
-                      initval="0x00"
-                      name="PIN4CTRL"
-                      offset="0x14"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 5 Control"
-                      initval="0x00"
-                      name="PIN5CTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 6 Control"
-                      initval="0x00"
-                      name="PIN6CTRL"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Pin 7 Control"
-                      initval="0x00"
-                      name="PIN7CTRL"
-                      offset="0x17"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Input/Sense Configuration"
-                         mask="0x07"
-                         name="ISC"
-                         rw="RW"
-                         values="PORT_ISC"/>
-               <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
-               <bitfield caption="Input Level Select"
-                         mask="0x40"
-                         name="INLVL"
-                         rw="RW"
-                         values="PORT_INLVL"/>
-               <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
-            </register>
-            <register caption="Event Generation Control"
-                      initval="0x00"
-                      name="EVGENCTRL"
-                      offset="0x18"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generator 0 Select"
-                         mask="0x07"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="PORT_EVGEN0SEL"/>
-               <bitfield caption="Event Generator 1 Select"
-                         mask="0x70"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="PORT_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
-            <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
-            <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
-            <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
-            <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
-            <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
-            <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
-            <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
-            <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
-         </value-group>
-         <value-group caption="Input Level Select" name="PORT_INLVL">
-            <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
-            <value caption="TTL Input level" name="TTL" value="0x1"/>
-         </value-group>
-         <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
-            <value caption="Interrupt disabled but input buffer enabled"
-                   name="INTDISABLE"
-                   value="0x0"/>
-            <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
-            <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
-            <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
-            <value caption="Digital Input Buffer disabled"
-                   name="INPUT_DISABLE"
-                   value="0x4"/>
-            <value caption="Sense low Level" name="LEVEL" value="0x5"/>
-         </value-group>
-      </module>
-      <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
-         <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
-            <register caption="EVSYS route A"
-                      initval="0x00"
-                      name="EVSYSROUTEA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Output A"
-                         mask="0x01"
-                         name="EVOUTA"
-                         rw="RW"
-                         values="PORTMUX_EVOUTA"/>
-               <bitfield caption="Event Output C"
-                         mask="0x04"
-                         name="EVOUTC"
-                         rw="RW"
-                         values="PORTMUX_EVOUTC"/>
-               <bitfield caption="Event Output D"
-                         mask="0x08"
-                         name="EVOUTD"
-                         rw="RW"
-                         values="PORTMUX_EVOUTD"/>
-               <bitfield caption="Event Output F"
-                         mask="0x20"
-                         name="EVOUTF"
-                         rw="RW"
-                         values="PORTMUX_EVOUTF"/>
-            </register>
-            <register caption="CCL route A"
-                      initval="0x00"
-                      name="CCLROUTEA"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="CCL Look-Up Table 0 Signals"
-                         mask="0x01"
-                         name="LUT0"
-                         rw="RW"
-                         values="PORTMUX_LUT0"/>
-               <bitfield caption="CCL Look-Up Table 1 Signals"
-                         mask="0x02"
-                         name="LUT1"
-                         rw="RW"
-                         values="PORTMUX_LUT1"/>
-               <bitfield caption="CCL Look-Up Table 2 Signals"
-                         mask="0x04"
-                         name="LUT2"
-                         rw="RW"
-                         values="PORTMUX_LUT2"/>
-            </register>
-            <register caption="USART route A"
-                      initval="0x00"
-                      name="USARTROUTEA"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART0 Routing"
-                         mask="0x07"
-                         name="USART0"
-                         rw="RW"
-                         values="PORTMUX_USART0"/>
-               <bitfield caption="USART1 Routing"
-                         mask="0x18"
-                         name="USART1"
-                         rw="RW"
-                         values="PORTMUX_USART1"/>
-            </register>
-            <register caption="USART route B"
-                      initval="0x00"
-                      name="USARTROUTEB"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="USART2 Routing"
-                         mask="0x30"
-                         name="USART2"
-                         rw="RW"
-                         values="PORTMUX_USART2"/>
-            </register>
-            <register caption="SPI route A"
-                      initval="0x00"
-                      name="SPIROUTEA"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI0 Signals"
-                         mask="0x07"
-                         name="SPI0"
-                         rw="RW"
-                         values="PORTMUX_SPI0"/>
-            </register>
-            <register caption="TWI route A"
-                      initval="0x00"
-                      name="TWIROUTEA"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TWI0 Signals"
-                         mask="0x03"
-                         name="TWI0"
-                         rw="RW"
-                         values="PORTMUX_TWI0"/>
-            </register>
-            <register caption="TCA route A"
-                      initval="0x00"
-                      name="TCAROUTEA"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCA0 Signals"
-                         mask="0x07"
-                         name="TCA0"
-                         rw="RW"
-                         values="PORTMUX_TCA0"/>
-               <bitfield caption="TCA1 Signals"
-                         mask="0x38"
-                         name="TCA1"
-                         rw="RW"
-                         values="PORTMUX_TCA1"/>
-            </register>
-            <register caption="TCB route A"
-                      initval="0x00"
-                      name="TCBROUTEA"
-                      offset="0x08"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="TCB0 Output"
-                         mask="0x01"
-                         name="TCB0"
-                         rw="RW"
-                         values="PORTMUX_TCB0"/>
-               <bitfield caption="TCB1 Output"
-                         mask="0x02"
-                         name="TCB1"
-                         rw="RW"
-                         values="PORTMUX_TCB1"/>
-               <bitfield caption="TCB2 Output"
-                         mask="0x04"
-                         name="TCB2"
-                         rw="RW"
-                         values="PORTMUX_TCB2"/>
-               <bitfield caption="TCB3 Output"
-                         mask="0x08"
-                         name="TCB3"
-                         rw="RW"
-                         values="PORTMUX_TCB3"/>
-            </register>
-            <register caption="AC route A"
-                      initval="0x00"
-                      name="ACROUTEA"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Analog Comparator 0 Output"
-                         mask="0x01"
-                         name="AC0"
-                         rw="RW"
-                         values="PORTMUX_AC0"/>
-               <bitfield caption="Analog Comparator 1 Output"
-                         mask="0x02"
-                         name="AC1"
-                         rw="RW"
-                         values="PORTMUX_AC1"/>
-            </register>
-         </register-group>
-         <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-            <value caption="OUT on PC6" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
-            <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
-            <value caption="OUT on PC6" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
-            <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
-            <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
-            <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
-            <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
-            <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
-            <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
-            <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
-            <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
-            <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
-            <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
-            <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
-            <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
-            <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
-            <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
-            <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
-            <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
-         </value-group>
-         <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
-            <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x0"/>
-            <value caption="PC4, PC5, PC6" name="PORTC" value="0x1"/>
-            <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
-            <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
-         </value-group>
-         <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
-            <value caption="PA2" name="DEFAULT" value="0x0"/>
-            <value caption="PF4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
-            <value caption="PA3" name="DEFAULT" value="0x0"/>
-            <value caption="PF5" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
-            <value caption="PC0" name="DEFAULT" value="0x0"/>
-            <value caption="PB4" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
-            <value caption="PB5" name="DEFAULT" value="0x0"/>
-            <value caption="PC1" name="ALT1" value="0x1"/>
-         </value-group>
-         <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
-            <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PA2, PA3}, {PC6, PC7}" name="ALT1" value="0x1"/>
-            <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
-            <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
-         </value-group>
-         <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
-            <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
-            <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
-            <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
-            <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x5"/>
-         </value-group>
-         <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
-            <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PC4, PC5, PC6, PC7}" name="ALT1" value="0x1"/>
-            <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-         <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
-            <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
-            <value caption="{PF4, PF5,- , -}" name="ALT1" value="0x1"/>
-            <value caption="Not connected to any pins" name="NONE" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="Reset controller"
-              id="rst_integration_avr_v2"
-              name="RSTCTRL">
-         <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
-            <register caption="Reset Flags"
-                      initval="0x00"
-                      name="RSTFR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
-               <bitfield caption="Brown out detector Reset flag"
-                         mask="0x02"
-                         name="BORF"
-                         rw="RW"/>
-               <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
-               <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
-               <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
-               <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
-            </register>
-            <register caption="Software Reset"
-                      initval="0x00"
-                      name="SWRR"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
-         <register-group caption="Real-Time Counter" name="RTC" size="0x20">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
-               <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
-               <bitfield caption="Prescaling Factor"
-                         mask="0x78"
-                         name="PRESCALER"
-                         rw="RW"
-                         values="RTC_PRESCALER"/>
-               <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLABUSY"
-                         rw="R"/>
-               <bitfield caption="Count Synchronization Busy Flag"
-                         mask="0x02"
-                         name="CNTBUSY"
-                         rw="R"/>
-               <bitfield caption="Period Synchronization Busy Flag"
-                         mask="0x04"
-                         name="PERBUSY"
-                         rw="R"/>
-               <bitfield caption="Comparator Synchronization Busy Flag"
-                         mask="0x08"
-                         name="CMPBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt enable"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt enable"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt Flag"
-                         mask="0x01"
-                         name="OVF"
-                         rw="RW"/>
-               <bitfield caption="Compare Match Interrupt"
-                         mask="0x02"
-                         name="CMP"
-                         rw="RW"/>
-            </register>
-            <register caption="Temporary"
-                      name="TEMP"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Debug control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Calibration"
-                      initval="0x00"
-                      name="CALIB"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Error Correction Value"
-                         mask="0x7F"
-                         name="ERROR"
-                         rw="RW"/>
-               <bitfield caption="Error Correction Sign Bit"
-                         mask="0x80"
-                         name="SIGN"
-                         rw="RW"/>
-            </register>
-            <register caption="Clock Select"
-                      initval="0x00"
-                      name="CLKSEL"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Clock Select"
-                         mask="0x03"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="RTC_CLKSEL"/>
-            </register>
-            <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
-            <register caption="Period"
-                      initval="0xFFFF"
-                      name="PER"
-                      offset="0x0A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
-            <register caption="PIT Control A"
-                      initval="0x00"
-                      name="PITCTRLA"
-                      offset="0x10"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
-               <bitfield caption="Period"
-                         mask="0x78"
-                         name="PERIOD"
-                         rw="RW"
-                         values="RTC_PERIOD"/>
-            </register>
-            <register caption="PIT Status"
-                      initval="0x00"
-                      name="PITSTATUS"
-                      offset="0x11"
-                      rw="R"
-                      size="1">
-               <bitfield caption="CTRLA Synchronization Busy Flag"
-                         mask="0x01"
-                         name="CTRLBUSY"
-                         rw="R"/>
-            </register>
-            <register caption="PIT Interrupt Control"
-                      initval="0x00"
-                      name="PITINTCTRL"
-                      offset="0x12"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Interrupt Flags"
-                      initval="0x00"
-                      name="PITINTFLAGS"
-                      offset="0x13"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
-            </register>
-            <register caption="PIT Debug control"
-                      initval="0x00"
-                      name="PITDBGCTRL"
-                      offset="0x15"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="PIT Event Generation Control A"
-                      initval="0x00"
-                      name="PITEVGENCTRLA"
-                      offset="0x16"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Generation 0 Select"
-                         mask="0x0F"
-                         name="EVGEN0SEL"
-                         rw="RW"
-                         values="RTC_EVGEN0SEL"/>
-               <bitfield caption="Event Generation 1 Select"
-                         mask="0xF0"
-                         name="EVGEN1SEL"
-                         rw="RW"
-                         values="RTC_EVGEN1SEL"/>
-            </register>
-         </register-group>
-         <value-group caption="Clock Select" name="RTC_CLKSEL">
-            <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
-            <value caption="Internal 32.768 kHz Oscillator Divided by 32"
-                   name="OSC1K"
-                   value="0x1"/>
-            <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
-            <value caption="External Clock" name="EXTCLK" value="0x3"/>
-         </value-group>
-         <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
-            <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
-            <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
-            <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
-            <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
-            <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
-            <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
-            <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
-            <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
-            <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
-            <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
-            <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
-            <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
-            <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
-            <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
-            <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
-            <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
-         </value-group>
-         <value-group caption="Period select" name="RTC_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
-            <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
-            <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
-            <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
-            <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
-            <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
-            <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
-            <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
-            <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
-            <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
-            <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
-            <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
-            <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
-            <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
-         </value-group>
-         <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-         <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
-            <value caption="No Event Generated" name="OFF" value="0x0"/>
-            <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
-            <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
-            <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
-            <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
-            <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
-            <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
-            <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
-            <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
-            <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
-            <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
-            <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
-            <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
-            <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
-            <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
-         </value-group>
-      </module>
-      <module caption="Signature row" id="avrea" name="SIGROW">
-         <register-group caption="Signature row" name="SIGROW" size="0x40">
-            <register caption="Device ID Byte 0"
-                      name="DEVICEID0"
-                      offset="0x00"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 1"
-                      name="DEVICEID1"
-                      offset="0x01"
-                      rw="R"
-                      size="1"/>
-            <register caption="Device ID Byte 2"
-                      name="DEVICEID2"
-                      offset="0x02"
-                      rw="R"
-                      size="1"/>
-            <register caption="Temperature Calibration 0"
-                      name="TEMPSENSE0"
-                      offset="0x04"
-                      rw="R"
-                      size="2"/>
-            <register caption="Temperature Calibration 1"
-                      name="TEMPSENSE1"
-                      offset="0x06"
-                      rw="R"
-                      size="2"/>
-            <register caption="Serial Number Byte 0"
-                      name="SERNUM0"
-                      offset="0x10"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 1"
-                      name="SERNUM1"
-                      offset="0x11"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 2"
-                      name="SERNUM2"
-                      offset="0x12"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 3"
-                      name="SERNUM3"
-                      offset="0x13"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 4"
-                      name="SERNUM4"
-                      offset="0x14"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 5"
-                      name="SERNUM5"
-                      offset="0x15"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 6"
-                      name="SERNUM6"
-                      offset="0x16"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 7"
-                      name="SERNUM7"
-                      offset="0x17"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 8"
-                      name="SERNUM8"
-                      offset="0x18"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 9"
-                      name="SERNUM9"
-                      offset="0x19"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 10"
-                      name="SERNUM10"
-                      offset="0x1A"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 11"
-                      name="SERNUM11"
-                      offset="0x1B"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 12"
-                      name="SERNUM12"
-                      offset="0x1C"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 13"
-                      name="SERNUM13"
-                      offset="0x1D"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 14"
-                      name="SERNUM14"
-                      offset="0x1E"
-                      rw="R"
-                      size="1"/>
-            <register caption="Serial Number Byte 15"
-                      name="SERNUM15"
-                      offset="0x1F"
-                      rw="R"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Sleep Controller"
-              id="clk_sleep_ctrl_avr_v1"
-              name="SLPCTRL">
-         <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
-               <bitfield caption="Sleep mode"
-                         mask="0x06"
-                         name="SMODE"
-                         rw="RW"
-                         values="SLPCTRL_SMODE"/>
-            </register>
-         </register-group>
-         <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
-            <value caption="Idle mode" name="IDLE" value="0x00"/>
-            <value caption="Standby Mode" name="STDBY" value="0x01"/>
-            <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
-         </value-group>
-      </module>
-      <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
-         <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Prescaler"
-                         mask="0x06"
-                         name="PRESC"
-                         rw="RW"
-                         values="SPI_PRESC"/>
-               <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
-               <bitfield caption="Host Operation Enable"
-                         mask="0x20"
-                         name="MASTER"
-                         rw="RW"/>
-               <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="SPI Mode"
-                         mask="0x03"
-                         name="MODE"
-                         rw="RW"
-                         values="SPI_MODE"/>
-               <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
-               <bitfield caption="Buffer Mode Wait for Receive"
-                         mask="0x40"
-                         name="BUFWR"
-                         rw="RW"/>
-               <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Enable"
-                         mask="0x10"
-                         name="SSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
-               <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
-               <bitfield caption="Buffer Overflow"
-                         mask="0x01"
-                         modes="BUFFERED"
-                         name="BUFOVF"
-                         rw="RW"/>
-               <bitfield caption="SPI Select Trigger Interrupt Flag"
-                         mask="0x10"
-                         modes="BUFFERED"
-                         name="SSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Flag"
-                         mask="0x20"
-                         modes="BUFFERED"
-                         name="DREIF"
-                         rw="RW"/>
-               <bitfield caption="Transfer Complete Interrupt Flag"
-                         mask="0x40"
-                         modes="BUFFERED"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         modes="BUFFERED"
-                         name="RXCIF"
-                         rw="RW"/>
-               <bitfield caption="Write Collision"
-                         mask="0x40"
-                         modes="DEFAULT"
-                         name="WRCOL"
-                         rw="RW"/>
-               <bitfield caption="Interrupt Flag"
-                         mask="0x80"
-                         modes="DEFAULT"
-                         name="IF"
-                         rw="RW"/>
-            </register>
-            <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
-         </register-group>
-         <value-group caption="Prescaler select" name="SPI_PRESC">
-            <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
-            <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
-         </value-group>
-         <value-group caption="SPI Mode select" name="SPI_MODE">
-            <value caption="SPI Mode 0" name="0" value="0x00"/>
-            <value caption="SPI Mode 1" name="1" value="0x01"/>
-            <value caption="SPI Mode 2" name="2" value="0x02"/>
-            <value caption="SPI Mode 3" name="3" value="0x03"/>
-         </value-group>
-      </module>
-      <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
-         <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
-            <register caption="Revision ID"
-                      name="REVID"
-                      offset="0x01"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
-               <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
-            </register>
-            <register caption="OCD Message Control"
-                      name="OCDMCTRL"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
-            </register>
-            <register caption="OCD Message Status"
-                      initval="0x00"
-                      name="OCDMSTATUS"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="16-bit Timer/Counter Type A"
-              id="tmr_16b_pwm_v1"
-              name="TCA">
-         <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
-            <mode caption="Single Mode"
-                  name="SINGLE"
-                  qualifier="TCA.SINGLE.CTRLD.SPLITM"
-                  value="0"/>
-            <mode caption="Split Mode"
-                  name="SPLIT"
-                  qualifier="TCA.SPLIT.CTRLD.SPLITM"
-                  value="1"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SINGLE_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Waveform generation mode"
-                         mask="0x07"
-                         name="WGMODE"
-                         rw="RW"
-                         values="TCA_SINGLE_WGMODE"/>
-               <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
-               <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
-               <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
-               <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Compare 0 Waveform Output Value"
-                         mask="0x01"
-                         name="CMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Waveform Output Value"
-                         mask="0x02"
-                         name="CMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Waveform Output Value"
-                         mask="0x04"
-                         name="CMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Direction"
-                         mask="0x01"
-                         name="DIR"
-                         rw="RW"
-                         values="TCA_SINGLE_DIR"/>
-               <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SINGLE_CMD"/>
-            </register>
-            <register caption="Control F Clear"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFCLR"
-                      offset="0x06"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control F Set"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="CTRLFSET"
-                      offset="0x07"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
-               <bitfield caption="Compare 0 Buffer Valid"
-                         mask="0x02"
-                         name="CMP0BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 1 Buffer Valid"
-                         mask="0x04"
-                         name="CMP1BV"
-                         rw="RW"/>
-               <bitfield caption="Compare 2 Buffer Valid"
-                         mask="0x08"
-                         name="CMP2BV"
-                         rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="EVCTRL"
-                      offset="0x09"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Count on Event Input A"
-                         mask="0x01"
-                         name="CNTAEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action A"
-                         mask="0x0E"
-                         name="EVACTA"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTA"/>
-               <bitfield caption="Count on Event Input B"
-                         mask="0x10"
-                         name="CNTBEI"
-                         rw="RW"/>
-               <bitfield caption="Event Action B"
-                         mask="0xE0"
-                         name="EVACTB"
-                         rw="RW"
-                         values="TCA_SINGLE_EVACTB"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
-               <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
-               <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
-               <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SINGLE"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary data for 16-bit Access"
-                      modes="SINGLE"
-                      name="TEMP"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      modes="SINGLE"
-                      name="CNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period"
-                      modes="SINGLE"
-                      name="PER"
-                      offset="0x26"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0"
-                      modes="SINGLE"
-                      name="CMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1"
-                      modes="SINGLE"
-                      name="CMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2"
-                      modes="SINGLE"
-                      name="CMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Period Buffer"
-                      modes="SINGLE"
-                      name="PERBUF"
-                      offset="0x36"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 0 Buffer"
-                      modes="SINGLE"
-                      name="CMP0BUF"
-                      offset="0x38"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 1 Buffer"
-                      modes="SINGLE"
-                      name="CMP1BUF"
-                      offset="0x3A"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare 2 Buffer"
-                      modes="SINGLE"
-                      name="CMP2BUF"
-                      offset="0x3C"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control A"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLA"
-                      offset="0x00"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Selection"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCA_SPLIT_CLKSEL"/>
-               <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLB"
-                      offset="0x01"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Enable"
-                         mask="0x01"
-                         name="LCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Enable"
-                         mask="0x02"
-                         name="LCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Enable"
-                         mask="0x04"
-                         name="LCMP2EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Enable"
-                         mask="0x10"
-                         name="HCMP0EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Enable"
-                         mask="0x20"
-                         name="HCMP1EN"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Enable"
-                         mask="0x40"
-                         name="HCMP2EN"
-                         rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLC"
-                      offset="0x02"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Compare 0 Output Value"
-                         mask="0x01"
-                         name="LCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Output Value"
-                         mask="0x02"
-                         name="LCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Output Value"
-                         mask="0x04"
-                         name="LCMP2OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 0 Output Value"
-                         mask="0x10"
-                         name="HCMP0OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 1 Output Value"
-                         mask="0x20"
-                         name="HCMP1OV"
-                         rw="RW"/>
-               <bitfield caption="High Compare 2 Output Value"
-                         mask="0x40"
-                         name="HCMP2OV"
-                         rw="RW"/>
-            </register>
-            <register caption="Control D"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLD"
-                      offset="0x03"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
-            </register>
-            <register caption="Control E Clear"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLECLR"
-                      offset="0x04"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Control E Set"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="CTRLESET"
-                      offset="0x05"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command Enable"
-                         mask="0x03"
-                         name="CMDEN"
-                         rw="RW"
-                         values="TCA_SPLIT_CMDEN"/>
-               <bitfield caption="Command"
-                         mask="0x0C"
-                         name="CMD"
-                         rw="RW"
-                         values="TCA_SPLIT_CMD"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTCTRL"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Enable"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Enable"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Enable"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Enable"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Enable"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="INTFLAGS"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Low Underflow Interrupt Flag"
-                         mask="0x01"
-                         name="LUNF"
-                         rw="RW"/>
-               <bitfield caption="High Underflow Interrupt Flag"
-                         mask="0x02"
-                         name="HUNF"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 2 Interrupt Flag"
-                         mask="0x10"
-                         name="LCMP0"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 1 Interrupt Flag"
-                         mask="0x20"
-                         name="LCMP1"
-                         rw="RW"/>
-               <bitfield caption="Low Compare 0 Interrupt Flag"
-                         mask="0x40"
-                         name="LCMP2"
-                         rw="RW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      modes="SPLIT"
-                      name="DBGCTRL"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Low Count"
-                      modes="SPLIT"
-                      name="LCNT"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Count"
-                      modes="SPLIT"
-                      name="HCNT"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Period"
-                      modes="SPLIT"
-                      name="LPER"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Period"
-                      modes="SPLIT"
-                      name="HPER"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP0"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP0"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP1"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP1"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Low Compare"
-                      modes="SPLIT"
-                      name="LCMP2"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="High Compare"
-                      modes="SPLIT"
-                      name="HCMP2"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-         <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
-            <value caption="Normal Mode" name="NORMAL" value="0x00"/>
-            <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
-            <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
-            <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
-            <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
-                   name="DSBOTH"
-                   value="0x06"/>
-            <value caption="Dual Slope PWM, overflow on BOTTOM"
-                   name="DSBOTTOM"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SINGLE_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Direction select" name="TCA_SINGLE_DIR">
-            <value caption="Count up" name="UP" value="0x0"/>
-            <value caption="Count down" name="DOWN" value="0x1"/>
-         </value-group>
-         <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
-            <value caption="Count on positive edge event"
-                   name="CNT_POSEDGE"
-                   value="0x00"/>
-            <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
-            <value caption="Count on prescaled clock while event line is 1."
-                   name="CNT_HIGHLVL"
-                   value="0x02"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-         </value-group>
-         <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
-            <value caption="No Action" name="NONE" value="0x00"/>
-            <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
-                   name="UPDOWN"
-                   value="0x03"/>
-            <value caption="Restart counter at positive edge event"
-                   name="RESTART_POSEDGE"
-                   value="0x04"/>
-            <value caption="Restart counter on any edge event"
-                   name="RESTART_ANYEDGE"
-                   value="0x05"/>
-            <value caption="Restart counter while event line is 1."
-                   name="RESTART_HIGHLVL"
-                   value="0x06"/>
-         </value-group>
-         <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
-            <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
-            <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
-            <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
-            <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
-            <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
-            <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
-         </value-group>
-         <value-group caption="Command select" name="TCA_SPLIT_CMD">
-            <value caption="No Command" name="NONE" value="0x00"/>
-            <value caption="Force Update" name="UPDATE" value="0x01"/>
-            <value caption="Force Restart" name="RESTART" value="0x02"/>
-            <value caption="Force Hard Reset" name="RESET" value="0x03"/>
-         </value-group>
-         <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
-            <value caption="None" name="NONE" value="0x0"/>
-            <value caption="Both low byte and high byte counter"
-                   name="BOTH"
-                   value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
-         <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Clock Select"
-                         mask="0x0E"
-                         name="CLKSEL"
-                         rw="RW"
-                         values="TCB_CLKSEL"/>
-               <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
-               <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
-               <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
-            </register>
-            <register caption="Control Register B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Timer Mode"
-                         mask="0x07"
-                         name="CNTMODE"
-                         rw="RW"
-                         values="TCB_CNTMODE"/>
-               <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
-               <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
-               <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
-               <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
-               <bitfield caption="Input Capture Noise Cancellation Filter"
-                         mask="0x40"
-                         name="FILTER"
-                         rw="RW"/>
-            </register>
-            <register caption="Interrupt Control"
-                      initval="0x00"
-                      name="INTCTRL"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
-               <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x7"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Temporary Value"
-                      name="TEMP"
-                      offset="0x9"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Count"
-                      initval="0x0000"
-                      name="CNT"
-                      offset="0xA"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Compare or Capture"
-                      name="CCMP"
-                      offset="0xC"
-                      rw="RW"
-                      size="2"/>
-         </register-group>
-         <value-group caption="Clock Select" name="TCB_CLKSEL">
-            <value caption="CLK_PER" name="DIV1" value="0x00"/>
-            <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
-            <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
-            <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
-            <value caption="Count on event edge" name="EVENT" value="0x07"/>
-         </value-group>
-         <value-group caption="Timer Mode select" name="TCB_CNTMODE">
-            <value caption="Periodic Interrupt" name="INT" value="0x00"/>
-            <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
-            <value caption="Input Capture Event" name="CAPT" value="0x02"/>
-            <value caption="Input Capture Frequency measurement"
-                   name="FRQ"
-                   value="0x03"/>
-            <value caption="Input Capture Pulse-Width measurement"
-                   name="PW"
-                   value="0x04"/>
-            <value caption="Input Capture Frequency and Pulse-Width measurement"
-                   name="FRQPW"
-                   value="0x05"/>
-            <value caption="Single Shot" name="SINGLE" value="0x06"/>
-            <value caption="8-bit PWM" name="PWM8" value="0x07"/>
-         </value-group>
-      </module>
-      <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
-         <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Fast-mode Enable"
-                         mask="0x01"
-                         name="FMEN"
-                         rw="RW"
-                         values="TWI_FMEN"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="SDA Setup Time"
-                         mask="0x10"
-                         name="SDASETUP"
-                         rw="RW"
-                         values="TWI_SDASETUP"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Dual Mode Control"
-                      initval="0x00"
-                      name="DUALCTRL"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Fast-mode Plus Enable"
-                         mask="0x02"
-                         name="FMPEN"
-                         rw="RW"
-                         values="TWI_FMPEN"/>
-               <bitfield caption="SDA Hold Time"
-                         mask="0x0C"
-                         name="SDAHOLD"
-                         rw="RW"
-                         values="TWI_SDAHOLD"/>
-               <bitfield caption="Input voltage transition level"
-                         mask="0x40"
-                         name="INPUTLVL"
-                         rw="RW"
-                         values="TWI_INPUTLVL"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run"
-                         mask="0x01"
-                         name="DBGRUN"
-                         rw="RW"
-                         values="TWI_DBGRUN"/>
-            </register>
-            <register caption="Host Control A"
-                      initval="0x00"
-                      name="MCTRLA"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Inactive Bus Time-Out"
-                         mask="0x0C"
-                         name="TIMEOUT"
-                         rw="RW"
-                         values="TWI_TIMEOUT"/>
-               <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
-               <bitfield caption="Write Interrupt Enable"
-                         mask="0x40"
-                         name="WIEN"
-                         rw="RW"/>
-               <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
-            </register>
-            <register caption="Host Control B"
-                      initval="0x00"
-                      name="MCTRLB"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="MCMD"
-                         rw="RW"
-                         values="TWI_MCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-               <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
-            </register>
-            <register caption="Host STATUS"
-                      initval="0x00"
-                      name="MSTATUS"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Bus State"
-                         mask="0x03"
-                         name="BUSSTATE"
-                         rw="RW"
-                         values="TWI_BUSSTATE"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
-               <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
-            </register>
-            <register caption="Host Baud Rate"
-                      initval="0x00"
-                      name="MBAUD"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
-            </register>
-            <register caption="Host Address"
-                      initval="0x00"
-                      name="MADDR"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Host Data"
-                      initval="0x00"
-                      name="MDATA"
-                      offset="0x8"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Control A"
-                      initval="0x00"
-                      name="SCTRLA"
-                      offset="0x9"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
-               <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
-               <bitfield caption="Address Recognition Mode"
-                         mask="0x04"
-                         name="PMEN"
-                         rw="RW"/>
-               <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Enable"
-                         mask="0x40"
-                         name="APIEN"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
-            </register>
-            <register caption="Client Control B"
-                      initval="0x00"
-                      name="SCTRLB"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Command"
-                         mask="0x03"
-                         name="SCMD"
-                         rw="RW"
-                         values="TWI_SCMD"/>
-               <bitfield caption="Acknowledge Action"
-                         mask="0x04"
-                         name="ACKACT"
-                         rw="RW"
-                         values="TWI_ACKACT"/>
-            </register>
-            <register caption="Client Status"
-                      initval="0x00"
-                      name="SSTATUS"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address or Stop"
-                         mask="0x01"
-                         name="AP"
-                         rw="RW"
-                         values="TWI_AP"/>
-               <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
-               <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
-               <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
-               <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
-               <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
-               <bitfield caption="Address or Stop Interrupt Flag"
-                         mask="0x40"
-                         name="APIF"
-                         rw="RW"/>
-               <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
-            </register>
-            <register caption="Client Address"
-                      initval="0x00"
-                      name="SADDR"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
-            </register>
-            <register caption="Client Data"
-                      initval="0x00"
-                      name="SDATA"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
-            </register>
-            <register caption="Client Address Mask"
-                      initval="0x00"
-                      name="SADDRMASK"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
-               <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
-            <value caption="SCL duty cycle operating according to Sm specification"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="SCL duty cycle operating according to Fm specification"
-                   name="ON"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
-            <value caption="Operating in Standard-mode or Fast-mode"
-                   name="OFF"
-                   value="0x0"/>
-            <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
-         </value-group>
-         <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
-            <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
-            <value caption="SMBus 3.0 input voltage transition level"
-                   name="SMBUS"
-                   value="0x1"/>
-         </value-group>
-         <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
-            <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
-            <value caption="Short SDA hold time" name="50NS" value="0x1"/>
-            <value caption="Meets SMBUS 2.0 specification under typical conditions"
-                   name="300NS"
-                   value="0x2"/>
-            <value caption="Meets SMBUS 2.0 specificaiton across all corners"
-                   name="500NS"
-                   value="0x3"/>
-         </value-group>
-         <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
-            <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
-            <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
-         </value-group>
-         <value-group caption="Debug Run select" name="TWI_DBGRUN">
-            <value caption="The peripheral is halted in Break Debug mode and ignores events"
-                   name="HALT"
-                   value="0"/>
-            <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
-                   name="RUN"
-                   value="1"/>
-         </value-group>
-         <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
-            <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
-            <value caption="50us - SMBus" name="50US" value="1"/>
-            <value caption="100us" name="100US" value="2"/>
-            <value caption="200us" name="200US" value="3"/>
-         </value-group>
-         <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
-            <value caption="Send ACK" name="ACK" value="0x0"/>
-            <value caption="Send NACK" name="NACK" value="0x1"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_MCMD">
-            <value caption="No action" name="NOACT" value="0"/>
-            <value caption="Execute Acknowledge Action followed by repeated Start."
-                   name="REPSTART"
-                   value="1"/>
-            <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
-                   name="RECVTRANS"
-                   value="2"/>
-            <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
-                   name="STOP"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Bus State select" name="TWI_BUSSTATE">
-            <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
-            <value caption="Bus is idle" name="IDLE" value="1"/>
-            <value caption="This TWI controls the bus" name="OWNER" value="2"/>
-            <value caption="The bus is busy" name="BUSY" value="3"/>
-         </value-group>
-         <value-group caption="Command select" name="TWI_SCMD">
-            <value caption="No Action" name="NOACT" value="0"/>
-            <value caption="Complete transaction" name="COMPTRANS" value="2"/>
-            <value caption="Used in response to an interrupt"
-                   name="RESPONSE"
-                   value="3"/>
-         </value-group>
-         <value-group caption="Address or Stop select" name="TWI_AP">
-            <value caption="A Stop condition generated the interrupt on APIF flag"
-                   name="STOP"
-                   value="0"/>
-            <value caption="Address detection generated the interrupt on APIF flag"
-                   name="ADR"
-                   value="1"/>
-         </value-group>
-      </module>
-      <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-              id="uart_autobd_v4"
-              name="USART">
-         <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
-                         name="USART"
-                         size="0x10">
-            <register caption="Receive Data Low Byte"
-                      initval="0x00"
-                      name="RXDATAL"
-                      offset="0x0"
-                      rw="R"
-                      size="1">
-               <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
-            </register>
-            <register caption="Receive Data High Byte"
-                      initval="0x00"
-                      name="RXDATAH"
-                      offset="0x1"
-                      rw="R"
-                      size="1">
-               <bitfield caption="Receiver Data Register"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="R"/>
-               <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
-               <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
-               <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Transmit Data Low Byte"
-                      initval="0x00"
-                      name="TXDATAL"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register"
-                         mask="0xFF"
-                         name="DATA"
-                         rw="RW"/>
-            </register>
-            <register caption="Transmit Data High Byte"
-                      initval="0x00"
-                      name="TXDATAH"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
-                         mask="0x01"
-                         name="DATA8"
-                         rw="RW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
-               <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
-               <bitfield caption="Inconsistent Sync Field Interrupt Flag"
-                         mask="0x08"
-                         name="ISFIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Start Interrupt"
-                         mask="0x10"
-                         name="RXSIF"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Flag"
-                         mask="0x20"
-                         name="DREIF"
-                         rw="R"/>
-               <bitfield caption="Transmit Interrupt Flag"
-                         mask="0x40"
-                         name="TXCIF"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Flag"
-                         mask="0x80"
-                         name="RXCIF"
-                         rw="R"/>
-            </register>
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x5"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="RS485 Mode internal transmitter"
-                         mask="0x01"
-                         name="RS485"
-                         rw="RW"
-                         values="USART_RS485"/>
-               <bitfield caption="Auto-baud Error Interrupt Enable"
-                         mask="0x04"
-                         name="ABEIE"
-                         rw="RW"/>
-               <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
-               <bitfield caption="Receiver Start Frame Interrupt Enable"
-                         mask="0x10"
-                         name="RXSIE"
-                         rw="RW"/>
-               <bitfield caption="Data Register Empty Interrupt Enable"
-                         mask="0x20"
-                         name="DREIE"
-                         rw="RW"/>
-               <bitfield caption="Transmit Complete Interrupt Enable"
-                         mask="0x40"
-                         name="TXCIE"
-                         rw="RW"/>
-               <bitfield caption="Receive Complete Interrupt Enable"
-                         mask="0x80"
-                         name="RXCIE"
-                         rw="RW"/>
-            </register>
-            <register caption="Control B"
-                      initval="0x00"
-                      name="CTRLB"
-                      offset="0x6"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Multi-processor Communication Mode"
-                         mask="0x01"
-                         name="MPCM"
-                         rw="RW"/>
-               <bitfield caption="Receiver Mode"
-                         mask="0x06"
-                         name="RXMODE"
-                         rw="RW"
-                         values="USART_RXMODE"/>
-               <bitfield caption="Open Drain Mode Enable"
-                         mask="0x08"
-                         name="ODME"
-                         rw="RW"/>
-               <bitfield caption="Start Frame Detection Enable"
-                         mask="0x10"
-                         name="SFDEN"
-                         rw="RW"/>
-               <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
-               <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
-            </register>
-            <register caption="Control C"
-                      initval="0x03"
-                      name="CTRLC"
-                      offset="0x7"
-                      rw="RW"
-                      size="1">
-               <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
-               <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
-               <bitfield caption="Communication Mode"
-                         mask="0xC0"
-                         name="CMODE"
-                         rw="RW"
-                         values="USART_CMODE"/>
-               <bitfield caption="SPI Host Mode, Clock Phase"
-                         mask="0x02"
-                         modes="MSPI"
-                         name="UCPHA"
-                         rw="RW"/>
-               <bitfield caption="SPI Host Mode, Data Order"
-                         mask="0x04"
-                         modes="MSPI"
-                         name="UDORD"
-                         rw="RW"/>
-               <bitfield caption="Character Size"
-                         mask="0x07"
-                         modes="NORMAL"
-                         name="CHSIZE"
-                         rw="RW"
-                         values="USART_NORMAL_CHSIZE"/>
-               <bitfield caption="Stop Bit Mode"
-                         mask="0x08"
-                         modes="NORMAL"
-                         name="SBMODE"
-                         rw="RW"
-                         values="USART_NORMAL_SBMODE"/>
-               <bitfield caption="Parity Mode"
-                         mask="0x30"
-                         modes="NORMAL"
-                         name="PMODE"
-                         rw="RW"
-                         values="USART_NORMAL_PMODE"/>
-            </register>
-            <register caption="Baud Rate"
-                      initval="0x0000"
-                      name="BAUD"
-                      offset="0x8"
-                      rw="RW"
-                      size="2"/>
-            <register caption="Control D"
-                      initval="0x00"
-                      name="CTRLD"
-                      offset="0xA"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Auto Baud Window"
-                         mask="0xC0"
-                         name="ABW"
-                         rw="RW"
-                         values="USART_ABW"/>
-            </register>
-            <register caption="Debug Control"
-                      initval="0x00"
-                      name="DBGCTRL"
-                      offset="0xB"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
-            </register>
-            <register caption="Event Control"
-                      initval="0x00"
-                      name="EVCTRL"
-                      offset="0xC"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="IrDA Event Input Enable"
-                         mask="0x01"
-                         name="IREI"
-                         rw="RW"/>
-            </register>
-            <register caption="IRCOM Transmitter Pulse Length Control"
-                      initval="0x00"
-                      name="TXPLCTRL"
-                      offset="0xD"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
-            </register>
-            <register caption="IRCOM Receiver Pulse Length Control"
-                      initval="0x00"
-                      name="RXPLCTRL"
-                      offset="0xE"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
-            <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
-            <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
-         </value-group>
-         <value-group caption="Receiver Mode select" name="USART_RXMODE">
-            <value caption="Normal mode" name="NORMAL" value="0x0"/>
-            <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
-            <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
-            <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
-         </value-group>
-         <value-group caption="Communication Mode select" name="USART_CMODE">
-            <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
-            <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
-            <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
-            <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
-         </value-group>
-         <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
-            <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
-            <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
-            <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
-            <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
-            <value caption="Character size: 9 bit read low byte first"
-                   name="9BITL"
-                   value="0x06"/>
-            <value caption="Character size: 9 bit read high byte first"
-                   name="9BITH"
-                   value="0x07"/>
-         </value-group>
-         <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
-            <value caption="No Parity" name="DISABLED" value="0x00"/>
-            <value caption="Even Parity" name="EVEN" value="0x02"/>
-            <value caption="Odd Parity" name="ODD" value="0x03"/>
-         </value-group>
-         <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
-            <value caption="1 stop bit" name="1BIT" value="0x0"/>
-            <value caption="2 stop bits" name="2BIT" value="0x1"/>
-         </value-group>
-         <value-group caption="Auto Baud Window select" name="USART_ABW">
-            <value caption="18% tolerance" name="WDW0" value="0x0"/>
-            <value caption="15% tolerance" name="WDW1" value="0x1"/>
-            <value caption="21% tolerance" name="WDW2" value="0x2"/>
-            <value caption="25% tolerance" name="WDW3" value="0x3"/>
-         </value-group>
-      </module>
-      <module caption="User Row" id="avrea" name="USERROW">
-         <register-group caption="User Row" name="USERROW" size="0x40">
-            <register caption="User Row Byte 0"
-                      name="USERROW0"
-                      offset="0x00"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 1"
-                      name="USERROW1"
-                      offset="0x01"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 2"
-                      name="USERROW2"
-                      offset="0x02"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 3"
-                      name="USERROW3"
-                      offset="0x03"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 4"
-                      name="USERROW4"
-                      offset="0x04"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 5"
-                      name="USERROW5"
-                      offset="0x05"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 6"
-                      name="USERROW6"
-                      offset="0x06"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 7"
-                      name="USERROW7"
-                      offset="0x07"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 8"
-                      name="USERROW8"
-                      offset="0x08"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 9"
-                      name="USERROW9"
-                      offset="0x09"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 10"
-                      name="USERROW10"
-                      offset="0x0A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 11"
-                      name="USERROW11"
-                      offset="0x0B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 12"
-                      name="USERROW12"
-                      offset="0x0C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 13"
-                      name="USERROW13"
-                      offset="0x0D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 14"
-                      name="USERROW14"
-                      offset="0x0E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 15"
-                      name="USERROW15"
-                      offset="0x0F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 16"
-                      name="USERROW16"
-                      offset="0x10"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 17"
-                      name="USERROW17"
-                      offset="0x11"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 18"
-                      name="USERROW18"
-                      offset="0x12"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 19"
-                      name="USERROW19"
-                      offset="0x13"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 20"
-                      name="USERROW20"
-                      offset="0x14"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 21"
-                      name="USERROW21"
-                      offset="0x15"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 22"
-                      name="USERROW22"
-                      offset="0x16"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 23"
-                      name="USERROW23"
-                      offset="0x17"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 24"
-                      name="USERROW24"
-                      offset="0x18"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 25"
-                      name="USERROW25"
-                      offset="0x19"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 26"
-                      name="USERROW26"
-                      offset="0x1A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 27"
-                      name="USERROW27"
-                      offset="0x1B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 28"
-                      name="USERROW28"
-                      offset="0x1C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 29"
-                      name="USERROW29"
-                      offset="0x1D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 30"
-                      name="USERROW30"
-                      offset="0x1E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 31"
-                      name="USERROW31"
-                      offset="0x1F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 32"
-                      name="USERROW32"
-                      offset="0x20"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 33"
-                      name="USERROW33"
-                      offset="0x21"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 34"
-                      name="USERROW34"
-                      offset="0x22"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 35"
-                      name="USERROW35"
-                      offset="0x23"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 36"
-                      name="USERROW36"
-                      offset="0x24"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 37"
-                      name="USERROW37"
-                      offset="0x25"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 38"
-                      name="USERROW38"
-                      offset="0x26"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 39"
-                      name="USERROW39"
-                      offset="0x27"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 40"
-                      name="USERROW40"
-                      offset="0x28"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 41"
-                      name="USERROW41"
-                      offset="0x29"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 42"
-                      name="USERROW42"
-                      offset="0x2A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 43"
-                      name="USERROW43"
-                      offset="0x2B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 44"
-                      name="USERROW44"
-                      offset="0x2C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 45"
-                      name="USERROW45"
-                      offset="0x2D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 46"
-                      name="USERROW46"
-                      offset="0x2E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 47"
-                      name="USERROW47"
-                      offset="0x2F"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 48"
-                      name="USERROW48"
-                      offset="0x30"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 49"
-                      name="USERROW49"
-                      offset="0x31"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 50"
-                      name="USERROW50"
-                      offset="0x32"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 51"
-                      name="USERROW51"
-                      offset="0x33"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 52"
-                      name="USERROW52"
-                      offset="0x34"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 53"
-                      name="USERROW53"
-                      offset="0x35"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 54"
-                      name="USERROW54"
-                      offset="0x36"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 55"
-                      name="USERROW55"
-                      offset="0x37"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 56"
-                      name="USERROW56"
-                      offset="0x38"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 57"
-                      name="USERROW57"
-                      offset="0x39"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 58"
-                      name="USERROW58"
-                      offset="0x3A"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 59"
-                      name="USERROW59"
-                      offset="0x3B"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 60"
-                      name="USERROW60"
-                      offset="0x3C"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 61"
-                      name="USERROW61"
-                      offset="0x3D"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 62"
-                      name="USERROW62"
-                      offset="0x3E"
-                      rw="RW"
-                      size="1"/>
-            <register caption="User Row Byte 63"
-                      name="USERROW63"
-                      offset="0x3F"
-                      rw="RW"
-                      size="1"/>
-         </register-group>
-      </module>
-      <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
-         <register-group caption="Virtual Ports" name="VPORT" size="0x4">
-            <register caption="Data Direction"
-                      initval="0x00"
-                      name="DIR"
-                      offset="0x0"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Output Value"
-                      initval="0x00"
-                      name="OUT"
-                      offset="0x1"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Input Value"
-                      initval="0x00"
-                      name="IN"
-                      offset="0x2"
-                      rw="RW"
-                      size="1"/>
-            <register caption="Interrupt Flags"
-                      initval="0x00"
-                      name="INTFLAGS"
-                      offset="0x3"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
-            </register>
-         </register-group>
-      </module>
-      <module caption="Voltage reference" id="avrea" name="VREF">
-         <register-group caption="Voltage reference" name="VREF" size="0x2">
-            <register caption="DAC0 Reference"
-                      initval="0x00"
-                      name="DAC0REF"
-                      offset="0x2"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-            <register caption="AC Reference"
-                      initval="0x00"
-                      name="ACREF"
-                      offset="0x4"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Reference select"
-                         mask="0x07"
-                         name="REFSEL"
-                         rw="RW"
-                         values="VREF_REFSEL"/>
-               <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Reference select" name="VREF_REFSEL">
-            <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
-            <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
-            <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
-            <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
-            <value caption="VDD as reference" name="VDD" value="0x5"/>
-            <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
-         </value-group>
-      </module>
-      <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
-         <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
-            <register caption="Control A"
-                      initval="0x00"
-                      name="CTRLA"
-                      offset="0x0"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Period"
-                         mask="0x0F"
-                         name="PERIOD"
-                         rw="RW"
-                         values="WDT_PERIOD"/>
-               <bitfield caption="Window"
-                         mask="0xF0"
-                         name="WINDOW"
-                         rw="RW"
-                         values="WDT_WINDOW"/>
-            </register>
-            <register caption="Status"
-                      initval="0x00"
-                      name="STATUS"
-                      offset="0x1"
-                      rw="RW"
-                      size="1">
-               <bitfield caption="Syncronization busy"
-                         mask="0x01"
-                         name="SYNCBUSY"
-                         rw="R"/>
-               <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
-            </register>
-         </register-group>
-         <value-group caption="Period select" name="WDT_PERIOD">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-         <value-group caption="Window select" name="WDT_WINDOW">
-            <value caption="Off" name="OFF" value="0x00"/>
-            <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
-            <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
-            <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
-            <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
-            <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
-            <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
-            <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
-            <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
-            <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
-            <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
-            <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
-         </value-group>
-      </module>
-   </modules>
-   <pinouts>
-      <pinout name="QFN48">
-         <pin pad="PA5" position="1"/>
-         <pin pad="PA6" position="2"/>
-         <pin pad="PA7" position="3"/>
-         <pin pad="PB0" position="4"/>
-         <pin pad="PB1" position="5"/>
-         <pin pad="PB2" position="6"/>
-         <pin pad="PB3" position="7"/>
-         <pin pad="PB4" position="8"/>
-         <pin pad="PB5" position="9"/>
-         <pin pad="PC0" position="10"/>
-         <pin pad="PC1" position="11"/>
-         <pin pad="PC2" position="12"/>
-         <pin pad="PC3" position="13"/>
-         <pin pad="VDD2" position="14"/>
-         <pin pad="GND2" position="15"/>
-         <pin pad="PC4" position="16"/>
-         <pin pad="PC5" position="17"/>
-         <pin pad="PC6" position="18"/>
-         <pin pad="PC7" position="19"/>
-         <pin pad="PD0" position="20"/>
-         <pin pad="PD1" position="21"/>
-         <pin pad="PD2" position="22"/>
-         <pin pad="PD3" position="23"/>
-         <pin pad="PD4" position="24"/>
-         <pin pad="PD5" position="25"/>
-         <pin pad="PD6" position="26"/>
-         <pin pad="PD7" position="27"/>
-         <pin pad="VDD" position="28"/>
-         <pin pad="GND" position="29"/>
-         <pin pad="PE0" position="30"/>
-         <pin pad="PE1" position="31"/>
-         <pin pad="PE2" position="32"/>
-         <pin pad="PE3" position="33"/>
-         <pin pad="PF0" position="34"/>
-         <pin pad="PF1" position="35"/>
-         <pin pad="PF2" position="36"/>
-         <pin pad="PF3" position="37"/>
-         <pin pad="PF4" position="38"/>
-         <pin pad="PF5" position="39"/>
-         <pin pad="PF6" position="40"/>
-         <pin pad="PF7" position="41"/>
-         <pin pad="VDD1" position="42"/>
-         <pin pad="GND1" position="43"/>
-         <pin pad="PA0" position="44"/>
-         <pin pad="PA1" position="45"/>
-         <pin pad="PA2" position="46"/>
-         <pin pad="PA3" position="47"/>
-         <pin pad="PA4" position="48"/>
-      </pinout>
-   </pinouts>
+        </property-groups>
+    </device>
+    <modules>
+        <module caption="Analog Comparator" id="cmp_control_v8" name="AC">
+            <register-group caption="Analog Comparator" name="AC" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Hysteresis Mode"
+                              mask="0x06"
+                              name="HYSMODE"
+                              rw="RW"
+                              values="AC_HYSMODE"/>
+                    <bitfield caption="Power profile"
+                              mask="0x18"
+                              name="POWER"
+                              rw="RW"
+                              values="AC_POWER"/>
+                    <bitfield caption="Output Pad Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window selection mode"
+                              mask="0x03"
+                              name="WINSEL"
+                              rw="RW"
+                              values="AC_WINSEL"/>
+                </register>
+                <register caption="Mux Control A"
+                          initval="0x00"
+                          name="MUXCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Negative Input MUX Selection"
+                              mask="0x07"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="AC_MUXNEG"/>
+                    <bitfield caption="Positive Input MUX Selection"
+                              mask="0x38"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="AC_MUXPOS"/>
+                    <bitfield caption="AC Output Initial Value"
+                              mask="0x40"
+                              name="INITVAL"
+                              rw="RW"
+                              values="AC_INITVAL"/>
+                    <bitfield caption="Invert AC Output" mask="0x80" name="INVERT" rw="RW"/>
+                </register>
+                <register caption="DAC Voltage Reference"
+                          initval="0xFF"
+                          name="DACREF"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DACREF" mask="0xFF" name="DACREF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="AC.CTRLB.WINSEL" value="0x0"/>
+                    <mode name="WINDOW" qualifier="AC.CTRLB.WINSEL" value="0x1 0x2"/>
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CMP" rw="RW"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_NORMAL_INTMODE"/>
+                    <bitfield caption="Interrupt Mode"
+                              mask="0x30"
+                              modes="WINDOW"
+                              name="INTMODE"
+                              rw="RW"
+                              values="AC_WINDOW_INTMODE"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator Interrupt Flag"
+                              mask="0x01"
+                              name="CMPIF"
+                              rw="RW"/>
+                    <bitfield caption="Analog Comparator State"
+                              mask="0x10"
+                              name="CMPSTATE"
+                              rw="R"/>
+                    <bitfield caption="Analog Comparator Window State"
+                              mask="0xC0"
+                              name="WINSTATE"
+                              rw="R"
+                              values="AC_WINSTATE"/>
+                </register>
+            </register-group>
+            <value-group caption="Hysteresis Mode select" name="AC_HYSMODE">
+                <value caption="No hysteresis" name="NONE" value="0x00"/>
+                <value caption="Small hysteresis" name="SMALL" value="0x01"/>
+                <value caption="Medium hysteresis" name="MEDIUM" value="0x02"/>
+                <value caption="Large hysteresis" name="LARGE" value="0x03"/>
+            </value-group>
+            <value-group caption="Power profile select" name="AC_POWER">
+                <value caption="Power profile 0, Fastest response time, highest consumption"
+                       name="PROFILE0"
+                       value="0x0"/>
+                <value caption="Power profile 1" name="PROFILE1" value="0x1"/>
+            </value-group>
+            <value-group caption="Window selection mode" name="AC_WINSEL">
+                <value caption="Window function disabled" name="DISABLED" value="0x0"/>
+                <value caption="Select ACn+1 as upper limit in window compare"
+                       name="UPSEL1"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_NORMAL_INTMODE">
+                <value caption="Positive and negative inputs crosses"
+                       name="BOTHEDGE"
+                       value="0x0"/>
+                <value caption="Positive input goes below negative input"
+                       name="NEGEDGE"
+                       value="0x2"/>
+                <value caption="Positive input goes above negative input"
+                       name="POSEDGE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode select" name="AC_WINDOW_INTMODE">
+                <value caption="Window interrupt when input above both references"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="Window interrupt when input betweeen references"
+                       name="INSIDE"
+                       value="0x1"/>
+                <value caption="Window interrupt when input below both references"
+                       name="BELOW"
+                       value="0x2"/>
+                <value caption="Window interrupt when input outside reference"
+                       name="OUTSIDE"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="AC Output Initial Value select" name="AC_INITVAL">
+                <value caption="Output initialized to 0" name="LOW" value="0x0"/>
+                <value caption="Output initialized to 1" name="HIGH" value="0x1"/>
+            </value-group>
+            <value-group caption="Negative Input MUX Selection" name="AC_MUXNEG">
+                <value caption="Negative Pin 0" name="AINN0" value="0x00"/>
+                <value caption="Negative Pin 1" name="AINN1" value="0x01"/>
+                <value caption="Negative Pin 2" name="AINN2" value="0x02"/>
+                <value caption="Negative Pin 3" name="AINN3" value="0x03"/>
+                <value caption="DAC Reference" name="DACREF" value="0x04"/>
+            </value-group>
+            <value-group caption="Positive Input MUX Selection" name="AC_MUXPOS">
+                <value caption="Positive Pin 0" name="AINP0" value="0x00"/>
+                <value caption="Positive Pin 1" name="AINP1" value="0x01"/>
+                <value caption="Positive Pin 2" name="AINP2" value="0x02"/>
+                <value caption="Positive Pin 3" name="AINP3" value="0x03"/>
+                <value caption="Positive Pin 4" name="AINP4" value="0x04"/>
+            </value-group>
+            <value-group caption="Analog Comparator Window State select" name="AC_WINSTATE">
+                <value caption="Above window" name="ABOVE" value="0x0"/>
+                <value caption="Inside window" name="INSIDE" value="0x1"/>
+                <value caption="Below window" name="BELOW" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Analog to Digital Converter"
+                id="adc_12b_diff_ctrl_avr_v2"
+                name="ADC">
+            <register-group caption="Analog to Digital Converter" name="ADC" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="ADC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low Latency" mask="0x20" name="LOWLAT" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler Value"
+                              mask="0x0F"
+                              name="PRESC"
+                              rw="RW"
+                              values="ADC_PRESC"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="ADC_REFSEL"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Window Comparator Mode"
+                              mask="0x07"
+                              name="WINCM"
+                              rw="RW"
+                              values="ADC_WINCM"/>
+                    <bitfield caption="Window Mode Source"
+                              mask="0x08"
+                              name="WINSRC"
+                              rw="RW"
+                              values="ADC_WINSRC"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Enable"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Enable"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Enable"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Enable"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Enable"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Enable"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Result Ready Interrupt Flag"
+                              mask="0x01"
+                              name="RESRDY"
+                              rw="RW"/>
+                    <bitfield caption="Sample Ready Interrupt Flag"
+                              mask="0x02"
+                              name="SAMPRDY"
+                              rw="RW"/>
+                    <bitfield caption="Window Comparator Interrupt Flag"
+                              mask="0x04"
+                              name="WCMP"
+                              rw="RW"/>
+                    <bitfield caption="Result Overwrite Interrupt Flag"
+                              mask="0x08"
+                              name="RESOVR"
+                              rw="RW"/>
+                    <bitfield caption="Sample Overwrite Interrupt Flag"
+                              mask="0x10"
+                              name="SAMPOVR"
+                              rw="RW"/>
+                    <bitfield caption="Trigger Overrun Interrupt Flag"
+                              mask="0x20"
+                              name="TRIGOVR"
+                              rw="RW"/>
+                </register>
+                <register caption="Status register"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="ADC Busy" mask="0x01" name="ADCBUSY" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in Debug Mode" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Control E"
+                          initval="0x00"
+                          name="CTRLE"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample Duration" mask="0xFF" name="SAMPDUR" rw="RW"/>
+                </register>
+                <register caption="Control F"
+                          initval="0x00"
+                          name="CTRLF"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sample numbers"
+                              mask="0x0F"
+                              name="SAMPNUM"
+                              rw="RW"
+                              values="ADC_SAMPNUM"/>
+                    <bitfield caption="Left Adjust" mask="0x10" name="LEFTADJ" rw="RW"/>
+                    <bitfield caption="Free-Running mode" mask="0x20" name="FREERUN" rw="RW"/>
+                    <bitfield caption="Sign Chopping"
+                              mask="0x40"
+                              name="CHOPPING"
+                              rw="RW"
+                              values="ADC_CHOPPING"/>
+                </register>
+                <register caption="Command register"
+                          initval="0x00"
+                          name="COMMAND"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Start command"
+                              mask="0x07"
+                              name="START"
+                              rw="RW"
+                              values="ADC_START"/>
+                    <bitfield caption="Mode"
+                              mask="0x70"
+                              name="MODE"
+                              rw="RW"
+                              values="ADC_MODE"/>
+                    <bitfield caption="Differential mode" mask="0x80" name="DIFF" rw="RW"/>
+                </register>
+                <register caption="PGA Control"
+                          initval="0x00"
+                          name="PGACTRL"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="PGA Enable" mask="0x01" name="PGAEN" rw="RW"/>
+                    <bitfield caption="PGA BIAS Select"
+                              mask="0x18"
+                              name="PGABIASSEL"
+                              rw="RW"
+                              values="ADC_PGABIASSEL"/>
+                    <bitfield caption="Gain"
+                              mask="0xE0"
+                              name="GAIN"
+                              rw="RW"
+                              values="ADC_GAIN"/>
+                </register>
+                <register caption="Positive Input Multiplexer"
+                          initval="0x00"
+                          name="MUXPOS"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXPOS"
+                              rw="RW"
+                              values="ADC_MUXPOS"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Negative Input Multiplexer"
+                          initval="0x00"
+                          name="MUXNEG"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Channel Selection Bits"
+                              mask="0x3F"
+                              name="MUXNEG"
+                              rw="RW"
+                              values="ADC_MUXNEG"/>
+                    <bitfield caption="VIA"
+                              mask="0xC0"
+                              name="VIA"
+                              rw="RW"
+                              values="ADC_VIA"/>
+                </register>
+                <register caption="Result"
+                          initval="0x00000000"
+                          name="RESULT"
+                          offset="0x10"
+                          rw="R"
+                          size="4"/>
+                <register caption="Sample"
+                          initval="0x0000"
+                          name="SAMPLE"
+                          offset="0x14"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temporary Data 0"
+                          initval="0x00"
+                          name="TEMP0"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 1"
+                          initval="0x00"
+                          name="TEMP1"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Temporary Data 2"
+                          initval="0x00"
+                          name="TEMP2"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Window Low Threshold"
+                          initval="0x0000"
+                          name="WINLT"
+                          offset="0x1C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Window High Threshold"
+                          initval="0x0000"
+                          name="WINHT"
+                          offset="0x1E"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Mode select" name="ADC_MODE">
+                <value caption="Single Conversion with 8-bit resolution"
+                       name="SINGLE_8BIT"
+                       value="0x00"/>
+                <value caption="Single Conversion with 12-bit resolution"
+                       name="SINGLE_12BIT"
+                       value="0x01"/>
+                <value caption="Series with accumulation, separate trigger for every 12-bit conversion"
+                       name="SERIES"
+                       value="0x02"/>
+                <value caption="Series with accumulation and scaling, separate trigger for every 12-bit conversion"
+                       name="SERIES_SCALING"
+                       value="0x03"/>
+                <value caption="Burst with accumulation, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST"
+                       value="0x04"/>
+                <value caption="Burst with accumulation and scaling, one trigger will run SAMPNUM 12-bit conversions"
+                       name="BURST_SCALING"
+                       value="0x05"/>
+            </value-group>
+            <value-group caption="Start command select" name="ADC_START">
+                <value caption="Stop an ongoing conversion" name="STOP" value="0x00"/>
+                <value caption="Start a conversion immediately. This will be set back to STOP when the first conversion is done, unless Free-Running mode is enabled"
+                       name="IMMEDIATE"
+                       value="0x01"/>
+                <value caption="Start when MUXPOS register is written"
+                       name="MUXPOS_WRITE"
+                       value="0x02"/>
+                <value caption="Start when MUXNEG register is written"
+                       name="MUXNEG_WRITE"
+                       value="0x03"/>
+                <value caption="Start when an event is received"
+                       name="EVENT_TRIGGER"
+                       value="0x04"/>
+            </value-group>
+            <value-group caption="Prescaler Value select" name="ADC_PRESC">
+                <value caption="System clock divided by 2" name="DIV2" value="0x00"/>
+                <value caption="System clock divided by 4" name="DIV4" value="0x01"/>
+                <value caption="System clock divided by 6" name="DIV6" value="0x02"/>
+                <value caption="System clock divided by 8" name="DIV8" value="0x03"/>
+                <value caption="System clock divided by 10" name="DIV10" value="0x04"/>
+                <value caption="System clock divided by 12" name="DIV12" value="0x05"/>
+                <value caption="System clock divided by 14" name="DIV14" value="0x06"/>
+                <value caption="System clock divided by 16" name="DIV16" value="0x07"/>
+                <value caption="System clock divided by 20" name="DIV20" value="0x08"/>
+                <value caption="System clock divided by 24" name="DIV24" value="0x09"/>
+                <value caption="System clock divided by 28" name="DIV28" value="0x0A"/>
+                <value caption="System clock divided by 32" name="DIV32" value="0x0B"/>
+                <value caption="System clock divided by 40" name="DIV40" value="0x0C"/>
+                <value caption="System clock divided by 48" name="DIV48" value="0x0D"/>
+                <value caption="System clock divided by 56" name="DIV56" value="0x0E"/>
+                <value caption="System clock divided by 64" name="DIV64" value="0x0F"/>
+            </value-group>
+            <value-group caption="Reference select" name="ADC_REFSEL">
+                <value caption="VDD" name="VDD" value="0x00"/>
+                <value caption="External Reference" name="VREFA" value="0x02"/>
+                <value caption="Internal 1.024V Reference" name="1V024" value="0x04"/>
+                <value caption="Internal 2.048V Reference" name="2V048" value="0x05"/>
+                <value caption="Internal 4.096V Reference" name="4V096" value="0x06"/>
+                <value caption="Internal 2.500V Reference" name="2V500" value="0x07"/>
+            </value-group>
+            <value-group caption="Window Comparator Mode select" name="ADC_WINCM">
+                <value caption="No Window Comparison" name="NONE" value="0x00"/>
+                <value caption="Below Window" name="BELOW" value="0x01"/>
+                <value caption="Above Window" name="ABOVE" value="0x02"/>
+                <value caption="Inside Window" name="INSIDE" value="0x03"/>
+                <value caption="Outside Window" name="OUTSIDE" value="0x04"/>
+            </value-group>
+            <value-group caption="Window Mode Source select" name="ADC_WINSRC">
+                <value caption="Result register used as Window Comparator Source"
+                       name="RESULT"
+                       value="0x0"/>
+                <value caption="Sample register used as Window Comparator Source"
+                       name="SAMPLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Sign Chopping select" name="ADC_CHOPPING">
+                <value caption="Sign Chopping Disabled" name="DISABLE" value="0x0"/>
+                <value caption="Sign Chopping Enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Sample numbers select" name="ADC_SAMPNUM">
+                <value caption="No accumulation" name="NONE" value="0x0"/>
+                <value caption="2 samples accumulated" name="ACC2" value="0x1"/>
+                <value caption="4 samples accumulated" name="ACC4" value="0x2"/>
+                <value caption="8 samples accumulated" name="ACC8" value="0x3"/>
+                <value caption="16 samples accumulated" name="ACC16" value="0x4"/>
+                <value caption="32 samples accumulated" name="ACC32" value="0x5"/>
+                <value caption="64 samples accumulated" name="ACC64" value="0x6"/>
+                <value caption="128 samples accumulated" name="ACC128" value="0x7"/>
+                <value caption="256 samples accumulated" name="ACC256" value="0x8"/>
+                <value caption="512 samples accumulated" name="ACC512" value="0x9"/>
+                <value caption="1024 samples accumulated" name="ACC1024" value="0xA"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXNEG">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 8" name="AIN8" value="0x08"/>
+                <value caption="ADC input pin 9" name="AIN9" value="0x09"/>
+                <value caption="ADC input pin 10" name="AIN10" value="0x0A"/>
+                <value caption="ADC input pin 11" name="AIN11" value="0x0B"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+                <value caption="AC0 DAC reference" name="DACREF0" value="0x39"/>
+                <value caption="AC1 DAC reference" name="DACREF1" value="0x3A"/>
+            </value-group>
+            <value-group caption="VIA select" name="ADC_VIA">
+                <value caption="Inputs connected directly to ADC"
+                       name="DIRECT"
+                       value="0x0"/>
+                <value caption="Inputs connected via PGA" name="PGA" value="0x1"/>
+            </value-group>
+            <value-group caption="Analog Channel Selection Bits" name="ADC_MUXPOS">
+                <value caption="ADC input pin 0" name="AIN0" value="0x00"/>
+                <value caption="ADC input pin 1" name="AIN1" value="0x01"/>
+                <value caption="ADC input pin 2" name="AIN2" value="0x02"/>
+                <value caption="ADC input pin 3" name="AIN3" value="0x03"/>
+                <value caption="ADC input pin 4" name="AIN4" value="0x04"/>
+                <value caption="ADC input pin 5" name="AIN5" value="0x05"/>
+                <value caption="ADC input pin 6" name="AIN6" value="0x06"/>
+                <value caption="ADC input pin 7" name="AIN7" value="0x07"/>
+                <value caption="ADC input pin 8" name="AIN8" value="0x08"/>
+                <value caption="ADC input pin 9" name="AIN9" value="0x09"/>
+                <value caption="ADC input pin 10" name="AIN10" value="0x0A"/>
+                <value caption="ADC input pin 11" name="AIN11" value="0x0B"/>
+                <value caption="ADC input pin 16" name="AIN16" value="0x10"/>
+                <value caption="ADC input pin 17" name="AIN17" value="0x11"/>
+                <value caption="ADC input pin 18" name="AIN18" value="0x12"/>
+                <value caption="ADC input pin 19" name="AIN19" value="0x13"/>
+                <value caption="ADC input pin 20" name="AIN20" value="0x14"/>
+                <value caption="ADC input pin 21" name="AIN21" value="0x15"/>
+                <value caption="ADC input pin 22" name="AIN22" value="0x16"/>
+                <value caption="ADC input pin 23" name="AIN23" value="0x17"/>
+                <value caption="ADC input pin 24" name="AIN24" value="0x18"/>
+                <value caption="ADC input pin 25" name="AIN25" value="0x19"/>
+                <value caption="ADC input pin 26" name="AIN26" value="0x1A"/>
+                <value caption="ADC input pin 27" name="AIN27" value="0x1B"/>
+                <value caption="ADC input pin 28" name="AIN28" value="0x1C"/>
+                <value caption="ADC input pin 29" name="AIN29" value="0x1D"/>
+                <value caption="ADC input pin 30" name="AIN30" value="0x1E"/>
+                <value caption="ADC input pin 31" name="AIN31" value="0x1F"/>
+                <value caption="Ground" name="GND" value="0x30"/>
+                <value caption="VDD Divided by 10" name="VDD10" value="0x31"/>
+                <value caption="Temperature Sensor" name="TEMPSENSE" value="0x32"/>
+                <value caption="Digital to Analog Converter 0" name="DAC0" value="0x38"/>
+            </value-group>
+            <value-group caption="Gain select" name="ADC_GAIN">
+                <value caption="1x gain" name="1X" value="0x0"/>
+                <value caption="2x gain" name="2X" value="0x1"/>
+                <value caption="4x gain" name="4X" value="0x2"/>
+                <value caption="8x gain" name="8X" value="0x3"/>
+                <value caption="16x gain" name="16X" value="0x4"/>
+            </value-group>
+            <value-group caption="PGA BIAS Select" name="ADC_PGABIASSEL">
+                <value caption="100% BIAS current." name="100PCT" value="0x0"/>
+                <value caption="75% BIAS current. Usable for CLK_ADC&lt;4.5MHz"
+                       name="75PCT"
+                       value="0x1"/>
+                <value caption="50% BIAS current. Usable for CLK_ADC&lt;3MHz"
+                       name="50PCT"
+                       value="0x2"/>
+                <value caption="25% BIAS current. Usable for CLK_ADC&lt;1.5MHz"
+                       name="25PCT"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Bod interface" id="bor_lvd_ctrl_avr_v2" name="BOD">
+            <register-group caption="Bod interface" name="BOD" size="0x10">
+                <register caption="Control A"
+                          initval="0x01"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Operation in sleep mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="BOD_SLEEP"/>
+                    <bitfield caption="Operation in active mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="R"
+                              values="BOD_ACTIVE"/>
+                    <bitfield caption="Sample frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="R"
+                              values="BOD_SAMPFREQ"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bod level"
+                              mask="0x07"
+                              name="LVL"
+                              rw="R"
+                              values="BOD_LVL"/>
+                </register>
+                <register caption="Voltage level monitor Control"
+                          initval="0x00"
+                          name="VLMCTRLA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor level"
+                              mask="0x03"
+                              name="VLMLVL"
+                              rw="RW"
+                              values="BOD_VLMLVL"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="voltage level monitor interrrupt enable"
+                              mask="0x01"
+                              name="VLMIE"
+                              rw="RW"/>
+                    <bitfield caption="Configuration"
+                              mask="0x06"
+                              name="VLMCFG"
+                              rw="RW"
+                              values="BOD_VLMCFG"/>
+                </register>
+                <register caption="Voltage level monitor interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor interrupt flag"
+                              mask="0x01"
+                              name="VLMIF"
+                              rw="RW"/>
+                </register>
+                <register caption="Voltage level monitor status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Voltage level monitor status"
+                              mask="0x01"
+                              name="VLMS"
+                              rw="R"
+                              values="BOD_VLMS"/>
+                </register>
+            </register-group>
+            <value-group caption="Operation in active mode select" name="BOD_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Sample frequency select" name="BOD_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="Operation in sleep mode select" name="BOD_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="Bod level select" name="BOD_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="Configuration select" name="BOD_VLMCFG">
+                <value caption="VDD falls below VLM threshold" name="FALLING" value="0x00"/>
+                <value caption="VDD rises above VLM threshold" name="RISING" value="0x01"/>
+                <value caption="VDD crosses VLM threshold" name="BOTH" value="0x02"/>
+            </value-group>
+            <value-group caption="Voltage level monitor status select" name="BOD_VLMS">
+                <value caption="The voltage is above the VLM threshold level"
+                       name="ABOVE"
+                       value="0x0"/>
+                <value caption="The voltage is below the VLM threshold level"
+                       name="BELOW"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="voltage level monitor level select" name="BOD_VLMLVL">
+                <value caption="VLM Disabled" name="OFF" value="0x0"/>
+                <value caption="VLM threshold 5% above BOD level"
+                       name="5ABOVE"
+                       value="0x1"/>
+                <value caption="VLM threshold 15% above BOD level"
+                       name="15ABOVE"
+                       value="0x2"/>
+                <value caption="VLM threshold 25% above BOD level"
+                       name="25ABOVE"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Configurable Custom Logic" id="cla_ccl_v1" name="CCL">
+            <register-group caption="Configurable Custom Logic" name="CCL" size="0x40">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Run in Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Sequential Control 0"
+                          initval="0x00"
+                          name="SEQCTRL0"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Sequential Control 1"
+                          initval="0x00"
+                          name="SEQCTRL1"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sequential Selection"
+                              mask="0x07"
+                              name="SEQSEL"
+                              rw="RW"
+                              values="CCL_SEQSEL"/>
+                </register>
+                <register caption="Interrupt Control 0"
+                          initval="0x00"
+                          name="INTCTRL0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Mode for LUT0"
+                              mask="0x03"
+                              name="INTMODE0"
+                              rw="RW"
+                              values="CCL_INTMODE0"/>
+                    <bitfield caption="Interrupt Mode for LUT1"
+                              mask="0x0C"
+                              name="INTMODE1"
+                              rw="RW"
+                              values="CCL_INTMODE1"/>
+                    <bitfield caption="Interrupt Mode for LUT2"
+                              mask="0x30"
+                              name="INTMODE2"
+                              rw="RW"
+                              values="CCL_INTMODE2"/>
+                    <bitfield caption="Interrupt Mode for LUT3"
+                              mask="0xC0"
+                              name="INTMODE3"
+                              rw="RW"
+                              values="CCL_INTMODE3"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Flag" mask="0x0F" name="INT" rw="RW"/>
+                </register>
+                <register caption="LUT 0 Control A"
+                          initval="0x00"
+                          name="LUT0CTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 0 Control B"
+                          initval="0x00"
+                          name="LUT0CTRLB"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 0 Control C"
+                          initval="0x00"
+                          name="LUT0CTRLC"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 0"
+                          initval="0x00"
+                          name="TRUTH0"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 1 Control A"
+                          initval="0x00"
+                          name="LUT1CTRLA"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 1 Control B"
+                          initval="0x00"
+                          name="LUT1CTRLB"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 1 Control C"
+                          initval="0x00"
+                          name="LUT1CTRLC"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 1"
+                          initval="0x00"
+                          name="TRUTH1"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 2 Control A"
+                          initval="0x00"
+                          name="LUT2CTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 2 Control B"
+                          initval="0x00"
+                          name="LUT2CTRLB"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 2 Control C"
+                          initval="0x00"
+                          name="LUT2CTRLC"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 2"
+                          initval="0x00"
+                          name="TRUTH2"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+                <register caption="LUT 3 Control A"
+                          initval="0x00"
+                          name="LUT3CTRLA"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Source Selection"
+                              mask="0x0E"
+                              name="CLKSRC"
+                              rw="RW"
+                              values="CCL_CLKSRC"/>
+                    <bitfield caption="Filter Selection"
+                              mask="0x30"
+                              name="FILTSEL"
+                              rw="RW"
+                              values="CCL_FILTSEL"/>
+                    <bitfield caption="Output Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Edge Detection Enable"
+                              mask="0x80"
+                              name="EDGEDET"
+                              rw="RW"
+                              values="CCL_EDGEDET"/>
+                </register>
+                <register caption="LUT 3 Control B"
+                          initval="0x00"
+                          name="LUT3CTRLB"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 0 Source Selection"
+                              mask="0x0F"
+                              name="INSEL0"
+                              rw="RW"
+                              values="CCL_INSEL0"/>
+                    <bitfield caption="LUT Input 1 Source Selection"
+                              mask="0xF0"
+                              name="INSEL1"
+                              rw="RW"
+                              values="CCL_INSEL1"/>
+                </register>
+                <register caption="LUT 3 Control C"
+                          initval="0x00"
+                          name="LUT3CTRLC"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="LUT Input 2 Source Selection"
+                              mask="0x0F"
+                              name="INSEL2"
+                              rw="RW"
+                              values="CCL_INSEL2"/>
+                </register>
+                <register caption="Truth 3"
+                          initval="0x00"
+                          name="TRUTH3"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Interrupt Mode for LUT0 select" name="CCL_INTMODE0">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT1 select" name="CCL_INTMODE1">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT2 select" name="CCL_INTMODE2">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Interrupt Mode for LUT3 select" name="CCL_INTMODE3">
+                <value caption="Interrupt disabled" name="INTDISABLE" value="0x0"/>
+                <value caption="Sense rising edge" name="RISING" value="0x1"/>
+                <value caption="Sense falling edge" name="FALLING" value="0x2"/>
+                <value caption="Sense both edges" name="BOTH" value="0x3"/>
+            </value-group>
+            <value-group caption="Clock Source Selection" name="CCL_CLKSRC">
+                <value caption="Peripheral Clock" name="CLKPER" value="0x0"/>
+                <value caption="INSEL2 selection" name="IN2" value="0x1"/>
+                <value caption="Internal High Frequency oscillator"
+                       name="OSCHF"
+                       value="0x4"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x5"/>
+                <value caption="Internal 32.768 kHz oscillator divided by 32"
+                       name="OSC1K"
+                       value="0x6"/>
+            </value-group>
+            <value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
+                <value caption="Edge detector is disabled" name="DIS" value="0x0"/>
+                <value caption="Edge detector is enabled" name="EN" value="0x1"/>
+            </value-group>
+            <value-group caption="Filter Selection" name="CCL_FILTSEL">
+                <value caption="Filter disabled" name="DISABLE" value="0x0"/>
+                <value caption="Synchronizer enabled" name="SYNCH" value="0x1"/>
+                <value caption="Filter enabled" name="FILTER" value="0x2"/>
+            </value-group>
+            <value-group caption="LUT Input 0 Source Selection" name="CCL_INSEL0">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC0 output input source" name="AC0" value="0x6"/>
+                <value caption="USART0 TxD input source" name="USART0" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO0 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO0 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB0 WO input source" name="TCB0" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 1 Source Selection" name="CCL_INSEL1">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART1 TxD input source" name="USART1" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO1 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO1 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB1 WO input source" name="TCB1" value="0xB"/>
+            </value-group>
+            <value-group caption="LUT Input 2 Source Selection" name="CCL_INSEL2">
+                <value caption="Masked input" name="MASK" value="0x0"/>
+                <value caption="Feedback input" name="FEEDBACK" value="0x1"/>
+                <value caption="Output from LUT[n+1] as input source"
+                       name="LINK"
+                       value="0x2"/>
+                <value caption="Event A as input source" name="EVENTA" value="0x3"/>
+                <value caption="Event B as input source" name="EVENTB" value="0x4"/>
+                <value caption="IN0 input source" name="IO" value="0x5"/>
+                <value caption="AC1 output input source" name="AC1" value="0x6"/>
+                <value caption="USART2 TxD input source" name="USART2" value="0x7"/>
+                <value caption="SPI0 MISO input source" name="SPI0" value="0x8"/>
+                <value caption="TCA0 WO2 input source" name="TCA0" value="0x9"/>
+                <value caption="TCA1 WO2 input source" name="TCA1" value="0xA"/>
+                <value caption="TCB2 WO input source" name="TCB2" value="0xB"/>
+            </value-group>
+            <value-group caption="Sequential Selection" name="CCL_SEQSEL">
+                <value caption="Sequential logic disabled" name="DISABLE" value="0x00"/>
+                <value caption="D FlipFlop" name="DFF" value="0x01"/>
+                <value caption="JK FlipFlop" name="JK" value="0x02"/>
+                <value caption="D Latch" name="LATCH" value="0x03"/>
+                <value caption="RS Latch" name="RS" value="0x04"/>
+            </value-group>
+        </module>
+        <module caption="Clock controller" id="avrea" name="CLKCTRL">
+            <register-group caption="Clock controller" name="CLKCTRL" size="0x20">
+                <register caption="MCLK Control A"
+                          initval="0x00"
+                          name="MCLKCTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock select"
+                              mask="0x07"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="CLKCTRL_CLKSEL"/>
+                    <bitfield caption="System clock out" mask="0x80" name="CLKOUT" rw="RW"/>
+                </register>
+                <register caption="MCLK Control B"
+                          initval="0x11"
+                          name="MCLKCTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Prescaler enable" mask="0x01" name="PEN" rw="RW"/>
+                    <bitfield caption="Prescaler division"
+                              mask="0x1E"
+                              name="PDIV"
+                              rw="RW"
+                              values="CLKCTRL_PDIV"/>
+                </register>
+                <register caption="MCLK Control C"
+                          initval="0x00"
+                          name="MCLKCTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detect Enable"
+                              mask="0x01"
+                              name="CFDEN"
+                              rw="RW"/>
+                    <bitfield caption="CFD Test" mask="0x02" name="CFDTST" rw="RW"/>
+                    <bitfield caption="CFD Source"
+                              mask="0x0C"
+                              name="CFDSRC"
+                              rw="RW"
+                              values="CLKCTRL_CFDSRC"/>
+                </register>
+                <register caption="MCLK Interrupt Control"
+                          initval="0x00"
+                          name="MCLKINTCTRL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="CFD" rw="RW"/>
+                    <bitfield caption="Interrupt Type"
+                              mask="0x80"
+                              name="INTTYPE"
+                              rw="RW"
+                              values="CLKCTRL_INTTYPE"/>
+                </register>
+                <register caption="MCLK Interrupt Flags"
+                          initval="0x00"
+                          name="MCLKINTFLAGS"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Failure Detected" mask="0x01" name="CFD" rw="RW"/>
+                </register>
+                <register caption="MCLK Status"
+                          initval="0x00"
+                          name="MCLKSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="System Oscillator changing"
+                              mask="0x01"
+                              name="SOSC"
+                              rw="R"/>
+                    <bitfield caption="High frequency oscillator status"
+                              mask="0x02"
+                              name="OSCHFS"
+                              rw="R"/>
+                    <bitfield caption="32KHz oscillator status"
+                              mask="0x04"
+                              name="OSC32KS"
+                              rw="R"/>
+                    <bitfield caption="32.768 kHz Crystal Oscillator status"
+                              mask="0x08"
+                              name="XOSC32KS"
+                              rw="R"/>
+                    <bitfield caption="External Clock status / XOSCHF status"
+                              mask="0x10"
+                              name="EXTS"
+                              rw="R"/>
+                </register>
+                <register caption="MCLK Timebase"
+                          initval="0x00"
+                          name="MCLKTIMEBASE"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timebase" mask="0x1F" name="TIMEBASE" rw="RW"/>
+                </register>
+                <register caption="OSCHF Control A"
+                          initval="0x0C"
+                          name="OSCHFCTRLA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Automatic Oscillator Tune"
+                              mask="0x03"
+                              name="AUTOTUNE"
+                              rw="RW"
+                              values="CLKCTRL_AUTOTUNE"/>
+                    <bitfield caption="Run in standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="OSCHF Tune"
+                          initval="0x00"
+                          name="OSCHFTUNE"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Oscillator Tune" mask="0xFF" name="TUNE" rw="RW"/>
+                </register>
+                <register caption="OSC32K Control A"
+                          initval="0x00"
+                          name="OSC32KCTRLA"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSC32K Control A"
+                          initval="0x00"
+                          name="XOSC32KCTRLA"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Low power mode" mask="0x02" name="LPMODE" rw="RW"/>
+                    <bitfield caption="Select" mask="0x04" name="SEL" rw="RW"/>
+                    <bitfield caption="Crystal startup time"
+                              mask="0x30"
+                              name="CSUT"
+                              rw="RW"
+                              values="CLKCTRL_CSUT"/>
+                    <bitfield caption="Run standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="XOSCHF Control A"
+                          initval="0x00"
+                          name="XOSCHFCTRLA"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Source Select"
+                              mask="0x02"
+                              name="SELHF"
+                              rw="RW"
+                              values="CLKCTRL_SELHF"/>
+                    <bitfield caption="Start-Up Time"
+                              mask="0x30"
+                              name="CSUTHF"
+                              rw="RW"
+                              values="CLKCTRL_CSUTHF"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock select" name="CLKCTRL_CLKSEL">
+                <value caption="Internal high-frequency oscillator"
+                       name="OSCHF"
+                       value="0x0"/>
+                <value caption="Internal 32.768 kHz oscillator" name="OSC32K" value="0x1"/>
+                <value caption="32.768 kHz crystal oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaler division select" name="CLKCTRL_PDIV">
+                <value caption="Divide by 2" name="DIV2" value="0x00"/>
+                <value caption="Divide by 4" name="DIV4" value="0x01"/>
+                <value caption="Divide by 8" name="DIV8" value="0x02"/>
+                <value caption="Divide by 16" name="DIV16" value="0x03"/>
+                <value caption="Divide by 32" name="DIV32" value="0x04"/>
+                <value caption="Divide by 64" name="DIV64" value="0x05"/>
+                <value caption="Divide by 6" name="DIV6" value="0x08"/>
+                <value caption="Divide by 10" name="DIV10" value="0x09"/>
+                <value caption="Divide by 12" name="DIV12" value="0x0A"/>
+                <value caption="Divide by 24" name="DIV24" value="0x0B"/>
+                <value caption="Divide by 48" name="DIV48" value="0x0C"/>
+            </value-group>
+            <value-group caption="CFD Source select" name="CLKCTRL_CFDSRC">
+                <value caption="Main Clock" name="CLKMAIN" value="0x0"/>
+                <value caption="High Frequency Crystal Oscillator"
+                       name="XOSCHF"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+            </value-group>
+            <value-group caption="Interrupt Type select" name="CLKCTRL_INTTYPE">
+                <value caption="Regular interrupt" name="INT" value="0x0"/>
+                <value caption="Non-maskable interrupt" name="NMI" value="0x1"/>
+            </value-group>
+            <value-group caption="Automatic Oscillator Tune select" name="CLKCTRL_AUTOTUNE">
+                <value caption="Disabled" name="OFF" value="0x0"/>
+                <value caption="Tune against 32.768 kHz Crystal Oscillator"
+                       name="XOSC32K"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Start-Up Time select" name="CLKCTRL_CSUTHF">
+                <value caption="256 XOSCHF Cycles" name="256CYC" value="0x0"/>
+                <value caption="1K XOSCHF Cycles" name="1KCYC" value="0x1"/>
+                <value caption="4K XOSCHF Cycles" name="4KCYC" value="0x2"/>
+            </value-group>
+            <value-group caption="Source Select" name="CLKCTRL_SELHF">
+                <value caption="External Crystal" name="CRYSTAL" value="0x0"/>
+                <value caption="Extenal Clock on XTALHF1 pin" name="EXTCLK" value="0x1"/>
+            </value-group>
+            <value-group caption="Crystal startup time select" name="CLKCTRL_CSUT">
+                <value caption="1k cycles" name="1K" value="0x00"/>
+                <value caption="16k cycles" name="16K" value="0x01"/>
+                <value caption="32k cycles" name="32K" value="0x02"/>
+                <value caption="64k cycles" name="64K" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="CPU" id="cpu_avr_xt_v1" name="CPU">
+            <register-group caption="CPU" name="CPU" size="0x10">
+                <register caption="Configuration Change Protection"
+                          initval="0x00"
+                          name="CCP"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCP signature"
+                              mask="0xFF"
+                              name="CCP"
+                              rw="RW"
+                              values="CPU_CCP"/>
+                </register>
+                <register caption="Stack Pointer"
+                          initval="0x7FFF"
+                          name="SP"
+                          offset="0xD"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Status Register"
+                          initval="0x00"
+                          name="SREG"
+                          offset="0xF"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Carry Flag" mask="0x01" name="C" rw="RW"/>
+                    <bitfield caption="Zero Flag" mask="0x02" name="Z" rw="RW"/>
+                    <bitfield caption="Negative Flag" mask="0x04" name="N" rw="RW"/>
+                    <bitfield caption="Two's Complement Overflow Flag"
+                              mask="0x08"
+                              name="V"
+                              rw="RW"/>
+                    <bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S" rw="RW"/>
+                    <bitfield caption="Half Carry Flag" mask="0x20" name="H" rw="RW"/>
+                    <bitfield caption="Transfer Bit" mask="0x40" name="T" rw="RW"/>
+                    <bitfield caption="Global Interrupt Enable Flag"
+                              mask="0x80"
+                              name="I"
+                              rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="CCP signature select" name="CPU_CCP">
+                <value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
+                <value caption="IO Register Protection" name="IOREG" value="0xD8"/>
+            </value-group>
+        </module>
+        <module caption="Interrupt Controller" id="int_8bit_v3" name="CPUINT">
+            <register-group caption="Interrupt Controller" name="CPUINT" size="0x4">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Round-robin Scheduling Enable"
+                              mask="0x01"
+                              name="LVL0RR"
+                              rw="RW"/>
+                    <bitfield caption="Compact Vector Table" mask="0x20" name="CVT" rw="RW"/>
+                    <bitfield caption="Interrupt Vector Select"
+                              mask="0x40"
+                              name="IVSEL"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Level 0 Interrupt Executing"
+                              mask="0x01"
+                              name="LVL0EX"
+                              rw="R"/>
+                    <bitfield caption="Level 1 Interrupt Executing"
+                              mask="0x02"
+                              name="LVL1EX"
+                              rw="R"/>
+                    <bitfield caption="Non-maskable Interrupt Executing"
+                              mask="0x80"
+                              name="NMIEX"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Level 0 Priority"
+                          initval="0x00"
+                          name="LVL0PRI"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Level Priority"
+                              mask="0xFF"
+                              name="LVL0PRI"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Level 1 Priority Vector"
+                          initval="0x00"
+                          name="LVL1VEC"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Vector with High Priority"
+                              mask="0xFF"
+                              name="LVL1VEC"
+                              rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="CRCSCAN" id="math_pdi_crc_v1" name="CRCSCAN">
+            <register-group caption="CRCSCAN" name="CRCSCAN" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable CRC scan" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Enable NMI Trigger" mask="0x02" name="NMIEN" rw="RW"/>
+                    <bitfield caption="Reset CRC scan" mask="0x80" name="RESET" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CRC Source"
+                              mask="0x03"
+                              name="SRC"
+                              rw="RW"
+                              values="CRCSCAN_SRC"/>
+                </register>
+                <register caption="Status"
+                          initval="0x02"
+                          name="STATUS"
+                          offset="0x2"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CRC Busy" mask="0x01" name="BUSY" rw="R"/>
+                    <bitfield caption="CRC Ok" mask="0x02" name="OK" rw="R"/>
+                </register>
+            </register-group>
+            <value-group caption="CRC Source select" name="CRCSCAN_SRC">
+                <value caption="CRC on entire flash" name="FLASH" value="0x0"/>
+                <value caption="CRC on boot and appl section of flash"
+                       name="APPLICATION"
+                       value="0x1"/>
+                <value caption="CRC on boot section of flash" name="BOOT" value="0x2"/>
+            </value-group>
+        </module>
+        <module caption="Digital to Analog Converter"
+                id="dac_nbit_ctrl_avr_v6"
+                name="DAC">
+            <register-group caption="Digital to Analog Converter" name="DAC" size="0x10">
+                <register caption="Control Register A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="DAC Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Output Buffer Range"
+                              mask="0x30"
+                              name="OUTRANGE"
+                              rw="RW"
+                              values="DAC_OUTRANGE"/>
+                    <bitfield caption="Output Buffer Enable" mask="0x40" name="OUTEN" rw="RW"/>
+                    <bitfield caption="Run in Standby Mode"
+                              mask="0x80"
+                              name="RUNSTDBY"
+                              rw="RW"/>
+                </register>
+                <register caption="DATA Register"
+                          name="DATA"
+                          offset="0x2"
+                          rw="RW"
+                          size="2">
+                    <bitfield caption="Data" mask="0xFFC0" name="DATA" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Output Buffer Range select" name="DAC_OUTRANGE">
+                <value caption="Output buffer automatically choose best range"
+                       name="AUTO"
+                       value="0x0"/>
+                <value caption="Output buffer configured to low range"
+                       name="LOW"
+                       value="0x2"/>
+                <value caption="Output buffer configured to high range"
+                       name="HIGH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Event System" id="avrea" name="EVSYS">
+            <register-group caption="Event System" name="EVSYS" size="0x40">
+                <register caption="Software Event A"
+                          initval="0x00"
+                          name="SWEVENTA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software event on channel select"
+                              mask="0xFF"
+                              name="SWEVENTA"
+                              rw="W"
+                              values="EVSYS_SWEVENTA"/>
+                </register>
+                <register caption="Multiplexer Channel 0"
+                          initval="0x00"
+                          name="CHANNEL0"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 1"
+                          initval="0x00"
+                          name="CHANNEL1"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 2"
+                          initval="0x00"
+                          name="CHANNEL2"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 3"
+                          initval="0x00"
+                          name="CHANNEL3"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 4"
+                          initval="0x00"
+                          name="CHANNEL4"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="Multiplexer Channel 5"
+                          initval="0x00"
+                          name="CHANNEL5"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Channel generator select"
+                              mask="0xFF"
+                              name="CHANNEL"
+                              rw="RW"
+                              values="EVSYS_CHANNEL"/>
+                </register>
+                <register caption="CCL0 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT0A"
+                          offset="0x20"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL0 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT0B"
+                          offset="0x21"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT1A"
+                          offset="0x22"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL1 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT1B"
+                          offset="0x23"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT2A"
+                          offset="0x24"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL2 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT2B"
+                          offset="0x25"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event A"
+                          initval="0x00"
+                          name="USERCCLLUT3A"
+                          offset="0x26"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="CCL3 Event B"
+                          initval="0x00"
+                          name="USERCCLLUT3B"
+                          offset="0x27"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="ADC0"
+                          initval="0x00"
+                          name="USERADC0START"
+                          offset="0x28"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTA"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTA"
+                          offset="0x29"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTB"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTB"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTC"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTC"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTD"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTD"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTE"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTE"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="EVOUTF"
+                          initval="0x00"
+                          name="USEREVSYSEVOUTF"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART0"
+                          initval="0x00"
+                          name="USERUSART0IRDA"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART1"
+                          initval="0x00"
+                          name="USERUSART1IRDA"
+                          offset="0x30"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="USART2"
+                          initval="0x00"
+                          name="USERUSART2IRDA"
+                          offset="0x31"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event A"
+                          initval="0x00"
+                          name="USERTCA0CNTA"
+                          offset="0x32"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA0 Event B"
+                          initval="0x00"
+                          name="USERTCA0CNTB"
+                          offset="0x33"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event A"
+                          initval="0x00"
+                          name="USERTCA1CNTA"
+                          offset="0x34"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCA1 Event B"
+                          initval="0x00"
+                          name="USERTCA1CNTB"
+                          offset="0x35"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event A"
+                          initval="0x00"
+                          name="USERTCB0CAPT"
+                          offset="0x36"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB0 Event B"
+                          initval="0x00"
+                          name="USERTCB0COUNT"
+                          offset="0x37"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event A"
+                          initval="0x00"
+                          name="USERTCB1CAPT"
+                          offset="0x38"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB1 Event B"
+                          initval="0x00"
+                          name="USERTCB1COUNT"
+                          offset="0x39"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event A"
+                          initval="0x00"
+                          name="USERTCB2CAPT"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB2 Event B"
+                          initval="0x00"
+                          name="USERTCB2COUNT"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event A"
+                          initval="0x00"
+                          name="USERTCB3CAPT"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+                <register caption="TCB3 Event B"
+                          initval="0x00"
+                          name="USERTCB3COUNT"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="User channel select"
+                              mask="0xFF"
+                              name="USER"
+                              rw="RW"
+                              values="EVSYS_USER"/>
+                </register>
+            </register-group>
+            <value-group caption="Channel generator select" name="EVSYS_CHANNEL">
+                <value caption="Off" name="OFF" value="0x0"/>
+                <value caption="UPDI SYNCH character" name="UPDI_SYNCH" value="0x1"/>
+                <value caption="Real Time Counter overflow" name="RTC_OVF" value="0x6"/>
+                <value caption="Real Time Counter compare" name="RTC_CMP" value="0x7"/>
+                <value caption="Periodic Interrupt Timer Event 0"
+                       name="RTC_PITEV0"
+                       value="0x8"/>
+                <value caption="Periodic Interrupt Timer Event 1"
+                       name="RTC_PITEV1"
+                       value="0x9"/>
+                <value caption="Configurable Custom Logic LUT0"
+                       name="CCL_LUT0"
+                       value="0x10"/>
+                <value caption="Configurable Custom Logic LUT1"
+                       name="CCL_LUT1"
+                       value="0x11"/>
+                <value caption="Configurable Custom Logic LUT2"
+                       name="CCL_LUT2"
+                       value="0x12"/>
+                <value caption="Configurable Custom Logic LUT3"
+                       name="CCL_LUT3"
+                       value="0x13"/>
+                <value caption="Analog Comparator 0 out" name="AC0_OUT" value="0x20"/>
+                <value caption="Analog Comparator 1 out" name="AC1_OUT" value="0x21"/>
+                <value caption="ADC 0 Result Ready" name="ADC0_RES" value="0x24"/>
+                <value caption="ADC 0 Sample Ready" name="ADC0_SAMP" value="0x25"/>
+                <value caption="ADC 0 Window Compare" name="ADC0_WCMP" value="0x26"/>
+                <value caption="Port A Event 0" name="PORTA_EV0" value="0x40"/>
+                <value caption="Port A Event 1" name="PORTA_EV1" value="0x41"/>
+                <value caption="Port B Event 0" name="PORTB_EV0" value="0x42"/>
+                <value caption="Port B Event 1" name="PORTB_EV1" value="0x43"/>
+                <value caption="Port C Event 0" name="PORTC_EV0" value="0x44"/>
+                <value caption="Port C Event 1" name="PORTC_EV1" value="0x45"/>
+                <value caption="Port D Event 0" name="PORTD_EV0" value="0x46"/>
+                <value caption="Port D Event 1" name="PORTD_EV1" value="0x47"/>
+                <value caption="Port E Event 0" name="PORTE_EV0" value="0x48"/>
+                <value caption="Port E Event 1" name="PORTE_EV1" value="0x49"/>
+                <value caption="Port F Event 0" name="PORTF_EV0" value="0x4A"/>
+                <value caption="Port F Event 1" name="PORTF_EV1" value="0x4B"/>
+                <value caption="USART 0 XCK" name="USART0_XCK" value="0x60"/>
+                <value caption="USART 1 XCK" name="USART1_XCK" value="0x61"/>
+                <value caption="USART 2 XCK" name="USART2_XCK" value="0x62"/>
+                <value caption="SPI 0 SCK" name="SPI0_SCK" value="0x68"/>
+                <value caption="Timer/Counter A0 overflow / low byte timer underflow"
+                       name="TCA0_OVF_LUNF"
+                       value="0x80"/>
+                <value caption="Timer/Counter A0 high byte timer underflow"
+                       name="TCA0_HUNF"
+                       value="0x81"/>
+                <value caption="Timer/Counter A0 compare 0 / low byte timer compare 0"
+                       name="TCA0_CMP0_LCMP0"
+                       value="0x84"/>
+                <value caption="Timer/Counter A0 compare 1 / low byte timer compare 1"
+                       name="TCA0_CMP1_LCMP1"
+                       value="0x85"/>
+                <value caption="Timer/Counter A0 compare 2 / low byte timer compare 2"
+                       name="TCA0_CMP2_LCMP2"
+                       value="0x86"/>
+                <value caption="Timer/Counter A1 overflow / low byte timer underflow"
+                       name="TCA1_OVF_LUNF"
+                       value="0x88"/>
+                <value caption="Timer/Counter A1 high byte timer underflow"
+                       name="TCA1_HUNF"
+                       value="0x89"/>
+                <value caption="Timer/Counter A1 compare 0 / low byte timer compare 0"
+                       name="TCA1_CMP0_LCMP0"
+                       value="0x8C"/>
+                <value caption="Timer/Counter A1 compare 1 / low byte timer compare 1"
+                       name="TCA1_CMP1_LCMP1"
+                       value="0x8D"/>
+                <value caption="Timer/Counter A1 compare 2 / low byte timer compare 2"
+                       name="TCA1_CMP2_LCMP2"
+                       value="0x8E"/>
+                <value caption="Timer/Counter B0 capture" name="TCB0_CAPT" value="0xA0"/>
+                <value caption="Timer/Counter B0 overflow" name="TCB0_OVF" value="0xA1"/>
+                <value caption="Timer/Counter B1 capture" name="TCB1_CAPT" value="0xA2"/>
+                <value caption="Timer/Counter B1 overflow" name="TCB1_OVF" value="0xA3"/>
+                <value caption="Timer/Counter B2 capture" name="TCB2_CAPT" value="0xA4"/>
+                <value caption="Timer/Counter B2 overflow" name="TCB2_OVF" value="0xA5"/>
+                <value caption="Timer/Counter B3 capture" name="TCB3_CAPT" value="0xA6"/>
+                <value caption="Timer/Counter B3 overflow" name="TCB3_OVF" value="0xA7"/>
+            </value-group>
+            <value-group caption="Software event on channel select" name="EVSYS_SWEVENTA">
+                <value caption="Software event on channel 0" name="CH0" value="0x01"/>
+                <value caption="Software event on channel 1" name="CH1" value="0x02"/>
+                <value caption="Software event on channel 2" name="CH2" value="0x04"/>
+                <value caption="Software event on channel 3" name="CH3" value="0x08"/>
+                <value caption="Software event on channel 4" name="CH4" value="0x10"/>
+                <value caption="Software event on channel 5" name="CH5" value="0x20"/>
+                <value caption="Software event on channel 6" name="CH6" value="0x40"/>
+                <value caption="Software event on channel 7" name="CH7" value="0x80"/>
+            </value-group>
+            <value-group caption="User channel select" name="EVSYS_USER">
+                <value caption="Off, No Eventsys Channel connected" name="OFF" value="0x0"/>
+                <value caption="Connect user to event channel 0"
+                       name="CHANNEL0"
+                       value="0x1"/>
+                <value caption="Connect user to event channel 1"
+                       name="CHANNEL1"
+                       value="0x2"/>
+                <value caption="Connect user to event channel 2"
+                       name="CHANNEL2"
+                       value="0x3"/>
+                <value caption="Connect user to event channel 3"
+                       name="CHANNEL3"
+                       value="0x4"/>
+                <value caption="Connect user to event channel 4"
+                       name="CHANNEL4"
+                       value="0x5"/>
+                <value caption="Connect user to event channel 5"
+                       name="CHANNEL5"
+                       value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Fuses" id="avrea" name="FUSE">
+            <register-group caption="Fuses" name="FUSE" size="0x09">
+                <register caption="Watchdog Configuration"
+                          initval="0x00"
+                          name="WDTCFG"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Watchdog Timeout Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="FUSE_PERIOD"/>
+                    <bitfield caption="Watchdog Window Timeout Period"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="FUSE_WINDOW"/>
+                </register>
+                <register caption="BOD Configuration"
+                          initval="0x00"
+                          name="BODCFG"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="BOD Operation in Sleep Mode"
+                              mask="0x03"
+                              name="SLEEP"
+                              rw="RW"
+                              values="FUSE_SLEEP"/>
+                    <bitfield caption="BOD Operation in Active Mode"
+                              mask="0x0C"
+                              name="ACTIVE"
+                              rw="RW"
+                              values="FUSE_ACTIVE"/>
+                    <bitfield caption="BOD Sample Frequency"
+                              mask="0x10"
+                              name="SAMPFREQ"
+                              rw="RW"
+                              values="FUSE_SAMPFREQ"/>
+                    <bitfield caption="BOD Level"
+                              mask="0xE0"
+                              name="LVL"
+                              rw="RW"
+                              values="FUSE_LVL"/>
+                </register>
+                <register caption="Oscillator Configuration"
+                          initval="0x00"
+                          name="OSCCFG"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="High-frequency Oscillator Frequency"
+                              mask="0x08"
+                              name="OSCHFFRQ"
+                              rw="RW"
+                              values="FUSE_OSCHFFRQ"/>
+                </register>
+                <register caption="System Configuration 0"
+                          initval="0xD0"
+                          name="SYSCFG0"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Save"
+                              mask="0x01"
+                              name="EESAVE"
+                              rw="RW"
+                              values="FUSE_EESAVE"/>
+                    <bitfield caption="Reset Pin Configuration"
+                              mask="0x08"
+                              name="RSTPINCFG"
+                              rw="RW"
+                              values="FUSE_RSTPINCFG"/>
+                    <bitfield caption="UPDI Pin Configuration"
+                              mask="0x10"
+                              name="UPDIPINCFG"
+                              rw="RW"
+                              values="FUSE_UPDIPINCFG"/>
+                    <bitfield caption="CRC Select"
+                              mask="0x20"
+                              name="CRCSEL"
+                              rw="RW"
+                              values="FUSE_CRCSEL"/>
+                    <bitfield caption="CRC Source"
+                              mask="0xC0"
+                              name="CRCSRC"
+                              rw="RW"
+                              values="FUSE_CRCSRC"/>
+                </register>
+                <register caption="System Configuration 1"
+                          initval="0x07"
+                          name="SYSCFG1"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Startup Time"
+                              mask="0x07"
+                              name="SUT"
+                              rw="RW"
+                              values="FUSE_SUT"/>
+                </register>
+                <register caption="Code Section Size"
+                          initval="0x00"
+                          name="CODESIZE"
+                          offset="0x7"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Boot Section Size"
+                          initval="0x00"
+                          name="BOOTSIZE"
+                          offset="0x8"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="BOD Operation in Active Mode select" name="FUSE_ACTIVE">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLED" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLED" value="0x02"/>
+                <value caption="Enabled in continuous mode. Execution halted at wake-up until BOD is running"
+                       name="ENABLEWAIT"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Level select" name="FUSE_LVL">
+                <value caption="BOD Disabled during normal operation"
+                       name="BODLEVEL0"
+                       value="0x00"/>
+                <value caption="1.9 V" name="BODLEVEL1" value="0x01"/>
+                <value caption="2.7 V" name="BODLEVEL2" value="0x02"/>
+                <value caption="4.5 V" name="BODLEVEL3" value="0x03"/>
+            </value-group>
+            <value-group caption="BOD Sample Frequency select" name="FUSE_SAMPFREQ">
+                <value caption="Sampling frequency is 128 Hz" name="128HZ" value="0x0"/>
+                <value caption="Sample frequency is 32 Hz" name="32HZ" value="0x1"/>
+            </value-group>
+            <value-group caption="BOD Operation in Sleep Mode select" name="FUSE_SLEEP">
+                <value caption="Disabled" name="DISABLE" value="0x00"/>
+                <value caption="Enabled in continuous mode" name="ENABLE" value="0x01"/>
+                <value caption="Enabled in sampled mode" name="SAMPLE" value="0x02"/>
+            </value-group>
+            <value-group caption="High-frequency Oscillator Frequency select"
+                         name="FUSE_OSCHFFRQ">
+                <value caption="OSCHF running at 20 MHz" name="20M" value="0x0"/>
+                <value caption="OSCHF running at 16 MHz" name="16M" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Select" name="FUSE_CRCSEL">
+                <value caption="Enable CRC16" name="CRC16" value="0x0"/>
+                <value caption="Enable CRC32" name="CRC32" value="0x1"/>
+            </value-group>
+            <value-group caption="CRC Source select" name="FUSE_CRCSRC">
+                <value caption="CRC of full Flash (boot, application code and application data)"
+                       name="FLASH"
+                       value="0x0"/>
+                <value caption="CRC of boot section" name="BOOT" value="0x1"/>
+                <value caption="CRC of application code and boot sections"
+                       name="BOOTAPP"
+                       value="0x2"/>
+                <value caption="No CRC" name="NOCRC" value="0x3"/>
+            </value-group>
+            <value-group caption="EEPROM Save select" name="FUSE_EESAVE">
+                <value caption="EEPROM content is erased during chip erase"
+                       name="DISABLE"
+                       value="0x0"/>
+                <value caption="EEPROM content is preserved during chip erase"
+                       name="ENABLE"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Reset Pin Configuration select" name="FUSE_RSTPINCFG">
+                <value caption="No External Reset" name="NONE" value="0x0"/>
+                <value caption="PF6 configured as RESET pin" name="RESET" value="0x1"/>
+            </value-group>
+            <value-group caption="UPDI Pin Configuration select" name="FUSE_UPDIPINCFG">
+                <value caption="PF7 Configured as GPIO pin" name="GPIO" value="0x0"/>
+                <value caption="PF7 Configured as UPDI pin" name="UPDI" value="0x1"/>
+            </value-group>
+            <value-group caption="Startup Time select" name="FUSE_SUT">
+                <value caption="0 ms" name="0MS" value="0x00"/>
+                <value caption="1 ms" name="1MS" value="0x01"/>
+                <value caption="2 ms" name="2MS" value="0x02"/>
+                <value caption="4 ms" name="4MS" value="0x03"/>
+                <value caption="8 ms" name="8MS" value="0x04"/>
+                <value caption="16 ms" name="16MS" value="0x05"/>
+                <value caption="32 ms" name="32MS" value="0x06"/>
+                <value caption="64 ms" name="64MS" value="0x07"/>
+            </value-group>
+            <value-group caption="Watchdog Timeout Period select" name="FUSE_PERIOD">
+                <value caption="Watch-Dog timer Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Watchdog Window Timeout Period select" name="FUSE_WINDOW">
+                <value caption="Window mode off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.0s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.0s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+        <module caption="General Purpose Registers" id="avrea" name="GPR">
+            <register-group caption="General Purpose Registers" name="GPR" size="0x4">
+                <register caption="General Purpose Register 0"
+                          name="GPR0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 1"
+                          name="GPR1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 2"
+                          name="GPR2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="General Purpose Register 3"
+                          name="GPR3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Lockbits" id="avrea" name="LOCK">
+            <register-group caption="Lockbits" name="LOCK" size="0x4">
+                <register caption="Lock Key Bits"
+                          initval="0x5CC5C55C"
+                          name="KEY"
+                          offset="0x0"
+                          rw="RW"
+                          size="4">
+                    <bitfield caption="Lock Key"
+                              mask="0xFFFFFFFF"
+                              name="KEY"
+                              rw="RW"
+                              values="LOCK_KEY"/>
+                </register>
+            </register-group>
+            <value-group caption="Lock Key select" name="LOCK_KEY">
+                <value caption="No locks" name="NOLOCK" value="0x5CC5C55C"/>
+                <value caption="Read and write lock" name="RWLOCK" value="0xA33A3AA3"/>
+            </value-group>
+        </module>
+        <module caption="Non-volatile Memory Controller"
+                id="nvm_ctrl_avr_v3"
+                name="NVMCTRL">
+            <register-group caption="Non-volatile Memory Controller" name="NVMCTRL" size="0x40">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x7F"
+                              name="CMD"
+                              rw="RW"
+                              values="NVMCTRL_CMD"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x30"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Application Code Write Protect"
+                              mask="0x01"
+                              name="APPCODEWP"
+                              rw="RW"/>
+                    <bitfield caption="Boot Read Protect" mask="0x02" name="BOOTRP" rw="RW"/>
+                    <bitfield caption="Application Data Write Protect"
+                              mask="0x04"
+                              name="APPDATAWP"
+                              rw="RW"/>
+                    <bitfield caption="EEPROM Write Protect" mask="0x08" name="EEWP" rw="RW"/>
+                    <bitfield caption="Flash Mapping in Data space"
+                              mask="0x30"
+                              name="FLMAP"
+                              rw="RW"
+                              values="NVMCTRL_FLMAP"/>
+                    <bitfield caption="Flash Mapping Lock"
+                              mask="0x80"
+                              name="FLMAPLOCK"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="EEPROM Ready" mask="0x01" name="EEREADY" rw="RW"/>
+                    <bitfield caption="Flash Ready" mask="0x02" name="FLREADY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x06"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="EEPROM busy" mask="0x01" name="EEBUSY" rw="R"/>
+                    <bitfield caption="Flash busy" mask="0x02" name="FLBUSY" rw="R"/>
+                    <bitfield caption="Write error"
+                              mask="0x70"
+                              name="ERROR"
+                              rw="R"
+                              values="NVMCTRL_ERROR"/>
+                </register>
+                <register caption="Data"
+                          initval="0x0000"
+                          name="DATA"
+                          offset="0x08"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Address"
+                          initval="0x00000000"
+                          name="ADDR"
+                          offset="0x0C"
+                          rw="RW"
+                          size="4"/>
+            </register-group>
+            <value-group caption="Command select" name="NVMCTRL_CMD">
+                <value caption="No Command" name="NOCMD" value="0x00"/>
+                <value caption="No Operation" name="NOOP" value="0x01"/>
+                <value caption="Flash Page Write" name="FLPW" value="0x04"/>
+                <value caption="Flash Page Erase and Write" name="FLPERW" value="0x05"/>
+                <value caption="Flash Page Erase" name="FLPER" value="0x08"/>
+                <value caption="Flash 2-page erase enable" name="FLMPER2" value="0x09"/>
+                <value caption="Flash 4-page erase enable" name="FLMPER4" value="0x0A"/>
+                <value caption="Flash 8-page erase enable" name="FLMPER8" value="0x0B"/>
+                <value caption="Flash 16-page erase enable" name="FLMPER16" value="0x0C"/>
+                <value caption="Flash 32-page erase enable" name="FLMPER32" value="0x0D"/>
+                <value caption="Flash Page Buffer Clear" name="FLPBCLR" value="0x0F"/>
+                <value caption="EEPROM Page Write" name="EEPW" value="0x14"/>
+                <value caption="EEPROM Page Erase and Write" name="EEPERW" value="0x15"/>
+                <value caption="EEPROM Page Erase" name="EEPER" value="0x17"/>
+                <value caption="EEPROM Page Buffer Clear" name="EEPBCLR" value="0x1F"/>
+                <value caption="Chip Erase Command (UPDI only)" name="CHER" value="0x20"/>
+                <value caption="EEPROM Erase Command (UPDI only)"
+                       name="EECHER"
+                       value="0x30"/>
+            </value-group>
+            <value-group caption="Flash Mapping in Data space select" name="NVMCTRL_FLMAP">
+                <value caption="Flash section 0, 0 - 32KB" name="SECTION0" value="0x0"/>
+                <value caption="Flash section 1, 32 - 64KB" name="SECTION1" value="0x1"/>
+                <value caption="Flash section 2, 64 - 96KB" name="SECTION2" value="0x2"/>
+                <value caption="Flash section 3, 96 - 128KB" name="SECTION3" value="0x3"/>
+            </value-group>
+            <value-group caption="Write error select" name="NVMCTRL_ERROR">
+                <value caption="No Error" name="NOERROR" value="0x0"/>
+                <value caption="Attempt to program write protected area"
+                       name="WRITEPROTECT"
+                       value="0x2"/>
+                <value caption="Selecting new write command while write command already seleted"
+                       name="CMDCOLLISION"
+                       value="0x3"/>
+                <value caption="Address cannot be written with selected command"
+                       name="WRONGSECTION"
+                       value="0x4"/>
+            </value-group>
+        </module>
+        <module caption="I/O Ports" id="gpio_ports_avr_v3" name="PORT">
+            <register-group caption="I/O Ports" name="PORT" size="0x20">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Set"
+                          initval="0x00"
+                          name="DIRSET"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Clear"
+                          initval="0x00"
+                          name="DIRCLR"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Data Direction Toggle"
+                          initval="0x00"
+                          name="DIRTGL"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Set"
+                          initval="0x00"
+                          name="OUTSET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Clear"
+                          initval="0x00"
+                          name="OUTCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value Toggle"
+                          initval="0x00"
+                          name="OUTTGL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+                <register caption="Port Control"
+                          initval="0x00"
+                          name="PORTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Slew Rate Limit Enable" mask="0x01" name="SRL" rw="RW"/>
+                </register>
+                <register caption="Pin Control Config"
+                          initval="0x00"
+                          name="PINCONFIG"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin Control Update"
+                          initval="0x00"
+                          name="PINCTRLUPD"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Set"
+                          initval="0x00"
+                          name="PINCTRLSET"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin Control Clear"
+                          initval="0x00"
+                          name="PINCTRLCLR"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Pin 0 Control"
+                          initval="0x00"
+                          name="PIN0CTRL"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 1 Control"
+                          initval="0x00"
+                          name="PIN1CTRL"
+                          offset="0x11"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 2 Control"
+                          initval="0x00"
+                          name="PIN2CTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 3 Control"
+                          initval="0x00"
+                          name="PIN3CTRL"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 4 Control"
+                          initval="0x00"
+                          name="PIN4CTRL"
+                          offset="0x14"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 5 Control"
+                          initval="0x00"
+                          name="PIN5CTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 6 Control"
+                          initval="0x00"
+                          name="PIN6CTRL"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Pin 7 Control"
+                          initval="0x00"
+                          name="PIN7CTRL"
+                          offset="0x17"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Input/Sense Configuration"
+                              mask="0x07"
+                              name="ISC"
+                              rw="RW"
+                              values="PORT_ISC"/>
+                    <bitfield caption="Pullup enable" mask="0x08" name="PULLUPEN" rw="RW"/>
+                    <bitfield caption="Input Level Select"
+                              mask="0x40"
+                              name="INLVL"
+                              rw="RW"
+                              values="PORT_INLVL"/>
+                    <bitfield caption="Inverted I/O Enable" mask="0x80" name="INVEN" rw="RW"/>
+                </register>
+                <register caption="Event Generation Control"
+                          initval="0x00"
+                          name="EVGENCTRL"
+                          offset="0x18"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generator 0 Select"
+                              mask="0x07"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="PORT_EVGEN0SEL"/>
+                    <bitfield caption="Event Generator 1 Select"
+                              mask="0x70"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="PORT_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Event Generator 0 Select" name="PORT_EVGEN0SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Event Generator 1 Select" name="PORT_EVGEN1SEL">
+                <value caption="Pin 0 used as event generator" name="PIN0" value="0x0"/>
+                <value caption="Pin 1 used as event generator" name="PIN1" value="0x1"/>
+                <value caption="Pin 2 used as event generator" name="PIN2" value="0x2"/>
+                <value caption="Pin 3 used as event generator" name="PIN3" value="0x3"/>
+                <value caption="Pin 4 used as event generator" name="PIN4" value="0x4"/>
+                <value caption="Pin 5 used as event generator" name="PIN5" value="0x5"/>
+                <value caption="Pin 6 used as event generator" name="PIN6" value="0x6"/>
+                <value caption="Pin 7 used as event generator" name="PIN7" value="0x7"/>
+            </value-group>
+            <value-group caption="Input Level Select" name="PORT_INLVL">
+                <value caption="Schmitt-Trigger input level" name="ST" value="0x0"/>
+                <value caption="TTL Input level" name="TTL" value="0x1"/>
+            </value-group>
+            <value-group caption="Input/Sense Configuration select" name="PORT_ISC">
+                <value caption="Interrupt disabled but input buffer enabled"
+                       name="INTDISABLE"
+                       value="0x0"/>
+                <value caption="Sense Both Edges" name="BOTHEDGES" value="0x1"/>
+                <value caption="Sense Rising Edge" name="RISING" value="0x2"/>
+                <value caption="Sense Falling Edge" name="FALLING" value="0x3"/>
+                <value caption="Digital Input Buffer disabled"
+                       name="INPUT_DISABLE"
+                       value="0x4"/>
+                <value caption="Sense low Level" name="LEVEL" value="0x5"/>
+            </value-group>
+        </module>
+        <module caption="Port Multiplexer" id="avrea" name="PORTMUX">
+            <register-group caption="Port Multiplexer" name="PORTMUX" size="0x20">
+                <register caption="EVSYS route A"
+                          initval="0x00"
+                          name="EVSYSROUTEA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Output A"
+                              mask="0x01"
+                              name="EVOUTA"
+                              rw="RW"
+                              values="PORTMUX_EVOUTA"/>
+                    <bitfield caption="Event Output C"
+                              mask="0x04"
+                              name="EVOUTC"
+                              rw="RW"
+                              values="PORTMUX_EVOUTC"/>
+                    <bitfield caption="Event Output D"
+                              mask="0x08"
+                              name="EVOUTD"
+                              rw="RW"
+                              values="PORTMUX_EVOUTD"/>
+                    <bitfield caption="Event Output F"
+                              mask="0x20"
+                              name="EVOUTF"
+                              rw="RW"
+                              values="PORTMUX_EVOUTF"/>
+                </register>
+                <register caption="CCL route A"
+                          initval="0x00"
+                          name="CCLROUTEA"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="CCL Look-Up Table 0 Signals"
+                              mask="0x01"
+                              name="LUT0"
+                              rw="RW"
+                              values="PORTMUX_LUT0"/>
+                    <bitfield caption="CCL Look-Up Table 1 Signals"
+                              mask="0x02"
+                              name="LUT1"
+                              rw="RW"
+                              values="PORTMUX_LUT1"/>
+                    <bitfield caption="CCL Look-Up Table 2 Signals"
+                              mask="0x04"
+                              name="LUT2"
+                              rw="RW"
+                              values="PORTMUX_LUT2"/>
+                </register>
+                <register caption="USART route A"
+                          initval="0x00"
+                          name="USARTROUTEA"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART0 Routing"
+                              mask="0x07"
+                              name="USART0"
+                              rw="RW"
+                              values="PORTMUX_USART0"/>
+                    <bitfield caption="USART1 Routing"
+                              mask="0x18"
+                              name="USART1"
+                              rw="RW"
+                              values="PORTMUX_USART1"/>
+                </register>
+                <register caption="USART route B"
+                          initval="0x00"
+                          name="USARTROUTEB"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="USART2 Routing"
+                              mask="0x30"
+                              name="USART2"
+                              rw="RW"
+                              values="PORTMUX_USART2"/>
+                </register>
+                <register caption="SPI route A"
+                          initval="0x00"
+                          name="SPIROUTEA"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI0 Signals"
+                              mask="0x07"
+                              name="SPI0"
+                              rw="RW"
+                              values="PORTMUX_SPI0"/>
+                </register>
+                <register caption="TWI route A"
+                          initval="0x00"
+                          name="TWIROUTEA"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TWI0 Signals"
+                              mask="0x03"
+                              name="TWI0"
+                              rw="RW"
+                              values="PORTMUX_TWI0"/>
+                </register>
+                <register caption="TCA route A"
+                          initval="0x00"
+                          name="TCAROUTEA"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCA0 Signals"
+                              mask="0x07"
+                              name="TCA0"
+                              rw="RW"
+                              values="PORTMUX_TCA0"/>
+                    <bitfield caption="TCA1 Signals"
+                              mask="0x38"
+                              name="TCA1"
+                              rw="RW"
+                              values="PORTMUX_TCA1"/>
+                </register>
+                <register caption="TCB route A"
+                          initval="0x00"
+                          name="TCBROUTEA"
+                          offset="0x08"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="TCB0 Output"
+                              mask="0x01"
+                              name="TCB0"
+                              rw="RW"
+                              values="PORTMUX_TCB0"/>
+                    <bitfield caption="TCB1 Output"
+                              mask="0x02"
+                              name="TCB1"
+                              rw="RW"
+                              values="PORTMUX_TCB1"/>
+                    <bitfield caption="TCB2 Output"
+                              mask="0x04"
+                              name="TCB2"
+                              rw="RW"
+                              values="PORTMUX_TCB2"/>
+                    <bitfield caption="TCB3 Output"
+                              mask="0x08"
+                              name="TCB3"
+                              rw="RW"
+                              values="PORTMUX_TCB3"/>
+                </register>
+                <register caption="AC route A"
+                          initval="0x00"
+                          name="ACROUTEA"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Analog Comparator 0 Output"
+                              mask="0x01"
+                              name="AC0"
+                              rw="RW"
+                              values="PORTMUX_AC0"/>
+                    <bitfield caption="Analog Comparator 1 Output"
+                              mask="0x02"
+                              name="AC1"
+                              rw="RW"
+                              values="PORTMUX_AC1"/>
+                </register>
+            </register-group>
+            <value-group caption="Analog Comparator 0 Output select" name="PORTMUX_AC0">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+                <value caption="OUT on PC6" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Analog Comparator 1 Output select" name="PORTMUX_AC1">
+                <value caption="OUT on PA7" name="DEFAULT" value="0x0"/>
+                <value caption="OUT on PC6" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 0 Signals select" name="PORTMUX_LUT0">
+                <value caption="Out: PA3 In: PA0, PA1, PA2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PA6 In: PA0, PA1, PA2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 1 Signals select" name="PORTMUX_LUT1">
+                <value caption="Out: PC3 In: PC0, PC1, PC2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PC6 In: PC0, PC1, PC2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="CCL Look-Up Table 2 Signals select" name="PORTMUX_LUT2">
+                <value caption="Out: PD3 In: PD0, PD1, PD2" name="DEFAULT" value="0x0"/>
+                <value caption="Out: PD6 In: PD0, PD1, PD2" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output A select" name="PORTMUX_EVOUTA">
+                <value caption="EVOUT on PA2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PA7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output C select" name="PORTMUX_EVOUTC">
+                <value caption="EVOUT on PC2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PC7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output D select" name="PORTMUX_EVOUTD">
+                <value caption="EVOUT on PD2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PD7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Output F select" name="PORTMUX_EVOUTF">
+                <value caption="EVOUT on PF2" name="DEFAULT" value="0x0"/>
+                <value caption="EVOUT on PF7" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="SPI0 Signals select" name="PORTMUX_SPI0">
+                <value caption="PA4, PA5, PA6, PA7" name="DEFAULT" value="0x0"/>
+                <value caption="PE0, PE1, PE2, PE3" name="ALT1" value="0x1"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="TCA0 Signals select" name="PORTMUX_TCA0">
+                <value caption="PA0, PA1, PA2, PA3, PA4, PA5" name="PORTA" value="0x0"/>
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x1"/>
+                <value caption="PC0, PC1, PC2, PC3, PC4, PC5" name="PORTC" value="0x2"/>
+                <value caption="PD0, PD1, PD2, PD3, PD4, PD5" name="PORTD" value="0x3"/>
+                <value caption="PE0, PE1, PE2, PE3, PE4, PE5" name="PORTE" value="0x4"/>
+                <value caption="PF0, PF1, PF2, PF3, PF4, PF5" name="PORTF" value="0x5"/>
+            </value-group>
+            <value-group caption="TCA1 Signals select" name="PORTMUX_TCA1">
+                <value caption="PB0, PB1, PB2, PB3, PB4, PB5" name="PORTB" value="0x0"/>
+                <value caption="PC4, PC5, PC6" name="PORTC" value="0x1"/>
+                <value caption="PA4, PA5, PA6" name="PORTA" value="0x4"/>
+                <value caption="PD4, PD5, PD6" name="PORTD" value="0x5"/>
+            </value-group>
+            <value-group caption="TCB0 Output select" name="PORTMUX_TCB0">
+                <value caption="PA2" name="DEFAULT" value="0x0"/>
+                <value caption="PF4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB1 Output select" name="PORTMUX_TCB1">
+                <value caption="PA3" name="DEFAULT" value="0x0"/>
+                <value caption="PF5" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB2 Output select" name="PORTMUX_TCB2">
+                <value caption="PC0" name="DEFAULT" value="0x0"/>
+                <value caption="PB4" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TCB3 Output select" name="PORTMUX_TCB3">
+                <value caption="PB5" name="DEFAULT" value="0x0"/>
+                <value caption="PC1" name="ALT1" value="0x1"/>
+            </value-group>
+            <value-group caption="TWI0 Signals select" name="PORTMUX_TWI0">
+                <value caption="{PA2, PA3}, {PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PA2, PA3}, {PC6, PC7}" name="ALT1" value="0x1"/>
+                <value caption="{PC2, PC3}, {PC6, PC7}" name="ALT2" value="0x2"/>
+                <value caption="{PA0, PA1}, {PC2, PC3}" name="ALT3" value="0x3"/>
+            </value-group>
+            <value-group caption="USART0 Routing select" name="PORTMUX_USART0">
+                <value caption="{PA0, PA1, PA2, PA3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PA4, PA5, PA6, PA7}" name="ALT1" value="0x1"/>
+                <value caption="{PA2,PA3, -, -}" name="ALT2" value="0x2"/>
+                <value caption="{PD4, PD5, PD6, PD7}" name="ALT3" value="0x3"/>
+                <value caption="{PC1, PC2, PC3, -}" name="ALT4" value="0x4"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x5"/>
+            </value-group>
+            <value-group caption="USART1 Routing select" name="PORTMUX_USART1">
+                <value caption="{PC0, PC1, PC2, PC3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PC4, PC5, PC6, PC7}" name="ALT1" value="0x1"/>
+                <value caption="{PD6, PD7, -, -}" name="ALT2" value="0x2"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+            <value-group caption="USART2 Routing select" name="PORTMUX_USART2">
+                <value caption="{PF0, PF1, PF2, PF3}" name="DEFAULT" value="0x0"/>
+                <value caption="{PF4, PF5,- , -}" name="ALT1" value="0x1"/>
+                <value caption="Not connected to any pins" name="NONE" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="Reset controller"
+                id="rst_integration_avr_v2"
+                name="RSTCTRL">
+            <register-group caption="Reset controller" name="RSTCTRL" size="0x10">
+                <register caption="Reset Flags"
+                          initval="0x00"
+                          name="RSTFR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Power on Reset flag" mask="0x01" name="PORF" rw="RW"/>
+                    <bitfield caption="Brown out detector Reset flag"
+                              mask="0x02"
+                              name="BORF"
+                              rw="RW"/>
+                    <bitfield caption="External Reset flag" mask="0x04" name="EXTRF" rw="RW"/>
+                    <bitfield caption="Watch dog Reset flag" mask="0x08" name="WDRF" rw="RW"/>
+                    <bitfield caption="Software Reset flag" mask="0x10" name="SWRF" rw="RW"/>
+                    <bitfield caption="UPDI Reset flag" mask="0x20" name="UPDIRF" rw="RW"/>
+                </register>
+                <register caption="Software Reset"
+                          initval="0x00"
+                          name="SWRR"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Software Reset Enable" mask="0x01" name="SWRE" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Real-Time Counter" id="tmr_16b_rtc_avr_v2" name="RTC">
+            <register-group caption="Real-Time Counter" name="RTC" size="0x20">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="RTCEN" rw="RW"/>
+                    <bitfield caption="Correction enable" mask="0x04" name="CORREN" rw="RW"/>
+                    <bitfield caption="Prescaling Factor"
+                              mask="0x78"
+                              name="PRESCALER"
+                              rw="RW"
+                              values="RTC_PRESCALER"/>
+                    <bitfield caption="Run In Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLABUSY"
+                              rw="R"/>
+                    <bitfield caption="Count Synchronization Busy Flag"
+                              mask="0x02"
+                              name="CNTBUSY"
+                              rw="R"/>
+                    <bitfield caption="Period Synchronization Busy Flag"
+                              mask="0x04"
+                              name="PERBUSY"
+                              rw="R"/>
+                    <bitfield caption="Comparator Synchronization Busy Flag"
+                              mask="0x08"
+                              name="CMPBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt enable"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt enable"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt Flag"
+                              mask="0x01"
+                              name="OVF"
+                              rw="RW"/>
+                    <bitfield caption="Compare Match Interrupt"
+                              mask="0x02"
+                              name="CMP"
+                              rw="RW"/>
+                </register>
+                <register caption="Temporary"
+                          name="TEMP"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Debug control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Calibration"
+                          initval="0x00"
+                          name="CALIB"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Error Correction Value"
+                              mask="0x7F"
+                              name="ERROR"
+                              rw="RW"/>
+                    <bitfield caption="Error Correction Sign Bit"
+                              mask="0x80"
+                              name="SIGN"
+                              rw="RW"/>
+                </register>
+                <register caption="Clock Select"
+                          initval="0x00"
+                          name="CLKSEL"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Clock Select"
+                              mask="0x03"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="RTC_CLKSEL"/>
+                </register>
+                <register caption="Counter" name="CNT" offset="0x08" rw="RW" size="2"/>
+                <register caption="Period"
+                          initval="0xFFFF"
+                          name="PER"
+                          offset="0x0A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare" name="CMP" offset="0x0C" rw="RW" size="2"/>
+                <register caption="PIT Control A"
+                          initval="0x00"
+                          name="PITCTRLA"
+                          offset="0x10"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="PITEN" rw="RW"/>
+                    <bitfield caption="Period"
+                              mask="0x78"
+                              name="PERIOD"
+                              rw="RW"
+                              values="RTC_PERIOD"/>
+                </register>
+                <register caption="PIT Status"
+                          initval="0x00"
+                          name="PITSTATUS"
+                          offset="0x11"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="CTRLA Synchronization Busy Flag"
+                              mask="0x01"
+                              name="CTRLBUSY"
+                              rw="R"/>
+                </register>
+                <register caption="PIT Interrupt Control"
+                          initval="0x00"
+                          name="PITINTCTRL"
+                          offset="0x12"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Interrupt Flags"
+                          initval="0x00"
+                          name="PITINTFLAGS"
+                          offset="0x13"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Periodic Interrupt" mask="0x01" name="PI" rw="RW"/>
+                </register>
+                <register caption="PIT Debug control"
+                          initval="0x00"
+                          name="PITDBGCTRL"
+                          offset="0x15"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Run in debug" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="PIT Event Generation Control A"
+                          initval="0x00"
+                          name="PITEVGENCTRLA"
+                          offset="0x16"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Generation 0 Select"
+                              mask="0x0F"
+                              name="EVGEN0SEL"
+                              rw="RW"
+                              values="RTC_EVGEN0SEL"/>
+                    <bitfield caption="Event Generation 1 Select"
+                              mask="0xF0"
+                              name="EVGEN1SEL"
+                              rw="RW"
+                              values="RTC_EVGEN1SEL"/>
+                </register>
+            </register-group>
+            <value-group caption="Clock Select" name="RTC_CLKSEL">
+                <value caption="Internal 32.768 kHz Oscillator" name="OSC32K" value="0x0"/>
+                <value caption="Internal 32.768 kHz Oscillator Divided by 32"
+                       name="OSC1K"
+                       value="0x1"/>
+                <value caption="32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x2"/>
+                <value caption="External Clock" name="EXTCLK" value="0x3"/>
+            </value-group>
+            <value-group caption="Prescaling Factor select" name="RTC_PRESCALER">
+                <value caption="RTC Clock / 1" name="DIV1" value="0x00"/>
+                <value caption="RTC Clock / 2" name="DIV2" value="0x01"/>
+                <value caption="RTC Clock / 4" name="DIV4" value="0x02"/>
+                <value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
+                <value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
+                <value caption="RTC Clock / 32" name="DIV32" value="0x05"/>
+                <value caption="RTC Clock / 64" name="DIV64" value="0x06"/>
+                <value caption="RTC Clock / 128" name="DIV128" value="0x07"/>
+                <value caption="RTC Clock / 256" name="DIV256" value="0x08"/>
+                <value caption="RTC Clock / 512" name="DIV512" value="0x09"/>
+                <value caption="RTC Clock / 1024" name="DIV1024" value="0x0A"/>
+                <value caption="RTC Clock / 2048" name="DIV2048" value="0x0B"/>
+                <value caption="RTC Clock / 4096" name="DIV4096" value="0x0C"/>
+                <value caption="RTC Clock / 8192" name="DIV8192" value="0x0D"/>
+                <value caption="RTC Clock / 16384" name="DIV16384" value="0x0E"/>
+                <value caption="RTC Clock / 32768" name="DIV32768" value="0x0F"/>
+            </value-group>
+            <value-group caption="Period select" name="RTC_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="RTC Clock Cycles 4" name="CYC4" value="0x01"/>
+                <value caption="RTC Clock Cycles 8" name="CYC8" value="0x02"/>
+                <value caption="RTC Clock Cycles 16" name="CYC16" value="0x03"/>
+                <value caption="RTC Clock Cycles 32" name="CYC32" value="0x04"/>
+                <value caption="RTC Clock Cycles 64" name="CYC64" value="0x05"/>
+                <value caption="RTC Clock Cycles 128" name="CYC128" value="0x06"/>
+                <value caption="RTC Clock Cycles 256" name="CYC256" value="0x07"/>
+                <value caption="RTC Clock Cycles 512" name="CYC512" value="0x08"/>
+                <value caption="RTC Clock Cycles 1024" name="CYC1024" value="0x09"/>
+                <value caption="RTC Clock Cycles 2048" name="CYC2048" value="0x0A"/>
+                <value caption="RTC Clock Cycles 4096" name="CYC4096" value="0x0B"/>
+                <value caption="RTC Clock Cycles 8192" name="CYC8192" value="0x0C"/>
+                <value caption="RTC Clock Cycles 16384" name="CYC16384" value="0x0D"/>
+                <value caption="RTC Clock Cycles 32768" name="CYC32768" value="0x0E"/>
+            </value-group>
+            <value-group caption="Event Generation 0 Select" name="RTC_EVGEN0SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+            <value-group caption="Event Generation 1 Select" name="RTC_EVGEN1SEL">
+                <value caption="No Event Generated" name="OFF" value="0x0"/>
+                <value caption="CLK_RTC divided by 4" name="DIV4" value="0x1"/>
+                <value caption="CLK_RTC divided by 8" name="DIV8" value="0x2"/>
+                <value caption="CLK_RTC divided by 16" name="DIV16" value="0x3"/>
+                <value caption="CLK_RTC divided by 32" name="DIV32" value="0x4"/>
+                <value caption="CLK_RTC divided by 64" name="DIV64" value="0x5"/>
+                <value caption="CLK_RTC divided by 128" name="DIV128" value="0x6"/>
+                <value caption="CLK_RTC divided by 256" name="DIV256" value="0x7"/>
+                <value caption="CLK_RTC divided by 512" name="DIV512" value="0x8"/>
+                <value caption="CLK_RTC divided by 1024" name="DIV1024" value="0x9"/>
+                <value caption="CLK_RTC divided by 2048" name="DIV2048" value="0xA"/>
+                <value caption="CLK_RTC divided by 4096" name="DIV4096" value="0xB"/>
+                <value caption="CLK_RTC divided by 8192" name="DIV8192" value="0xC"/>
+                <value caption="CLK_RTC divided by 16384" name="DIV16384" value="0xD"/>
+                <value caption="CLK_RTC divided by 32768" name="DIV32768" value="0xE"/>
+            </value-group>
+        </module>
+        <module caption="Signature row" id="avrea" name="SIGROW">
+            <register-group caption="Signature row" name="SIGROW" size="0x40">
+                <register caption="Device ID Byte 0"
+                          name="DEVICEID0"
+                          offset="0x00"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 1"
+                          name="DEVICEID1"
+                          offset="0x01"
+                          rw="R"
+                          size="1"/>
+                <register caption="Device ID Byte 2"
+                          name="DEVICEID2"
+                          offset="0x02"
+                          rw="R"
+                          size="1"/>
+                <register caption="Temperature Calibration 0"
+                          name="TEMPSENSE0"
+                          offset="0x04"
+                          rw="R"
+                          size="2"/>
+                <register caption="Temperature Calibration 1"
+                          name="TEMPSENSE1"
+                          offset="0x06"
+                          rw="R"
+                          size="2"/>
+                <register caption="Serial Number Byte 0"
+                          name="SERNUM0"
+                          offset="0x10"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 1"
+                          name="SERNUM1"
+                          offset="0x11"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 2"
+                          name="SERNUM2"
+                          offset="0x12"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 3"
+                          name="SERNUM3"
+                          offset="0x13"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 4"
+                          name="SERNUM4"
+                          offset="0x14"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 5"
+                          name="SERNUM5"
+                          offset="0x15"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 6"
+                          name="SERNUM6"
+                          offset="0x16"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 7"
+                          name="SERNUM7"
+                          offset="0x17"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 8"
+                          name="SERNUM8"
+                          offset="0x18"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 9"
+                          name="SERNUM9"
+                          offset="0x19"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 10"
+                          name="SERNUM10"
+                          offset="0x1A"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 11"
+                          name="SERNUM11"
+                          offset="0x1B"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 12"
+                          name="SERNUM12"
+                          offset="0x1C"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 13"
+                          name="SERNUM13"
+                          offset="0x1D"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 14"
+                          name="SERNUM14"
+                          offset="0x1E"
+                          rw="R"
+                          size="1"/>
+                <register caption="Serial Number Byte 15"
+                          name="SERNUM15"
+                          offset="0x1F"
+                          rw="R"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Sleep Controller"
+                id="clk_sleep_ctrl_avr_v1"
+                name="SLPCTRL">
+            <register-group caption="Sleep Controller" name="SLPCTRL" size="0x2">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Sleep enable" mask="0x01" name="SEN" rw="RW"/>
+                    <bitfield caption="Sleep mode"
+                              mask="0x06"
+                              name="SMODE"
+                              rw="RW"
+                              values="SLPCTRL_SMODE"/>
+                </register>
+            </register-group>
+            <value-group caption="Sleep mode select" name="SLPCTRL_SMODE">
+                <value caption="Idle mode" name="IDLE" value="0x00"/>
+                <value caption="Standby Mode" name="STDBY" value="0x01"/>
+                <value caption="Power-down Mode" name="PDOWN" value="0x02"/>
+            </value-group>
+        </module>
+        <module caption="Serial Peripheral Interface" id="spi_8bit_v2" name="SPI">
+            <register-group caption="Serial Peripheral Interface" name="SPI" size="0x8">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable Module" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Prescaler"
+                              mask="0x06"
+                              name="PRESC"
+                              rw="RW"
+                              values="SPI_PRESC"/>
+                    <bitfield caption="Enable Double Speed" mask="0x10" name="CLK2X" rw="RW"/>
+                    <bitfield caption="Host Operation Enable"
+                              mask="0x20"
+                              name="MASTER"
+                              rw="RW"/>
+                    <bitfield caption="Data Order Setting" mask="0x40" name="DORD" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="SPI Mode"
+                              mask="0x03"
+                              name="MODE"
+                              rw="RW"
+                              values="SPI_MODE"/>
+                    <bitfield caption="SPI Select Disable" mask="0x04" name="SSD" rw="RW"/>
+                    <bitfield caption="Buffer Mode Wait for Receive"
+                              mask="0x40"
+                              name="BUFWR"
+                              rw="RW"/>
+                    <bitfield caption="Buffer Mode Enable" mask="0x80" name="BUFEN" rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Interrupt Enable" mask="0x01" name="IE" rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Enable"
+                              mask="0x10"
+                              name="SSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <mode name="DEFAULT" qualifier="SPI.CTRLB.BUFEN" value="0"/>
+                    <mode name="BUFFERED" qualifier="SPI.CTRLB.BUFEN" value="1"/>
+                    <bitfield caption="Buffer Overflow"
+                              mask="0x01"
+                              modes="BUFFERED"
+                              name="BUFOVF"
+                              rw="RW"/>
+                    <bitfield caption="SPI Select Trigger Interrupt Flag"
+                              mask="0x10"
+                              modes="BUFFERED"
+                              name="SSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Flag"
+                              mask="0x20"
+                              modes="BUFFERED"
+                              name="DREIF"
+                              rw="RW"/>
+                    <bitfield caption="Transfer Complete Interrupt Flag"
+                              mask="0x40"
+                              modes="BUFFERED"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              modes="BUFFERED"
+                              name="RXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Write Collision"
+                              mask="0x40"
+                              modes="DEFAULT"
+                              name="WRCOL"
+                              rw="RW"/>
+                    <bitfield caption="Interrupt Flag"
+                              mask="0x80"
+                              modes="DEFAULT"
+                              name="IF"
+                              rw="RW"/>
+                </register>
+                <register caption="Data" name="DATA" offset="0x4" rw="RW" size="1"/>
+            </register-group>
+            <value-group caption="Prescaler select" name="SPI_PRESC">
+                <value caption="CLK_PER / 4" name="DIV4" value="0x00"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x01"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x02"/>
+                <value caption="CLK_PER / 128" name="DIV128" value="0x03"/>
+            </value-group>
+            <value-group caption="SPI Mode select" name="SPI_MODE">
+                <value caption="SPI Mode 0" name="0" value="0x00"/>
+                <value caption="SPI Mode 1" name="1" value="0x01"/>
+                <value caption="SPI Mode 2" name="2" value="0x02"/>
+                <value caption="SPI Mode 3" name="3" value="0x03"/>
+            </value-group>
+        </module>
+        <module caption="System Configuration Registers" id="avrea" name="SYSCFG">
+            <register-group caption="System Configuration Registers" name="SYSCFG" size="0x20">
+                <register caption="Revision ID"
+                          name="REVID"
+                          offset="0x01"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Minor Revision" mask="0x0F" name="MINOR" rw="R"/>
+                    <bitfield caption="Major Revision" mask="0xF0" name="MAJOR" rw="R"/>
+                </register>
+                <register caption="OCD Message Control"
+                          name="OCDMCTRL"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message" mask="0xFF" name="OCDM" rw="RW"/>
+                </register>
+                <register caption="OCD Message Status"
+                          initval="0x00"
+                          name="OCDMSTATUS"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="OCD Message Valid" mask="0x01" name="VALID" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="16-bit Timer/Counter Type A"
+                id="tmr_16b_pwm_v1"
+                name="TCA">
+            <register-group caption="16-bit Timer/Counter Type A" name="TCA" size="0x40">
+                <mode caption="Single Mode"
+                      name="SINGLE"
+                      qualifier="TCA.SINGLE.CTRLD.SPLITM"
+                      value="0"/>
+                <mode caption="Split Mode"
+                      name="SPLIT"
+                      qualifier="TCA.SPLIT.CTRLD.SPLITM"
+                      value="1"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SINGLE_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Waveform generation mode"
+                              mask="0x07"
+                              name="WGMODE"
+                              rw="RW"
+                              values="TCA_SINGLE_WGMODE"/>
+                    <bitfield caption="Auto Lock Update" mask="0x08" name="ALUPD" rw="RW"/>
+                    <bitfield caption="Compare 0 Enable" mask="0x10" name="CMP0EN" rw="RW"/>
+                    <bitfield caption="Compare 1 Enable" mask="0x20" name="CMP1EN" rw="RW"/>
+                    <bitfield caption="Compare 2 Enable" mask="0x40" name="CMP2EN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Compare 0 Waveform Output Value"
+                              mask="0x01"
+                              name="CMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Waveform Output Value"
+                              mask="0x02"
+                              name="CMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Waveform Output Value"
+                              mask="0x04"
+                              name="CMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction" mask="0x01" name="DIR" rw="RW"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Direction"
+                              mask="0x01"
+                              name="DIR"
+                              rw="RW"
+                              values="TCA_SINGLE_DIR"/>
+                    <bitfield caption="Lock Update" mask="0x02" name="LUPD" rw="RW"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SINGLE_CMD"/>
+                </register>
+                <register caption="Control F Clear"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFCLR"
+                          offset="0x06"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control F Set"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="CTRLFSET"
+                          offset="0x07"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV" rw="RW"/>
+                    <bitfield caption="Compare 0 Buffer Valid"
+                              mask="0x02"
+                              name="CMP0BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 1 Buffer Valid"
+                              mask="0x04"
+                              name="CMP1BV"
+                              rw="RW"/>
+                    <bitfield caption="Compare 2 Buffer Valid"
+                              mask="0x08"
+                              name="CMP2BV"
+                              rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="EVCTRL"
+                          offset="0x09"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Count on Event Input A"
+                              mask="0x01"
+                              name="CNTAEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action A"
+                              mask="0x0E"
+                              name="EVACTA"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTA"/>
+                    <bitfield caption="Count on Event Input B"
+                              mask="0x10"
+                              name="CNTBEI"
+                              rw="RW"/>
+                    <bitfield caption="Event Action B"
+                              mask="0xE0"
+                              name="EVACTB"
+                              rw="RW"
+                              values="TCA_SINGLE_EVACTB"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Overflow Interrupt" mask="0x01" name="OVF" rw="RW"/>
+                    <bitfield caption="Compare 0 Interrupt" mask="0x10" name="CMP0" rw="RW"/>
+                    <bitfield caption="Compare 1 Interrupt" mask="0x20" name="CMP1" rw="RW"/>
+                    <bitfield caption="Compare 2 Interrupt" mask="0x40" name="CMP2" rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SINGLE"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary data for 16-bit Access"
+                          modes="SINGLE"
+                          name="TEMP"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          modes="SINGLE"
+                          name="CNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period"
+                          modes="SINGLE"
+                          name="PER"
+                          offset="0x26"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0"
+                          modes="SINGLE"
+                          name="CMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1"
+                          modes="SINGLE"
+                          name="CMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2"
+                          modes="SINGLE"
+                          name="CMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Period Buffer"
+                          modes="SINGLE"
+                          name="PERBUF"
+                          offset="0x36"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 0 Buffer"
+                          modes="SINGLE"
+                          name="CMP0BUF"
+                          offset="0x38"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 1 Buffer"
+                          modes="SINGLE"
+                          name="CMP1BUF"
+                          offset="0x3A"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare 2 Buffer"
+                          modes="SINGLE"
+                          name="CMP2BUF"
+                          offset="0x3C"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control A"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLA"
+                          offset="0x00"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Module Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Selection"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCA_SPLIT_CLKSEL"/>
+                    <bitfield caption="Run in Standby" mask="0x80" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLB"
+                          offset="0x01"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Enable"
+                              mask="0x01"
+                              name="LCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Enable"
+                              mask="0x02"
+                              name="LCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Enable"
+                              mask="0x04"
+                              name="LCMP2EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Enable"
+                              mask="0x10"
+                              name="HCMP0EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Enable"
+                              mask="0x20"
+                              name="HCMP1EN"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Enable"
+                              mask="0x40"
+                              name="HCMP2EN"
+                              rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLC"
+                          offset="0x02"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Compare 0 Output Value"
+                              mask="0x01"
+                              name="LCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Output Value"
+                              mask="0x02"
+                              name="LCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Output Value"
+                              mask="0x04"
+                              name="LCMP2OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 0 Output Value"
+                              mask="0x10"
+                              name="HCMP0OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 1 Output Value"
+                              mask="0x20"
+                              name="HCMP1OV"
+                              rw="RW"/>
+                    <bitfield caption="High Compare 2 Output Value"
+                              mask="0x40"
+                              name="HCMP2OV"
+                              rw="RW"/>
+                </register>
+                <register caption="Control D"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLD"
+                          offset="0x03"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Split Mode Enable" mask="0x01" name="SPLITM" rw="RW"/>
+                </register>
+                <register caption="Control E Clear"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLECLR"
+                          offset="0x04"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Control E Set"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="CTRLESET"
+                          offset="0x05"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command Enable"
+                              mask="0x03"
+                              name="CMDEN"
+                              rw="RW"
+                              values="TCA_SPLIT_CMDEN"/>
+                    <bitfield caption="Command"
+                              mask="0x0C"
+                              name="CMD"
+                              rw="RW"
+                              values="TCA_SPLIT_CMD"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTCTRL"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Enable"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Enable"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Enable"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Enable"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Enable"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="INTFLAGS"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Low Underflow Interrupt Flag"
+                              mask="0x01"
+                              name="LUNF"
+                              rw="RW"/>
+                    <bitfield caption="High Underflow Interrupt Flag"
+                              mask="0x02"
+                              name="HUNF"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 2 Interrupt Flag"
+                              mask="0x10"
+                              name="LCMP0"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 1 Interrupt Flag"
+                              mask="0x20"
+                              name="LCMP1"
+                              rw="RW"/>
+                    <bitfield caption="Low Compare 0 Interrupt Flag"
+                              mask="0x40"
+                              name="LCMP2"
+                              rw="RW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          modes="SPLIT"
+                          name="DBGCTRL"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Low Count"
+                          modes="SPLIT"
+                          name="LCNT"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Count"
+                          modes="SPLIT"
+                          name="HCNT"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Period"
+                          modes="SPLIT"
+                          name="LPER"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Period"
+                          modes="SPLIT"
+                          name="HPER"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP0"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP0"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP1"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP1"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Low Compare"
+                          modes="SPLIT"
+                          name="LCMP2"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="High Compare"
+                          modes="SPLIT"
+                          name="HCMP2"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+            <value-group caption="Clock Selection" name="TCA_SINGLE_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Waveform generation mode select" name="TCA_SINGLE_WGMODE">
+                <value caption="Normal Mode" name="NORMAL" value="0x00"/>
+                <value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
+                <value caption="Single Slope PWM" name="SINGLESLOPE" value="0x03"/>
+                <value caption="Dual Slope PWM, overflow on TOP" name="DSTOP" value="0x05"/>
+                <value caption="Dual Slope PWM, overflow on TOP and BOTTOM"
+                       name="DSBOTH"
+                       value="0x06"/>
+                <value caption="Dual Slope PWM, overflow on BOTTOM"
+                       name="DSBOTTOM"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SINGLE_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Direction select" name="TCA_SINGLE_DIR">
+                <value caption="Count up" name="UP" value="0x0"/>
+                <value caption="Count down" name="DOWN" value="0x1"/>
+            </value-group>
+            <value-group caption="Event Action A select" name="TCA_SINGLE_EVACTA">
+                <value caption="Count on positive edge event"
+                       name="CNT_POSEDGE"
+                       value="0x00"/>
+                <value caption="Count on any edge event" name="CNT_ANYEDGE" value="0x01"/>
+                <value caption="Count on prescaled clock while event line is 1."
+                       name="CNT_HIGHLVL"
+                       value="0x02"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+            </value-group>
+            <value-group caption="Event Action B select" name="TCA_SINGLE_EVACTB">
+                <value caption="No Action" name="NONE" value="0x00"/>
+                <value caption="Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1."
+                       name="UPDOWN"
+                       value="0x03"/>
+                <value caption="Restart counter at positive edge event"
+                       name="RESTART_POSEDGE"
+                       value="0x04"/>
+                <value caption="Restart counter on any edge event"
+                       name="RESTART_ANYEDGE"
+                       value="0x05"/>
+                <value caption="Restart counter while event line is 1."
+                       name="RESTART_HIGHLVL"
+                       value="0x06"/>
+            </value-group>
+            <value-group caption="Clock Selection" name="TCA_SPLIT_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER / 2" name="DIV2" value="0x01"/>
+                <value caption="CLK_PER / 4" name="DIV4" value="0x02"/>
+                <value caption="CLK_PER / 8" name="DIV8" value="0x03"/>
+                <value caption="CLK_PER / 16" name="DIV16" value="0x04"/>
+                <value caption="CLK_PER / 64" name="DIV64" value="0x05"/>
+                <value caption="CLK_PER / 256" name="DIV256" value="0x06"/>
+                <value caption="CLK_PER / 1024" name="DIV1024" value="0x07"/>
+            </value-group>
+            <value-group caption="Command select" name="TCA_SPLIT_CMD">
+                <value caption="No Command" name="NONE" value="0x00"/>
+                <value caption="Force Update" name="UPDATE" value="0x01"/>
+                <value caption="Force Restart" name="RESTART" value="0x02"/>
+                <value caption="Force Hard Reset" name="RESET" value="0x03"/>
+            </value-group>
+            <value-group caption="Command Enable select" name="TCA_SPLIT_CMDEN">
+                <value caption="None" name="NONE" value="0x0"/>
+                <value caption="Both low byte and high byte counter"
+                       name="BOTH"
+                       value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="16-bit Timer Type B" id="tmr_16b_capture_v1" name="TCB">
+            <register-group caption="16-bit Timer Type B" name="TCB" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Clock Select"
+                              mask="0x0E"
+                              name="CLKSEL"
+                              rw="RW"
+                              values="TCB_CLKSEL"/>
+                    <bitfield caption="Synchronize Update" mask="0x10" name="SYNCUPD" rw="RW"/>
+                    <bitfield caption="Cascade two timers" mask="0x20" name="CASCADE" rw="RW"/>
+                    <bitfield caption="Run Standby" mask="0x40" name="RUNSTDBY" rw="RW"/>
+                </register>
+                <register caption="Control Register B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Timer Mode"
+                              mask="0x07"
+                              name="CNTMODE"
+                              rw="RW"
+                              values="TCB_CNTMODE"/>
+                    <bitfield caption="Pin Output Enable" mask="0x10" name="CCMPEN" rw="RW"/>
+                    <bitfield caption="Pin Initial State" mask="0x20" name="CCMPINIT" rw="RW"/>
+                    <bitfield caption="Asynchronous Enable" mask="0x40" name="ASYNC" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Event Input Enable" mask="0x01" name="CAPTEI" rw="RW"/>
+                    <bitfield caption="Event Edge" mask="0x10" name="EDGE" rw="RW"/>
+                    <bitfield caption="Input Capture Noise Cancellation Filter"
+                              mask="0x40"
+                              name="FILTER"
+                              rw="RW"/>
+                </register>
+                <register caption="Interrupt Control"
+                          initval="0x00"
+                          name="INTCTRL"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Capture or Timeout" mask="0x01" name="CAPT" rw="RW"/>
+                    <bitfield caption="Overflow" mask="0x02" name="OVF" rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x7"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Run" mask="0x01" name="RUN" rw="R"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Temporary Value"
+                          name="TEMP"
+                          offset="0x9"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Count"
+                          initval="0x0000"
+                          name="CNT"
+                          offset="0xA"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Compare or Capture"
+                          name="CCMP"
+                          offset="0xC"
+                          rw="RW"
+                          size="2"/>
+            </register-group>
+            <value-group caption="Clock Select" name="TCB_CLKSEL">
+                <value caption="CLK_PER" name="DIV1" value="0x00"/>
+                <value caption="CLK_PER/2" name="DIV2" value="0x01"/>
+                <value caption="Use CLK_TCA from TCA0" name="TCA0" value="0x02"/>
+                <value caption="Use CLK_TCA from TCA1" name="TCA1" value="0x03"/>
+                <value caption="Count on event edge" name="EVENT" value="0x07"/>
+            </value-group>
+            <value-group caption="Timer Mode select" name="TCB_CNTMODE">
+                <value caption="Periodic Interrupt" name="INT" value="0x00"/>
+                <value caption="Periodic Timeout" name="TIMEOUT" value="0x01"/>
+                <value caption="Input Capture Event" name="CAPT" value="0x02"/>
+                <value caption="Input Capture Frequency measurement"
+                       name="FRQ"
+                       value="0x03"/>
+                <value caption="Input Capture Pulse-Width measurement"
+                       name="PW"
+                       value="0x04"/>
+                <value caption="Input Capture Frequency and Pulse-Width measurement"
+                       name="FRQPW"
+                       value="0x05"/>
+                <value caption="Single Shot" name="SINGLE" value="0x06"/>
+                <value caption="8-bit PWM" name="PWM8" value="0x07"/>
+            </value-group>
+        </module>
+        <module caption="Two-Wire Interface" id="i2c_8bit_avr_v3" name="TWI">
+            <register-group caption="Two-Wire Interface" name="TWI" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Fast-mode Enable"
+                              mask="0x01"
+                              name="FMEN"
+                              rw="RW"
+                              values="TWI_FMEN"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="SDA Setup Time"
+                              mask="0x10"
+                              name="SDASETUP"
+                              rw="RW"
+                              values="TWI_SDASETUP"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Dual Mode Control"
+                          initval="0x00"
+                          name="DUALCTRL"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Fast-mode Plus Enable"
+                              mask="0x02"
+                              name="FMPEN"
+                              rw="RW"
+                              values="TWI_FMPEN"/>
+                    <bitfield caption="SDA Hold Time"
+                              mask="0x0C"
+                              name="SDAHOLD"
+                              rw="RW"
+                              values="TWI_SDAHOLD"/>
+                    <bitfield caption="Input voltage transition level"
+                              mask="0x40"
+                              name="INPUTLVL"
+                              rw="RW"
+                              values="TWI_INPUTLVL"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run"
+                              mask="0x01"
+                              name="DBGRUN"
+                              rw="RW"
+                              values="TWI_DBGRUN"/>
+                </register>
+                <register caption="Host Control A"
+                          initval="0x00"
+                          name="MCTRLA"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Inactive Bus Time-Out"
+                              mask="0x0C"
+                              name="TIMEOUT"
+                              rw="RW"
+                              values="TWI_TIMEOUT"/>
+                    <bitfield caption="Quick Command Enable" mask="0x10" name="QCEN" rw="RW"/>
+                    <bitfield caption="Write Interrupt Enable"
+                              mask="0x40"
+                              name="WIEN"
+                              rw="RW"/>
+                    <bitfield caption="Read Interrupt Enable" mask="0x80" name="RIEN" rw="RW"/>
+                </register>
+                <register caption="Host Control B"
+                          initval="0x00"
+                          name="MCTRLB"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="MCMD"
+                              rw="RW"
+                              values="TWI_MCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                    <bitfield caption="Flush" mask="0x08" name="FLUSH" rw="RW"/>
+                </register>
+                <register caption="Host STATUS"
+                          initval="0x00"
+                          name="MSTATUS"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Bus State"
+                              mask="0x03"
+                              name="BUSSTATE"
+                              rw="RW"
+                              values="TWI_BUSSTATE"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF" rw="RW"/>
+                    <bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF" rw="RW"/>
+                </register>
+                <register caption="Host Baud Rate"
+                          initval="0x00"
+                          name="MBAUD"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Baud Rate" mask="0xFF" name="BAUD" rw="RW"/>
+                </register>
+                <register caption="Host Address"
+                          initval="0x00"
+                          name="MADDR"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Host Data"
+                          initval="0x00"
+                          name="MDATA"
+                          offset="0x8"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Control A"
+                          initval="0x00"
+                          name="SCTRLA"
+                          offset="0x9"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Enable" mask="0x01" name="ENABLE" rw="RW"/>
+                    <bitfield caption="Smart Mode Enable" mask="0x02" name="SMEN" rw="RW"/>
+                    <bitfield caption="Address Recognition Mode"
+                              mask="0x04"
+                              name="PMEN"
+                              rw="RW"/>
+                    <bitfield caption="Stop Interrupt Enable" mask="0x20" name="PIEN" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Enable"
+                              mask="0x40"
+                              name="APIEN"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Enable" mask="0x80" name="DIEN" rw="RW"/>
+                </register>
+                <register caption="Client Control B"
+                          initval="0x00"
+                          name="SCTRLB"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Command"
+                              mask="0x03"
+                              name="SCMD"
+                              rw="RW"
+                              values="TWI_SCMD"/>
+                    <bitfield caption="Acknowledge Action"
+                              mask="0x04"
+                              name="ACKACT"
+                              rw="RW"
+                              values="TWI_ACKACT"/>
+                </register>
+                <register caption="Client Status"
+                          initval="0x00"
+                          name="SSTATUS"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address or Stop"
+                              mask="0x01"
+                              name="AP"
+                              rw="RW"
+                              values="TWI_AP"/>
+                    <bitfield caption="Read/Write Direction" mask="0x02" name="DIR" rw="RW"/>
+                    <bitfield caption="Bus Error" mask="0x04" name="BUSERR" rw="RW"/>
+                    <bitfield caption="Collision" mask="0x08" name="COLL" rw="RW"/>
+                    <bitfield caption="Received Acknowledge" mask="0x10" name="RXACK" rw="RW"/>
+                    <bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD" rw="RW"/>
+                    <bitfield caption="Address or Stop Interrupt Flag"
+                              mask="0x40"
+                              name="APIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF" rw="RW"/>
+                </register>
+                <register caption="Client Address"
+                          initval="0x00"
+                          name="SADDR"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address" mask="0xFF" name="ADDR" rw="RW"/>
+                </register>
+                <register caption="Client Data"
+                          initval="0x00"
+                          name="SDATA"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Data" mask="0xFF" name="DATA" rw="RW"/>
+                </register>
+                <register caption="Client Address Mask"
+                          initval="0x00"
+                          name="SADDRMASK"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Address Mask Enable" mask="0x01" name="ADDREN" rw="RW"/>
+                    <bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Fast-mode Enable select" name="TWI_FMEN">
+                <value caption="SCL duty cycle operating according to Sm specification"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="SCL duty cycle operating according to Fm specification"
+                       name="ON"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="Fast-mode Plus Enable select" name="TWI_FMPEN">
+                <value caption="Operating in Standard-mode or Fast-mode"
+                       name="OFF"
+                       value="0x0"/>
+                <value caption="Operating in Fast-mode Plus" name="ON" value="0x1"/>
+            </value-group>
+            <value-group caption="Input voltage transition level select" name="TWI_INPUTLVL">
+                <value caption="I2C input voltage transition level" name="I2C" value="0x0"/>
+                <value caption="SMBus 3.0 input voltage transition level"
+                       name="SMBUS"
+                       value="0x1"/>
+            </value-group>
+            <value-group caption="SDA Hold Time select" name="TWI_SDAHOLD">
+                <value caption="No SDA Hold Delay" name="OFF" value="0x0"/>
+                <value caption="Short SDA hold time" name="50NS" value="0x1"/>
+                <value caption="Meets SMBUS 2.0 specification under typical conditions"
+                       name="300NS"
+                       value="0x2"/>
+                <value caption="Meets SMBUS 2.0 specificaiton across all corners"
+                       name="500NS"
+                       value="0x3"/>
+            </value-group>
+            <value-group caption="SDA Setup Time select" name="TWI_SDASETUP">
+                <value caption="SDA setup time is four clock cycles" name="4CYC" value="0"/>
+                <value caption="SDA setup time is eight clock cycle" name="8CYC" value="1"/>
+            </value-group>
+            <value-group caption="Debug Run select" name="TWI_DBGRUN">
+                <value caption="The peripheral is halted in Break Debug mode and ignores events"
+                       name="HALT"
+                       value="0"/>
+                <value caption="The peripheral will continue to run in Break Debug mode when the CPU is halted"
+                       name="RUN"
+                       value="1"/>
+            </value-group>
+            <value-group caption="Inactive Bus Time-Out select" name="TWI_TIMEOUT">
+                <value caption="Bus time-out disabled. I2C." name="DISABLED" value="0"/>
+                <value caption="50us - SMBus" name="50US" value="1"/>
+                <value caption="100us" name="100US" value="2"/>
+                <value caption="200us" name="200US" value="3"/>
+            </value-group>
+            <value-group caption="Acknowledge Action select" name="TWI_ACKACT">
+                <value caption="Send ACK" name="ACK" value="0x0"/>
+                <value caption="Send NACK" name="NACK" value="0x1"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_MCMD">
+                <value caption="No action" name="NOACT" value="0"/>
+                <value caption="Execute Acknowledge Action followed by repeated Start."
+                       name="REPSTART"
+                       value="1"/>
+                <value caption="Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR."
+                       name="RECVTRANS"
+                       value="2"/>
+                <value caption="Execute Acknowledge Action followed by issuing a Stop condition."
+                       name="STOP"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Bus State select" name="TWI_BUSSTATE">
+                <value caption="Unknown bus state" name="UNKNOWN" value="0"/>
+                <value caption="Bus is idle" name="IDLE" value="1"/>
+                <value caption="This TWI controls the bus" name="OWNER" value="2"/>
+                <value caption="The bus is busy" name="BUSY" value="3"/>
+            </value-group>
+            <value-group caption="Command select" name="TWI_SCMD">
+                <value caption="No Action" name="NOACT" value="0"/>
+                <value caption="Complete transaction" name="COMPTRANS" value="2"/>
+                <value caption="Used in response to an interrupt"
+                       name="RESPONSE"
+                       value="3"/>
+            </value-group>
+            <value-group caption="Address or Stop select" name="TWI_AP">
+                <value caption="A Stop condition generated the interrupt on APIF flag"
+                       name="STOP"
+                       value="0"/>
+                <value caption="Address detection generated the interrupt on APIF flag"
+                       name="ADR"
+                       value="1"/>
+            </value-group>
+        </module>
+        <module caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                id="uart_autobd_v4"
+                name="USART">
+            <register-group caption="Universal Synchronous and Asynchronous Receiver and Transmitter"
+                            name="USART"
+                            size="0x10">
+                <register caption="Receive Data Low Byte"
+                          initval="0x00"
+                          name="RXDATAL"
+                          offset="0x0"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="RX Data" mask="0xFF" name="DATA" rw="R"/>
+                </register>
+                <register caption="Receive Data High Byte"
+                          initval="0x00"
+                          name="RXDATAH"
+                          offset="0x1"
+                          rw="R"
+                          size="1">
+                    <bitfield caption="Receiver Data Register"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="R"/>
+                    <bitfield caption="Parity Error" mask="0x02" name="PERR" rw="R"/>
+                    <bitfield caption="Frame Error" mask="0x04" name="FERR" rw="R"/>
+                    <bitfield caption="Buffer Overflow" mask="0x40" name="BUFOVF" rw="R"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Transmit Data Low Byte"
+                          initval="0x00"
+                          name="TXDATAL"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register"
+                              mask="0xFF"
+                              name="DATA"
+                              rw="RW"/>
+                </register>
+                <register caption="Transmit Data High Byte"
+                          initval="0x00"
+                          name="TXDATAH"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit Data Register (CHSIZE=9bit)"
+                              mask="0x01"
+                              name="DATA8"
+                              rw="RW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Wait For Break" mask="0x01" name="WFB" rw="RW"/>
+                    <bitfield caption="Break Detected Flag" mask="0x02" name="BDF" rw="RW"/>
+                    <bitfield caption="Inconsistent Sync Field Interrupt Flag"
+                              mask="0x08"
+                              name="ISFIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Start Interrupt"
+                              mask="0x10"
+                              name="RXSIF"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Flag"
+                              mask="0x20"
+                              name="DREIF"
+                              rw="R"/>
+                    <bitfield caption="Transmit Interrupt Flag"
+                              mask="0x40"
+                              name="TXCIF"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Flag"
+                              mask="0x80"
+                              name="RXCIF"
+                              rw="R"/>
+                </register>
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x5"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="RS485 Mode internal transmitter"
+                              mask="0x01"
+                              name="RS485"
+                              rw="RW"
+                              values="USART_RS485"/>
+                    <bitfield caption="Auto-baud Error Interrupt Enable"
+                              mask="0x04"
+                              name="ABEIE"
+                              rw="RW"/>
+                    <bitfield caption="Loop-back Mode Enable" mask="0x08" name="LBME" rw="RW"/>
+                    <bitfield caption="Receiver Start Frame Interrupt Enable"
+                              mask="0x10"
+                              name="RXSIE"
+                              rw="RW"/>
+                    <bitfield caption="Data Register Empty Interrupt Enable"
+                              mask="0x20"
+                              name="DREIE"
+                              rw="RW"/>
+                    <bitfield caption="Transmit Complete Interrupt Enable"
+                              mask="0x40"
+                              name="TXCIE"
+                              rw="RW"/>
+                    <bitfield caption="Receive Complete Interrupt Enable"
+                              mask="0x80"
+                              name="RXCIE"
+                              rw="RW"/>
+                </register>
+                <register caption="Control B"
+                          initval="0x00"
+                          name="CTRLB"
+                          offset="0x6"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Multi-processor Communication Mode"
+                              mask="0x01"
+                              name="MPCM"
+                              rw="RW"/>
+                    <bitfield caption="Receiver Mode"
+                              mask="0x06"
+                              name="RXMODE"
+                              rw="RW"
+                              values="USART_RXMODE"/>
+                    <bitfield caption="Open Drain Mode Enable"
+                              mask="0x08"
+                              name="ODME"
+                              rw="RW"/>
+                    <bitfield caption="Start Frame Detection Enable"
+                              mask="0x10"
+                              name="SFDEN"
+                              rw="RW"/>
+                    <bitfield caption="Transmitter Enable" mask="0x40" name="TXEN" rw="RW"/>
+                    <bitfield caption="Reciever enable" mask="0x80" name="RXEN" rw="RW"/>
+                </register>
+                <register caption="Control C"
+                          initval="0x03"
+                          name="CTRLC"
+                          offset="0x7"
+                          rw="RW"
+                          size="1">
+                    <mode name="NORMAL" qualifier="USART.CTRLC.CMODE" value="0x00 0x01 0x02"/>
+                    <mode name="MSPI" qualifier="USART.CTRLC.CMODE" value="0x03"/>
+                    <bitfield caption="Communication Mode"
+                              mask="0xC0"
+                              name="CMODE"
+                              rw="RW"
+                              values="USART_CMODE"/>
+                    <bitfield caption="SPI Host Mode, Clock Phase"
+                              mask="0x02"
+                              modes="MSPI"
+                              name="UCPHA"
+                              rw="RW"/>
+                    <bitfield caption="SPI Host Mode, Data Order"
+                              mask="0x04"
+                              modes="MSPI"
+                              name="UDORD"
+                              rw="RW"/>
+                    <bitfield caption="Character Size"
+                              mask="0x07"
+                              modes="NORMAL"
+                              name="CHSIZE"
+                              rw="RW"
+                              values="USART_NORMAL_CHSIZE"/>
+                    <bitfield caption="Stop Bit Mode"
+                              mask="0x08"
+                              modes="NORMAL"
+                              name="SBMODE"
+                              rw="RW"
+                              values="USART_NORMAL_SBMODE"/>
+                    <bitfield caption="Parity Mode"
+                              mask="0x30"
+                              modes="NORMAL"
+                              name="PMODE"
+                              rw="RW"
+                              values="USART_NORMAL_PMODE"/>
+                </register>
+                <register caption="Baud Rate"
+                          initval="0x0000"
+                          name="BAUD"
+                          offset="0x8"
+                          rw="RW"
+                          size="2"/>
+                <register caption="Control D"
+                          initval="0x00"
+                          name="CTRLD"
+                          offset="0xA"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Auto Baud Window"
+                              mask="0xC0"
+                              name="ABW"
+                              rw="RW"
+                              values="USART_ABW"/>
+                </register>
+                <register caption="Debug Control"
+                          initval="0x00"
+                          name="DBGCTRL"
+                          offset="0xB"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Debug Run" mask="0x01" name="DBGRUN" rw="RW"/>
+                </register>
+                <register caption="Event Control"
+                          initval="0x00"
+                          name="EVCTRL"
+                          offset="0xC"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="IrDA Event Input Enable"
+                              mask="0x01"
+                              name="IREI"
+                              rw="RW"/>
+                </register>
+                <register caption="IRCOM Transmitter Pulse Length Control"
+                          initval="0x00"
+                          name="TXPLCTRL"
+                          offset="0xD"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Transmit pulse length" mask="0xFF" name="TXPL" rw="RW"/>
+                </register>
+                <register caption="IRCOM Receiver Pulse Length Control"
+                          initval="0x00"
+                          name="RXPLCTRL"
+                          offset="0xE"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Receiver Pulse Lenght" mask="0x7F" name="RXPL" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="RS485 Mode internal transmitter select" name="USART_RS485">
+                <value caption="RS485 Mode disabled" name="DISABLE" value="0x0"/>
+                <value caption="RS485 Mode enabled" name="ENABLE" value="0x1"/>
+            </value-group>
+            <value-group caption="Receiver Mode select" name="USART_RXMODE">
+                <value caption="Normal mode" name="NORMAL" value="0x0"/>
+                <value caption="CLK2x mode" name="CLK2X" value="0x1"/>
+                <value caption="Generic autobaud mode" name="GENAUTO" value="0x2"/>
+                <value caption="LIN constrained autobaud mode" name="LINAUTO" value="0x3"/>
+            </value-group>
+            <value-group caption="Communication Mode select" name="USART_CMODE">
+                <value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
+                <value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
+                <value caption="Infrared Communication" name="IRCOM" value="0x02"/>
+                <value caption="SPI Host Mode" name="MSPI" value="0x03"/>
+            </value-group>
+            <value-group caption="Character Size select" name="USART_NORMAL_CHSIZE">
+                <value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
+                <value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
+                <value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
+                <value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
+                <value caption="Character size: 9 bit read low byte first"
+                       name="9BITL"
+                       value="0x06"/>
+                <value caption="Character size: 9 bit read high byte first"
+                       name="9BITH"
+                       value="0x07"/>
+            </value-group>
+            <value-group caption="Parity Mode select" name="USART_NORMAL_PMODE">
+                <value caption="No Parity" name="DISABLED" value="0x00"/>
+                <value caption="Even Parity" name="EVEN" value="0x02"/>
+                <value caption="Odd Parity" name="ODD" value="0x03"/>
+            </value-group>
+            <value-group caption="Stop Bit Mode select" name="USART_NORMAL_SBMODE">
+                <value caption="1 stop bit" name="1BIT" value="0x0"/>
+                <value caption="2 stop bits" name="2BIT" value="0x1"/>
+            </value-group>
+            <value-group caption="Auto Baud Window select" name="USART_ABW">
+                <value caption="18% tolerance" name="WDW0" value="0x0"/>
+                <value caption="15% tolerance" name="WDW1" value="0x1"/>
+                <value caption="21% tolerance" name="WDW2" value="0x2"/>
+                <value caption="25% tolerance" name="WDW3" value="0x3"/>
+            </value-group>
+        </module>
+        <module caption="User Row" id="avrea" name="USERROW">
+            <register-group caption="User Row" name="USERROW" size="0x40">
+                <register caption="User Row Byte 0"
+                          name="USERROW0"
+                          offset="0x00"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 1"
+                          name="USERROW1"
+                          offset="0x01"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 2"
+                          name="USERROW2"
+                          offset="0x02"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 3"
+                          name="USERROW3"
+                          offset="0x03"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 4"
+                          name="USERROW4"
+                          offset="0x04"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 5"
+                          name="USERROW5"
+                          offset="0x05"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 6"
+                          name="USERROW6"
+                          offset="0x06"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 7"
+                          name="USERROW7"
+                          offset="0x07"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 8"
+                          name="USERROW8"
+                          offset="0x08"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 9"
+                          name="USERROW9"
+                          offset="0x09"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 10"
+                          name="USERROW10"
+                          offset="0x0A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 11"
+                          name="USERROW11"
+                          offset="0x0B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 12"
+                          name="USERROW12"
+                          offset="0x0C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 13"
+                          name="USERROW13"
+                          offset="0x0D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 14"
+                          name="USERROW14"
+                          offset="0x0E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 15"
+                          name="USERROW15"
+                          offset="0x0F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 16"
+                          name="USERROW16"
+                          offset="0x10"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 17"
+                          name="USERROW17"
+                          offset="0x11"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 18"
+                          name="USERROW18"
+                          offset="0x12"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 19"
+                          name="USERROW19"
+                          offset="0x13"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 20"
+                          name="USERROW20"
+                          offset="0x14"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 21"
+                          name="USERROW21"
+                          offset="0x15"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 22"
+                          name="USERROW22"
+                          offset="0x16"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 23"
+                          name="USERROW23"
+                          offset="0x17"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 24"
+                          name="USERROW24"
+                          offset="0x18"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 25"
+                          name="USERROW25"
+                          offset="0x19"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 26"
+                          name="USERROW26"
+                          offset="0x1A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 27"
+                          name="USERROW27"
+                          offset="0x1B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 28"
+                          name="USERROW28"
+                          offset="0x1C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 29"
+                          name="USERROW29"
+                          offset="0x1D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 30"
+                          name="USERROW30"
+                          offset="0x1E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 31"
+                          name="USERROW31"
+                          offset="0x1F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 32"
+                          name="USERROW32"
+                          offset="0x20"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 33"
+                          name="USERROW33"
+                          offset="0x21"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 34"
+                          name="USERROW34"
+                          offset="0x22"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 35"
+                          name="USERROW35"
+                          offset="0x23"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 36"
+                          name="USERROW36"
+                          offset="0x24"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 37"
+                          name="USERROW37"
+                          offset="0x25"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 38"
+                          name="USERROW38"
+                          offset="0x26"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 39"
+                          name="USERROW39"
+                          offset="0x27"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 40"
+                          name="USERROW40"
+                          offset="0x28"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 41"
+                          name="USERROW41"
+                          offset="0x29"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 42"
+                          name="USERROW42"
+                          offset="0x2A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 43"
+                          name="USERROW43"
+                          offset="0x2B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 44"
+                          name="USERROW44"
+                          offset="0x2C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 45"
+                          name="USERROW45"
+                          offset="0x2D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 46"
+                          name="USERROW46"
+                          offset="0x2E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 47"
+                          name="USERROW47"
+                          offset="0x2F"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 48"
+                          name="USERROW48"
+                          offset="0x30"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 49"
+                          name="USERROW49"
+                          offset="0x31"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 50"
+                          name="USERROW50"
+                          offset="0x32"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 51"
+                          name="USERROW51"
+                          offset="0x33"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 52"
+                          name="USERROW52"
+                          offset="0x34"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 53"
+                          name="USERROW53"
+                          offset="0x35"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 54"
+                          name="USERROW54"
+                          offset="0x36"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 55"
+                          name="USERROW55"
+                          offset="0x37"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 56"
+                          name="USERROW56"
+                          offset="0x38"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 57"
+                          name="USERROW57"
+                          offset="0x39"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 58"
+                          name="USERROW58"
+                          offset="0x3A"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 59"
+                          name="USERROW59"
+                          offset="0x3B"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 60"
+                          name="USERROW60"
+                          offset="0x3C"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 61"
+                          name="USERROW61"
+                          offset="0x3D"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 62"
+                          name="USERROW62"
+                          offset="0x3E"
+                          rw="RW"
+                          size="1"/>
+                <register caption="User Row Byte 63"
+                          name="USERROW63"
+                          offset="0x3F"
+                          rw="RW"
+                          size="1"/>
+            </register-group>
+        </module>
+        <module caption="Virtual Ports" id="gpio_ports_avr_v3_vport" name="VPORT">
+            <register-group caption="Virtual Ports" name="VPORT" size="0x4">
+                <register caption="Data Direction"
+                          initval="0x00"
+                          name="DIR"
+                          offset="0x0"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Output Value"
+                          initval="0x00"
+                          name="OUT"
+                          offset="0x1"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Input Value"
+                          initval="0x00"
+                          name="IN"
+                          offset="0x2"
+                          rw="RW"
+                          size="1"/>
+                <register caption="Interrupt Flags"
+                          initval="0x00"
+                          name="INTFLAGS"
+                          offset="0x3"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Pin Interrupt Flag" mask="0xFF" name="INT" rw="RW"/>
+                </register>
+            </register-group>
+        </module>
+        <module caption="Voltage reference" id="avrea" name="VREF">
+            <register-group caption="Voltage reference" name="VREF" size="0x2">
+                <register caption="DAC0 Reference"
+                          initval="0x00"
+                          name="DAC0REF"
+                          offset="0x2"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+                <register caption="AC Reference"
+                          initval="0x00"
+                          name="ACREF"
+                          offset="0x4"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Reference select"
+                              mask="0x07"
+                              name="REFSEL"
+                              rw="RW"
+                              values="VREF_REFSEL"/>
+                    <bitfield caption="Always on" mask="0x80" name="ALWAYSON" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Reference select" name="VREF_REFSEL">
+                <value caption="Internal 1.024V reference" name="1V024" value="0x0"/>
+                <value caption="Internal 2.048V reference" name="2V048" value="0x1"/>
+                <value caption="Internal 4.096V reference" name="4V096" value="0x2"/>
+                <value caption="Internal 2.500V reference" name="2V500" value="0x3"/>
+                <value caption="VDD as reference" name="VDD" value="0x5"/>
+                <value caption="External reference on VREFA pin" name="VREFA" value="0x6"/>
+            </value-group>
+        </module>
+        <module caption="Watch-Dog Timer" id="wdt_windowed_v2" name="WDT">
+            <register-group caption="Watch-Dog Timer" name="WDT" size="0x10">
+                <register caption="Control A"
+                          initval="0x00"
+                          name="CTRLA"
+                          offset="0x0"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Period"
+                              mask="0x0F"
+                              name="PERIOD"
+                              rw="RW"
+                              values="WDT_PERIOD"/>
+                    <bitfield caption="Window"
+                              mask="0xF0"
+                              name="WINDOW"
+                              rw="RW"
+                              values="WDT_WINDOW"/>
+                </register>
+                <register caption="Status"
+                          initval="0x00"
+                          name="STATUS"
+                          offset="0x1"
+                          rw="RW"
+                          size="1">
+                    <bitfield caption="Syncronization busy"
+                              mask="0x01"
+                              name="SYNCBUSY"
+                              rw="R"/>
+                    <bitfield caption="Lock enable" mask="0x80" name="LOCK" rw="RW"/>
+                </register>
+            </register-group>
+            <value-group caption="Period select" name="WDT_PERIOD">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+            <value-group caption="Window select" name="WDT_WINDOW">
+                <value caption="Off" name="OFF" value="0x00"/>
+                <value caption="8 cycles (8ms)" name="8CLK" value="0x01"/>
+                <value caption="16 cycles (16ms)" name="16CLK" value="0x02"/>
+                <value caption="32 cycles (32ms)" name="32CLK" value="0x03"/>
+                <value caption="64 cycles (64ms)" name="64CLK" value="0x04"/>
+                <value caption="128 cycles (0.128s)" name="128CLK" value="0x05"/>
+                <value caption="256 cycles (0.256s)" name="256CLK" value="0x06"/>
+                <value caption="512 cycles (0.512s)" name="512CLK" value="0x07"/>
+                <value caption="1K cycles (1.0s)" name="1KCLK" value="0x08"/>
+                <value caption="2K cycles (2.0s)" name="2KCLK" value="0x09"/>
+                <value caption="4K cycles (4.1s)" name="4KCLK" value="0x0A"/>
+                <value caption="8K cycles (8.2s)" name="8KCLK" value="0x0B"/>
+            </value-group>
+        </module>
+    </modules>
+    <pinouts>
+        <pinout name="QFN48">
+            <pin pad="PA5" position="1"/>
+            <pin pad="PA6" position="2"/>
+            <pin pad="PA7" position="3"/>
+            <pin pad="PB0" position="4"/>
+            <pin pad="PB1" position="5"/>
+            <pin pad="PB2" position="6"/>
+            <pin pad="PB3" position="7"/>
+            <pin pad="PB4" position="8"/>
+            <pin pad="PB5" position="9"/>
+            <pin pad="PC0" position="10"/>
+            <pin pad="PC1" position="11"/>
+            <pin pad="PC2" position="12"/>
+            <pin pad="PC3" position="13"/>
+            <pin pad="VDD2" position="14"/>
+            <pin pad="GND2" position="15"/>
+            <pin pad="PC4" position="16"/>
+            <pin pad="PC5" position="17"/>
+            <pin pad="PC6" position="18"/>
+            <pin pad="PC7" position="19"/>
+            <pin pad="PD0" position="20"/>
+            <pin pad="PD1" position="21"/>
+            <pin pad="PD2" position="22"/>
+            <pin pad="PD3" position="23"/>
+            <pin pad="PD4" position="24"/>
+            <pin pad="PD5" position="25"/>
+            <pin pad="PD6" position="26"/>
+            <pin pad="PD7" position="27"/>
+            <pin pad="VDD" position="28"/>
+            <pin pad="GND" position="29"/>
+            <pin pad="PE0" position="30"/>
+            <pin pad="PE1" position="31"/>
+            <pin pad="PE2" position="32"/>
+            <pin pad="PE3" position="33"/>
+            <pin pad="PF0" position="34"/>
+            <pin pad="PF1" position="35"/>
+            <pin pad="PF2" position="36"/>
+            <pin pad="PF3" position="37"/>
+            <pin pad="PF4" position="38"/>
+            <pin pad="PF5" position="39"/>
+            <pin pad="PF6" position="40"/>
+            <pin pad="PF7" position="41"/>
+            <pin pad="VDD1" position="42"/>
+            <pin pad="GND1" position="43"/>
+            <pin pad="PA0" position="44"/>
+            <pin pad="PA1" position="45"/>
+            <pin pad="PA2" position="46"/>
+            <pin pad="PA3" position="47"/>
+            <pin pad="PA4" position="48"/>
+        </pinout>
+    </pinouts>
 </target-description-file>
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
index ee5cf6cb..abaa2d29 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN128.xml
@@ -10,7 +10,7 @@
         <variant ordercode="AT90CAN128-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="AT90CAN128" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90CAN128" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
index 8516a990..57dbd826 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN32.xml
@@ -10,7 +10,7 @@
         <variant ordercode="AT90CAN32-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="AT90CAN32" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90CAN32" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
index 4fac3a1a..0b46af16 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90CAN64.xml
@@ -10,7 +10,7 @@
         <variant ordercode="AT90CAN64-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="AT90CAN64" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90CAN64" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
index cce3e257..8566ad6a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM1.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90PWM1-MU" package="VQFN32" pinout="QFN32" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90PWM1-SU" package="SOIC24" pinout="SOIC24" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
index 6cb23669..2b56cb3c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM161.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90PWM161-MN" package="VQFN32" pinout="QFN32" tempmax="105" tempmin="-40"/>
         <variant ordercode="AT90PWM161-SN" package="SOIC20" pinout="SOIC20" tempmax="105" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM161" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM161" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
index 545cad3f..c137ac74 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM216.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="AT90PWM216-16SU" package="SOIC24" pinout="SOIC24" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM216" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM216" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
index f3c18719..9e205a7d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM2B.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="AT90PWM2B-16SU" package="SOIC24" pinout="SOIC24" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM2B" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM2B" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
index c4d20452..59c4ff27 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM316.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90PWM316-16SU" package="SOIC32" pinout="SOIC32" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90PWM316-16MU" package="VQFN32" pinout="QFN32" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM316" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM316" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
index 1e8209da..6c4c1a3a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM3B.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90PWM3B-SU" package="SOIC32" pinout="SOIC32" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90PWM3B-MU" package="QFN32" pinout="QFN32" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM3B" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM3B" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
index 40b02b6e..743559d2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90PWM81.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90PWM81-MN" package="VQFN32" pinout="QFN32" tempmax="105" tempmin="-40"/>
         <variant ordercode="AT90PWM81-SN" package="SOIC20" pinout="SOIC20" tempmax="105" tempmin="-40"/>
     </variants>
-    <device name="AT90PWM81" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90PWM81" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
index 4d7cd3b9..34999a93 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1286.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90USB1286-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90USB1286-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB1286" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB1286" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
index 35c2b580..212d55f6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB1287.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90USB1287-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90USB1287-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB1287" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB1287" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
index 749e5ff7..a4520bca 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB162.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90USB162-AU" package="TQFP32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90USB162-MU" package="VQFN32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB162" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB162" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
index 76297679..45b61a02 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB646.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90USB646-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90USB646-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB646" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB646" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
index d10a907b..f7eb0732 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB647.xml
@@ -4,7 +4,7 @@
         <variant ordercode="AT90USB647-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="AT90USB647-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB647" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB647" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
index 9785d6ef..2cf7b173 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/AT90USB82.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="AT90USB82-MU" package="VQFN32" pinout="QFN32" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="AT90USB82" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="AT90USB82" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
index 1d047ab9..58881078 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega128-16MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="TQFPQFN64"
                  package="QFN64" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega128" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega128" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
index febe82b4..55ce5996 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1280.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega1280-16CU" speedmax="16000000" tempmin="-40" tempmax="85" vccmin="2.7" vccmax="5.5"
                  package="CBGA100" pinout="CBGA100"/>
     </variants>
-    <device name="ATmega1280" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega1280" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
index 20e6deaf..4249cd55 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1281.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega1281-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega1281" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega1281" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
index 000442d0..c5359663 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega1284-MU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="QFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega1284" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega1284" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284P.xml
index 553f48b9..92160189 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284P.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega1284P-MN" tempmin="-40" tempmax="85" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="QFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega1284P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega1284P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
index 3b19580c..ece42e27 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1284RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega1284RFR2-ZFR" package="VQFN48" pinout="QFN48" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega1284RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega1284RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
index f6173407..66cdb225 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128A.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega128A-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega128A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega128A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
index 76ed3b4a..87a12bb1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFA1.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega128RFA1-ZU" tempmin="-40" tempmax="85" pinout="QFN64" package="QFN64"/>
     </variants>
-    <device name="ATmega128RFA1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega128RFA1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
index 1514cded..4e066c41 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA128RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega128RFR2-ZFR" package="QFN64" pinout="QFN64" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega128RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega128RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x20000">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
index 8d23f156..92ec9f06 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega16-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN44"
                  package="QFN44" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega16" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega16" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1608.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1608.xml
index f2c59877..1ea4fda0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1608.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1608.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega1608-XFR" package="SSOP28" pinout="SSOP28" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega1608" family="AVR8">
+    <device name="ATmega1608" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x4000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1609.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1609.xml
index f3731fba..7786dfee 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1609.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA1609.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega1609-MFR" package="UQFN48" pinout="QFN48" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega1609" family="AVR8">
+    <device name="ATmega1609" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x4000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
index 46305ea2..6c07c77a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA162.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATmega162-AU" tempmin="-40" tempmax="85" pinout="QFP_QFN_44" package="TQFP44"/>
         <variant ordercode="ATmega162-MU" tempmin="-40" tempmax="85" pinout="QFP_QFN_44" package="VQFN44"/>
     </variants>
-    <device name="ATmega162" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega162" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
index 7ac4fedc..887273c4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164A.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega164A-CU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="VFBGA49"
                  package="VFBGA49" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega164A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega164A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
index 0ad655ce..90df37cb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164P.xml
@@ -24,7 +24,7 @@
         <variant ordercode="ATmega164P-20MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="TQFP_VQFN_44"
                  package="VQFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega164P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega164P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
index a324f4c3..ec639865 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA164PA.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega164PA-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="VQFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega164PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega164PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
index 1112fb14..ef7bd2f7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165A.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega165A-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega165A-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega165A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega165A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
index 4d35946f..989c2284 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165P.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega165P-AU" tempmin="-40" tempmax="85" pinout="QFP_QFN_64" package="TQFP64"/>
         <variant ordercode="ATmega165P-MU" tempmin="-40" tempmax="85" pinout="QFP_QFN_64" package="VQFN64"/>
     </variants>
-    <device name="ATmega165P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega165P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
index af862780..c0ae4d33 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA165PA.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega165PA-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega165PA-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega165PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega165PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
index 0d917ebe..fdf65f8b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega168-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega168" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega168" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
index 55593d17..ef176a2c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168A.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega168A-PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega168A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega168A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
index e41c5555..87b13dae 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168P.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega168P-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega168P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega168P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
index cd0d906f..8e9310d4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PA.xml
@@ -16,7 +16,7 @@
         <variant ordercode="ATmega168PA-PN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega168PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega168PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
index 87fda80a..7028d0c5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA168PB.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega168PB-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="VQFN32"
                  package="VQFN32" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega168PB" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega168PB" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
index b58e7fd4..045bbdc4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169A.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega169A-MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega169A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega169A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
index 425f338a..b0d9d8ea 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169P.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega169P-16MCH" tempmin="-40" tempmax="85" speedmax="16000000" pinout="DRQFN64"
                  package="DRQFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega169P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega169P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
index bf6a55e4..babef4fa 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA169PA.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega169PA-MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega169PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega169PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16A.xml
index 11ac8917..09b5b79d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16A.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega16A-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN44"
                  package="QFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega16A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega16A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
index a39904d6..7ce103e4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16M1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega16M1-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN32"
                  package="QFN32" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega16M1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega16M1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
index bd01a898..525ef9ac 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U2.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega16U2-MU" speedmax="16000000" tempmin="-40" tempmax="85" vccmin="2.7" vccmax="5.5"
                  package="QFN32" pinout="QFP32"/>
     </variants>
-    <device name="ATmega16U2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega16U2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
index 637b8afe..6b0a2c54 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA16U4.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega16U4RC-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN44"
                  package="QFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega16U4" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega16U4" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
index d2f52d07..dddf6d8d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2560.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega2560-16CU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="CBGA100"
                  package="CBGA100" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega2560" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega2560" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x40000">
                 <memory-segment start="0x0000" size="0x40000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
index 1c277a3c..b04d8bd4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2561.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega2561-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega2561" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega2561" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x40000">
                 <memory-segment start="0x0000" size="0x40000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
index 82513575..38cde75c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA2564RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega2564RFR2-ZFR" package="VQFN48" pinout="QFN48" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega2564RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega2564RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x40000">
                 <memory-segment start="0x0000" size="0x40000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
index 1123eb84..af4d121d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA256RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega256RFR2-ZFR" package="QFN64" pinout="QFN64" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega256RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega256RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x40000">
                 <memory-segment start="0x0000" size="0x40000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
index 296b78b3..e23723ac 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega32-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN44"
                  package="QFN44" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega32" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3208.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3208.xml
index 576924f0..798eea89 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3208.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3208.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega3208-XFR" package="SSOP28" pinout="SSOP28" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega3208" family="AVR8">
+    <device name="ATmega3208" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3209.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3209.xml
index 18782fc4..5d86b096 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3209.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3209.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega3209-MFR" package="UQFN48" pinout="QFN48" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega3209" family="AVR8">
+    <device name="ATmega3209" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
index 67510d99..691d52be 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324A.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega324A-CU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="VFBGA49"
                  package="VFBGA49" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega324A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega324A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
index 262c561f..407a05ec 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324P.xml
@@ -26,7 +26,7 @@
         <variant ordercode="ATmega324P-20MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="TQFP_VQFN_44"
                  package="VQFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega324P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega324P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
index e1d5a7a8..8d8d4e25 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PA.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega324PA-CU" package="VFBGA49" pinout="BGA_49" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device name="ATmega324PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega324PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
index e2af246a..760ee2a5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA324PB.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega324PB-MNR" tempmin="-40" tempmax="105" speedmax="20000000" pinout="VQFN44"
                  package="VQFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega324PB" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega324PB" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
index 2466d5ec..ed6a27a1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega325-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega325-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega325" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega325" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
index 08be523e..ad93251e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3250-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3250" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3250" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
index 9fbea070..aa5f4964 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250A.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3250A-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3250A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3250A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
index 1daaf56f..bdbd0949 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250P.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3250P-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3250P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3250P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
index e927a550..91a56282 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3250PA.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3250PA-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3250PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3250PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
index 9395f0a1..ca44455e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325A.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega325A-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega325A-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega325A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega325A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
index 56cc82dd..fcd110c4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325P.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega325P-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega325P-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega325P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega325P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
index ef3a77f1..19968efb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA325PA.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega325PA-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega325PA-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega325PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega325PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
index a7fdbc1b..423738ee 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega328-PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega328" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega328" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
index 3a25ad7d..803c2baa 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328P.xml
@@ -16,7 +16,7 @@
         <variant ordercode="ATmega328P-PN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega328P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega328P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328PB.xml
index de7b22cb..d6993c0f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA328PB.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega328PB-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="VQFN32"
                  package="VQFN32" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega328PB" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega328PB" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
index 9ede900e..4ad891fa 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega329-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega329" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega329" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
index b476f777..8443fd47 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3290-16AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3290" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3290" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
index 91b52019..dc45bd3b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290A.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3290A-AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3290A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3290A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
index 3276dd15..b36bf2de 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290P.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3290P-AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3290P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3290P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
index eb4a4bb5..66447c00 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA3290PA.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega3290PA-AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega3290PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega3290PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
index 6174918f..d579464e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329A.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega329A-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="QFN64"
                  package="QFN64" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega329A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega329A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
index 9e7763b9..27f6a261 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329P.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega329P-20MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="QFN64"
                  package="QFN64" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega329P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega329P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
index 1635ca8d..c1f2c8b2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA329PA.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega329PA-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="QFN64"
                  package="QFN64" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega329PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega329PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
index e2158c69..dff1316d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32A.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATmega32A-MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="TQFPQFN44"
                  package="QFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega32A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
index 9030f96b..347d182c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32C1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega32C1-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN32"
                  package="QFN32" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega32C1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32C1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
index 3027dfee..56345c4b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32M1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega32M1-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN32"
                  package="QFN32" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega32M1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32M1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
index 73798fd9..60f47274 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U2.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega32U2-MU" speedmax="16000000" tempmin="-40" tempmax="85" vccmin="2.7" vccmax="5.5"
                  package="QFN32" pinout="QFP32"/>
     </variants>
-    <device name="ATmega32U2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32U2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
index d5332542..49302de1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA32U4.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega32U4RC-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN44"
                  package="QFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega32U4" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega32U4" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x8000">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
index 905c285a..ec5e91ec 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA406.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega406-1AAU" package="LQFP48" pinout="QFP48" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega406" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega406" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0xa000">
                 <memory-segment start="0x0000" size="0xa000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
index e13c03dd..8a857e87 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48.xml
@@ -22,7 +22,7 @@
         <variant ordercode="ATmega48-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega48" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega48" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4808.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4808.xml
index f05e0eae..ea302335 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4808.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4808.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega4808-XFR" package="SSOP28" pinout="SSOP28" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega4808" family="AVR8">
+    <device name="ATmega4808" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4809.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4809.xml
index 93d2aca0..6fb53f04 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4809.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA4809.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega4809-PF" package="PDIP40" pinout="PDIP40" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega4809" family="AVR8">
+    <device name="ATmega4809" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
index 098e40ff..8d0973d7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48A.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega48A-PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega48A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega48A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
index 8d451cab..a9abc6c3 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48P.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega48P-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega48P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega48P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
index 057dd810..c2185efd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PA.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega48PA-PN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega48PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega48PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
index fbc7548e..47162f57 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA48PB.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega48PB-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="VQFN32"
                  package="VQFN32" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega48PB" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega48PB" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
index 2f00ac27..0454912e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega64-16MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="TQFPQFN64"
                  package="QFN64" vccmin="4.5" vccmax="5.5"/>
     </variants>
-    <device name="ATmega64" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega64" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
index a529da32..47d9829f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA640.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega640-16CU" speedmax="16000000" tempmin="-40" tempmax="85" vccmin="2.7" vccmax="5.5"
                  package="CBGA100" pinout="CBGA100"/>
     </variants>
-    <device name="ATmega640" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega640" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
index 0a6758f0..f8a4ea6c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega644-20MU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="QFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega644" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega644" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
index b960fa34..bb875057 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644A.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega644A-MU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="VQFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega644A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega644A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
index b2306500..023617dd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644P.xml
@@ -26,7 +26,7 @@
         <variant ordercode="ATmega644P-20MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="TQFP_VQFN_44"
                  package="VQFN44" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega644P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega644P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
index 45611c07..35f247c6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644PA.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega644PA-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="TQFP_QFN_44"
                  package="VQFN44" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega644PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega644PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
index 60a63a6c..3b2b9c45 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA644RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega644RFR2-ZFR" package="VQFN48" pinout="QFN48" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega644RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega644RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
index 511c654d..e8c41909 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega645-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega645-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega645" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega645" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
index 6548cc8a..edbacbc2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6450-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6450" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6450" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
index ca5d2e02..b711aa2d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450A.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6450A-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6450A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6450A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
index c437950c..9184788d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6450P.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6450P-AU" package="TQFP100" pinout="QFP_100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6450P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6450P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
index 31e41780..526e092e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645A.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega645A-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega645A-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega645A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega645A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
index bc9d9303..a682bc99 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA645P.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATmega645P-AU" package="TQFP64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATmega645P-MU" package="VQFN64" pinout="QFP_QFN_64" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega645P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega645P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
index e4450615..bb2c8d50 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega649-16MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega649" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega649" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
index d620dc40..22536e93 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6490-16AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6490" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6490" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
index ce3afa25..a4572007 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490A.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6490A-AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6490A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6490A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
index c64b4efc..4a167dc1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA6490P.xml
@@ -3,7 +3,7 @@
     <variants>
         <variant ordercode="ATmega6490P-AU" package="TQFP100" pinout="QFP100" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATmega6490P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega6490P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
index 40c651ce..f23aff55 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649A.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega649A-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64" package="QFN64"
                  vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega649A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega649A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
index cd1dca04..b4c6cd42 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA649P.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega649P-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="QFN64" package="QFN64"
                  vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega649P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega649P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
index b9f98a76..802649df 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64A.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega64A-MN" tempmin="-40" tempmax="105" speedmax="16000000" pinout="TQFPQFN64"
                  package="QFN64" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega64A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega64A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
index 885714f2..8948109d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64C1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega64C1-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN32"
                  package="QFN32" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega64C1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega64C1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
index a314223e..b1e0b01f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64M1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega64M1-MU" tempmin="-40" tempmax="85" speedmax="16000000" pinout="TQFPQFN32"
                  package="QFN32" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega64M1" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega64M1" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
index e23e1fda..0c9878b2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA64RFR2.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega64RFR2-ZFR" package="QFN64" pinout="QFN64" speedmax="16000000" tempmax="125"
                  tempmin="-40" vccmax="3.6" vccmin="1.8"/>
     </variants>
-    <device name="ATmega64RFR2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega64RFR2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA808.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA808.xml
index 872855d5..ad8f404f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA808.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA808.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATmega808-XFR" package="SSOP28" pinout="SSOP28" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega808" family="AVR8">
+    <device name="ATmega808" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x2000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA809.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA809.xml
index a568cf82..b91ec9d5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA809.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA809.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega809-MFR" package="UQFN48" pinout="QFN48" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.0" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR MEGA" name="ATmega809" family="AVR8">
+    <device name="ATmega809" family="AVR8" architecture="AVR8X" avr-family="AVR MEGA">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x2000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
index e92ec850..6099b21d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega88-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega88" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega88" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
index 69b252fa..b681e584 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88A.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega88A-PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega88A" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega88A" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
index 9010b742..d35acda8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88P.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATmega88P-20PU" tempmin="-40" tempmax="85" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="2.7" vccmax="5.5"/>
     </variants>
-    <device name="ATmega88P" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega88P" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
index 0ade2086..8ec6107c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PA.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATmega88PA-PN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="PDIP28"
                  package="PDIP28" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega88PA" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega88PA" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
index 75f83d37..d90f7288 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA88PB.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATmega88PB-MN" tempmin="-40" tempmax="105" speedmax="20000000" pinout="VQFN32"
                  package="VQFN32" vccmin="1.8" vccmax="5.5"/>
     </variants>
-    <device name="ATmega88PB" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega88PB" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
index 4f89b55f..154e4ae7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/MEGA/ATMEGA8U2.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATmega8U2-MU" speedmax="16000000" tempmin="-40" tempmax="85" vccmin="2.7" vccmax="5.5"
                  package="QFN32" pinout="QFP32"/>
     </variants>
-    <device name="ATmega8U2" architecture="AVR8" avr-family="megaAVR" family="AVR8">
+    <device name="ATmega8U2" family="AVR8" architecture="AVR8" avr-family="megaAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
index 8cf6bb06..2c62000f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13.xml
@@ -22,7 +22,7 @@
         <variant ordercode="ATtiny13-20MMU" speedmax="20000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5"
                  package="MLF10" pinout="MLF10"/>
     </variants>
-    <device name="ATtiny13" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny13" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0400">
                 <memory-segment start="0x0000" size="0x0400" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
index f2839eff..e81fb296 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY13A.xml
@@ -24,7 +24,7 @@
         <variant ordercode="ATtiny13A-MMF" speedmax="20000000" tempmin="-40" tempmax="125" vccmin="1.8" vccmax="5.5"
                  package="MLF10" pinout="MLF10"/>
     </variants>
-    <device name="ATtiny13A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny13A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0400">
                 <memory-segment start="0x0000" size="0x0400" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1604.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1604.xml
index 9ca1d9db..6d90d71f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1604.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1604.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1604-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1604" family="AVR8">
+    <device name="ATtiny1604" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1606.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1606.xml
index 26dd7648..e29e1f7a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1606.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1606.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny1606-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1606" family="AVR8">
+    <device name="ATtiny1606" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1607.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1607.xml
index 35aed4a0..7397d271 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1607.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1607.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1607-MRF" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1607" family="AVR8">
+    <device name="ATtiny1607" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1614.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1614.xml
index b55ec2d8..e78cf5ef 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1614.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1614.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1614-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1614" family="AVR8">
+    <device name="ATtiny1614" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1616.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1616.xml
index e1832374..adb78f55 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1616.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1616.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny1616-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1616" family="AVR8">
+    <device name="ATtiny1616" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1617.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1617.xml
index 17b2ea3b..0d533492 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1617.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1617.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1617-MNR" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny1617" family="AVR8">
+    <device name="ATtiny1617" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xC000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1624.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1624.xml
index 5715eb31..9f2e17a6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1624.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1624.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1624-SSUR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="tinyAVR 2" name="ATtiny1624" family="AVR8">
+    <device name="ATtiny1624" family="AVR8" architecture="AVR8X" avr-family="tinyAVR 2">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1626.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1626.xml
index 9960ce5c..efa55679 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1626.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1626.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny1626-SUR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="tinyAVR 2" name="ATtiny1626" family="AVR8">
+    <device name="ATtiny1626" family="AVR8" architecture="AVR8X" avr-family="tinyAVR 2">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1627.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1627.xml
index 11d73006..275736d0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1627.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1627.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny1627-MUR" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="tinyAVR 2" name="ATtiny1627" family="AVR8">
+    <device name="ATtiny1627" family="AVR8" architecture="AVR8X" avr-family="tinyAVR 2">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
index 07cb2a60..b6804b86 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY1634.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATtiny1634-SU" package="SOIC20" pinout="SOIC_20" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny1634-MU" package="WQFN20" pinout="QFN_20" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny1634" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny1634" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
index 998cefa2..f0a4dadf 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY167.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATtiny167-MU" tempmin="-40" tempmax="85" pinout="VQFN32" package="VQFN32"/>
         <variant ordercode="ATtiny167-MMU" tempmin="-40" tempmax="85" pinout="QFN20" package="QFN20"/>
     </variants>
-    <device name="ATtiny167" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny167" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x4000">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY202.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY202.xml
index ac821938..4bae1c7e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY202.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY202.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny202-SSNR" package="SOIC8" pinout="SOIC8" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny202" family="AVR8">
+    <device name="ATtiny202" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x8800" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0040" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY204.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY204.xml
index 7c1f8ce5..32ddb037 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY204.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY204.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny204-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny204" family="AVR8">
+    <device name="ATtiny204" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x8800" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0040" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY212.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY212.xml
index 66261623..64e111b8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY212.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY212.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny212-SSNR" package="SOIC8" pinout="SOIC8" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny212" family="AVR8">
+    <device name="ATtiny212" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x8800" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0040" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY214.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY214.xml
index 3bc71508..8ea6464d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY214.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY214.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny214-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny214" family="AVR8">
+    <device name="ATtiny214" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x8800" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0040" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
index 5c8ed47c..0fa67e6e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATtiny2313-20SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="SOIC20"/>
         <variant ordercode="ATtiny2313-20MUR" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
     </variants>
-    <device name="ATtiny2313" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny2313" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
index e370a8e8..1a874382 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY2313A.xml
@@ -9,7 +9,7 @@
         <variant ordercode="ATtiny2313A-MMHR" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
         <variant ordercode="ATtiny2313A-MMH" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
     </variants>
-    <device name="ATtiny2313A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny2313A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
index 0bde694b..d8a79183 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATtiny24-20SSU" package="SOIC14" pinout="SOIC14" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny24V-10MU" package="QFN20" pinout="QFN20" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny24" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny24" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
index d276b008..54bd8d6c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY24A.xml
@@ -20,7 +20,7 @@
         <variant ordercode="ATtiny24A-SSF" package="SOIC14" pinout="SOIC_14" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device name="ATtiny24A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny24A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
index 69a2e226..a3ae1c41 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY25.xml
@@ -38,7 +38,7 @@
         <variant ordercode="ATtiny25V-20MF" package="MLF20" pinout="QFN_20" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny25" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny25" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
index 15ed0293..b6a074f4 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny261-20SU" package="SOIC20" pinout="SOIC_20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny261" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny261" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
index 08676d82..d0769aa1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY261A.xml
@@ -13,7 +13,7 @@
         <variant ordercode="ATtiny261A-MFR" tempmin="-40" tempmax="125" pinout="QFN32" package="VQFN32"/>
         <variant ordercode="ATtiny261A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
     </variants>
-    <device name="ATtiny261A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny261A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3216.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3216.xml
index 00a4468e..b5c6ec44 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3216.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3216.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny3216-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny3216" family="AVR8">
+    <device name="ATtiny3216" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3217.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3217.xml
index c36d5922..05d5451a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3217.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY3217.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny3217-MNR" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny3217" family="AVR8">
+    <device name="ATtiny3217" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x10000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x40" rw="RW" size="0x0100" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY402.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY402.xml
index 4f20dff7..2c0514eb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY402.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY402.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny402-SSNR" package="SOIC8" pinout="SOIC8" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny402" family="AVR8">
+    <device name="ATtiny402" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY404.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY404.xml
index 1e5847d9..d0f219dd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY404.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY404.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny404-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny404" family="AVR8">
+    <device name="ATtiny404" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY406.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY406.xml
index f6bb3f4d..c965235c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY406.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY406.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny406-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny406" family="AVR8">
+    <device name="ATtiny406" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY412.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY412.xml
index 38bdb20a..4f45b7cb 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY412.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY412.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny412-SSNR" package="SOIC8" pinout="SOIC8" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny412" family="AVR8">
+    <device name="ATtiny412" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY414.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY414.xml
index eb4cd016..e8b1f313 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY414.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY414.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny414-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny414" family="AVR8">
+    <device name="ATtiny414" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY416.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY416.xml
index 48087d00..7ed3e9cd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY416.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY416.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny416-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny416" family="AVR8">
+    <device name="ATtiny416" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY417.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY417.xml
index cb0eb385..ccb133aa 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY417.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY417.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny417-MNR" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny417" family="AVR8">
+    <device name="ATtiny417" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0x9000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
index 584173e0..636686e6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY4313.xml
@@ -9,7 +9,7 @@
         <variant ordercode="ATtiny4313-MU" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
         <variant ordercode="ATtiny4313-MUR" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
     </variants>
-    <device name="ATtiny4313" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny4313" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
index 0fb9c7c2..13c9c3e0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY43U.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATtiny43U-SU" package="SOIC20" pinout="SOIC20" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny43U-MU" package="WQFN20" pinout="QFN20" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny43U" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny43U" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
index 704bd98f..0921bd09 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATtiny44-20SSU" package="SOIC14" pinout="SOIC_14" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny44-20MU" package="WQFN20" pinout="QFN_20" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny44" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny44" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
index f078a15a..f91c9375 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY441.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATtiny441-MMH" package="VQFN20" pinout="QFN_20" speedmax="16000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.7"/>
     </variants>
-    <device name="ATtiny441" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny441" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
index 75401361..84c09e72 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY44A.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATtiny44A-SSF" package="SOIC14" pinout="SOIC_14" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device name="ATtiny44A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny44A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY45.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY45.xml
index 155a2820..485f36bc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY45.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY45.xml
@@ -22,7 +22,7 @@
         <variant ordercode="ATtiny45V-20MU" package="MLF20" pinout="QFN_20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny45" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny45" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
index f1d7bfaf..32310a26 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny461-20SU" package="SOIC20" pinout="SOIC_20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny461" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny461" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
index 0a19c819..0a9e90f5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY461A.xml
@@ -9,7 +9,7 @@
         <variant ordercode="ATtiny461A-MUR" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
         <variant ordercode="ATtiny461A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
     </variants>
-    <device name="ATtiny461A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny461A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
index 6abd1e92..3c5c19d5 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY48.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny48-MU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5"
                  package="QFN32" pinout="TQFP_QFN_32"/>
     </variants>
-    <device name="ATtiny48" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny48" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x1000">
                 <memory-segment start="0x0000" size="0x1000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY804.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY804.xml
index a7bc19c1..4cc3da35 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY804.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY804.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny804-SSNR" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny804" family="AVR8">
+    <device name="ATtiny804" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY806.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY806.xml
index a64c8a0f..6703a2bd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY806.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY806.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATtiny806-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny806" family="AVR8">
+    <device name="ATtiny806" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY807.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY807.xml
index d6b4f616..de3152d8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY807.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY807.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATtiny807-MRF" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny807" family="AVR8">
+    <device name="ATtiny807" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY814.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY814.xml
index a6275661..97198ff0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY814.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY814.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATtiny814-SSNRES" package="SOIC14" pinout="SOIC14" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny814" family="AVR8">
+    <device name="ATtiny814" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY816.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY816.xml
index b340da2a..b5384c88 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY816.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY816.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATtiny816-SNR" package="SOIC20" pinout="SOIC20" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny816" family="AVR8">
+    <device name="ATtiny816" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY817.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY817.xml
index 3af55977..7affbd44 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY817.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY817.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATtiny817-MNRES" package="VQFN24" pinout="QFN24" speedmax="20000000" tempmax="105"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device architecture="AVR8X" avr-family="AVR TINY" name="ATtiny817" family="AVR8">
+    <device name="ATtiny817" family="AVR8" architecture="AVR8X" avr-family="AVR TINY">
         <address-spaces>
             <address-space endianness="little" id="data" name="data" size="0xA000" start="0x0000">
                 <memory-segment exec="0" name="EEPROM" pagesize="0x20" rw="RW" size="0x0080" start="0x00001400"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
index 161d5c3d..1eee9fbf 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY828.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATtiny828-MU" package="VQFN32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny828-AU" package="TQFP32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny828" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny828" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
index e50593bd..6be68b84 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84.xml
@@ -5,7 +5,7 @@
         <variant ordercode="ATtiny84V-10SSU" package="SOIC14" pinout="SOIC_14" tempmax="85" tempmin="-40"/>
         <variant ordercode="ATtiny84-20MU" package="QFN20" pinout="QFN_20" tempmax="85" tempmin="-40"/>
     </variants>
-    <device name="ATtiny84" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny84" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
index cfd4fea1..3b0a014f 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY841.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATtiny841-MMH" package="VQFN20" pinout="QFN_20" speedmax="16000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="1.7"/>
     </variants>
-    <device name="ATtiny841" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny841" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
index b10e9f97..4195e2f2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY84A.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny84A-SSF" package="SOIC14" pinout="SOIC_14" speedmax="20000000" tempmax="125"
                  tempmin="-40" vccmax="5.5" vccmin="1.8"/>
     </variants>
-    <device name="ATtiny84A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny84A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
index ec8ee8bd..597f566d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY85.xml
@@ -18,7 +18,7 @@
         <variant ordercode="ATtiny85V-20MU" package="MLF20" pinout="QFN_20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny85" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny85" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
index 46c1d7a7..371402ff 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny861-20SU" package="SOIC20" pinout="SOIC_20" speedmax="20000000" tempmax="85"
                  tempmin="-40" vccmax="5.5" vccmin="2.7"/>
     </variants>
-    <device name="ATtiny861" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny861" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
index d84feffc..977bcaf0 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY861A.xml
@@ -9,7 +9,7 @@
         <variant ordercode="ATtiny861A-MUR" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
         <variant ordercode="ATtiny861A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
     </variants>
-    <device name="ATtiny861A" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny861A" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
index e4165c48..07ddc04e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY87.xml
@@ -4,7 +4,7 @@
         <variant ordercode="ATtiny87-SU" tempmin="-40" tempmax="85" pinout="SOIC20" package="SOIC20"/>
         <variant ordercode="ATtiny87-MU" tempmin="-40" tempmax="85" pinout="VQFN32" package="VQFN32"/>
     </variants>
-    <device name="ATtiny87" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny87" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
index 4fa2f3ab..5fd82579 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/TINY/ATTINY88.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATtiny88-MU" speedmax="12000000" tempmin="-40" tempmax="85" vccmin="1.8" vccmax="5.5"
                  package="QFN32" pinout="TQFP_QFN_32"/>
     </variants>
-    <device name="ATtiny88" architecture="AVR8" avr-family="tinyAVR" family="AVR8">
+    <device name="ATtiny88" family="AVR8" architecture="AVR8" avr-family="tinyAVR">
         <address-spaces>
             <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
                 <memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
index 1394cbed..aa05532a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA128A1-CU" package="CBGA100" pinout="BGA100" speedmax="32000000" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128A1" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128A1" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x22000" endianness="little">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
@@ -21,8 +21,8 @@
                 <memory-segment start="0x1000" size="0x000800" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
                 <memory-segment start="0x2000" size="0x002000" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
                 <!-- We don't support external SRAM (for now) -->
-<!--                <memory-segment start="0x4000" size="0xFFBFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
-<!--                                external="true"/>-->
+                <!--                <memory-segment start="0x4000" size="0xFFBFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
+                <!--                                external="true"/>-->
             </address-space>
             <address-space name="eeprom" id="eeprom" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="eeprom" rw="RW" exec="0" name="EEPROM"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
index f4cee9d9..ffb117f1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A1U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega128A1U-AN" package="TQFP100" pinout="TQFP100" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128A1U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128A1U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
@@ -25,8 +25,8 @@
                 <memory-segment start="0x1000" size="0x000800" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
                 <memory-segment start="0x2000" size="0x002000" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
                 <!-- We don't support external SRAM (for now) -->
-<!--                <memory-segment start="0x4000" size="0xFFBFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
-<!--                                external="true"/>-->
+                <!--                <memory-segment start="0x4000" size="0xFFBFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
+                <!--                                external="true"/>-->
             </address-space>
             <address-space name="eeprom" id="eeprom" start="0x00000" size="0x0800">
                 <memory-segment start="0x00000" size="0x0800" type="eeprom" rw="RW" exec="0" name="EEPROM"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
index 8409f8ba..08d0cf00 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA128A3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128A3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128A3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x22000" endianness="little">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
index 999f398e..daba68c9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A3U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega128A3U-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128A3U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128A3U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
index e2d6a29d..7e1efd0e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128A4U.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega128A4U-M7" package="VQFN44PW" pinout="QFP_QFN_44" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128A4U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128A4U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
index 67c77e38..9d780f66 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B1.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATxmega128B1-AN" package="TQFP100" pinout="QFP_100" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128B1" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128B1" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
index f45fd491..575389d1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128B3.xml
@@ -8,7 +8,7 @@
         <variant ordercode="ATxmega128B3-MCU" package="DRQFN64" pinout="DRQFN_64" speedmax="32000000" tempmax="85"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128B3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128B3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
index 3e98978d..68661550 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128C3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega128C3-M7" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
index d10b3dd0..a4ae106c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega128D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x22000" endianness="little">
                 <memory-segment start="0x0000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
index d244e445..a49c0a3c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA128D4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega128D4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega128D4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega128D4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x22000" endianness="little">
                 <memory-segment start="0x00000" size="0x20000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
index 5d6705a1..bcd29a3e 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA16A4-MH" package="VQFN44" speedmax="32000000" pinout="QFP_QFN_44" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega16A4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega16A4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x5000" endianness="little">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
index e57816da..1eb44091 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16A4U.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega16A4U-M7" package="VQFN44" pinout="QFP_QFN_44" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega16A4U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega16A4U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x5000" endianness="little">
                 <memory-segment start="0x00000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
index 224fab43..5371664a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16C4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega16C4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega16C4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega16C4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x5000" endianness="little">
                 <memory-segment start="0x00000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
index fb6c074f..8e36a4a6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16D4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega16D4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega16D4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega16D4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x5000" endianness="little">
                 <memory-segment start="0x0000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
index 94e6c684..a48d1dd2 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA16E5.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATxmega16E5-M4N" package="UQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega16E5" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega16E5" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x5000" endianness="little">
                 <memory-segment start="0x00000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
index 380db9d2..0fff17cc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA192A3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega192A3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega192A3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x32000" endianness="little">
                 <memory-segment start="0x0000" size="0x30000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
index a2ec5838..e1c27bcc 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192A3U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega192A3U-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega192A3U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega192A3U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x32000" endianness="little">
                 <memory-segment start="0x00000" size="0x30000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
index 90aaaf74..645f6b48 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192C3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA192C3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega192C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega192C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x32000" endianness="little">
                 <memory-segment start="0x00000" size="0x30000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
index 87d3826a..950258c9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA192D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega192D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega192D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega192D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x32000" endianness="little">
                 <memory-segment start="0x0000" size="0x30000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
index a00134c0..222bf9e1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA256A3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256A3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256A3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x42000" endianness="little">
                 <memory-segment start="0x00000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
index 03868579..859b7156 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3B.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA256A3B-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256A3B" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256A3B" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x42000" endianness="little">
                 <memory-segment start="0x00000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
index 2e2c7d3a..b50ca7d1 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3BU.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATxmega256A3BU-MH" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="85"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256A3BU" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256A3BU" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x42000" endianness="little">
                 <memory-segment start="0x00000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
index d37ae6b8..bfec639d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256A3U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega256A3U-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256A3U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256A3U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x42000" endianness="little">
                 <memory-segment start="0x00000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
index 28c2acde..7db6de68 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256C3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega256C3-M7" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x42000" endianness="little">
                 <memory-segment start="0x00000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
index 45b0d47a..f8c15807 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA256D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega256D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega256D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega256D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x42000" endianness="little">
                 <memory-segment start="0x0000" size="0x40000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
index e4165a99..5e3f899b 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA32A4-MH" package="VQFN44" speedmax="32000000" pinout="QFP_QFN_44" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32A4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32A4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x9000" endianness="little">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
index 0a5a0628..21d43150 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32A4U.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega32A4U-M7" package="VQFN44" pinout="QFP_QFN_44" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32A4U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32A4U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x9000" endianness="little">
                 <memory-segment start="0x00000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
index 4fda5be3..e414e53d 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega32C3-M7" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x9000" endianness="little">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
index 62b8006f..487e9892 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32C4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega32C4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32C4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32C4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x9000" endianness="little">
                 <memory-segment start="0x00000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
index 2c4d8669..706dd0fd 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega32D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x9000" endianness="little">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
index 8db69379..460ab9be 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32D4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega32D4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32D4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32D4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x9000" endianness="little">
                 <memory-segment start="0x0000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
index 354bb55f..0f7d00e8 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA32E5.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATxmega32E5-M4N" package="UQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega32E5" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega32E5" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x9000" endianness="little">
                 <memory-segment start="0x00000" size="0x8000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
index 8f6d1b56..30a68ade 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384C3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega384C3-M7" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega384C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega384C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x62000" endianness="little">
                 <memory-segment start="0x00000" size="0x60000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
index d3a03e02..38b6f7bf 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA384D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega384D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega384D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega384D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x62000" endianness="little">
                 <memory-segment start="0x00000" size="0x60000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
index 8c76535e..0f7baeb9 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA64A1-CU" package="CBGA100" pinout="BGA100" speedmax="32000000" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64A1" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64A1" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x11000" endianness="little">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
@@ -21,8 +21,8 @@
                 <memory-segment start="0x1000" size="0x000800" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
                 <memory-segment start="0x2000" size="0x001000" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
                 <!-- We don't support external SRAM (for now) -->
-<!--                <memory-segment start="0x3000" size="0xFFCFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
-<!--                                external="true"/>-->
+                <!--                <memory-segment start="0x3000" size="0xFFCFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
+                <!--                                external="true"/>-->
             </address-space>
             <address-space name="eeprom" id="eeprom" start="0x0000" size="0x0800">
                 <memory-segment start="0x0000" size="0x0800" type="eeprom" rw="RW" exec="0" name="EEPROM"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
index 4aa06787..0ad76f84 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A1U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega64A1U-AN" package="TQFP100" pinout="TQFP100" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64A1U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64A1U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
@@ -25,8 +25,8 @@
                 <memory-segment start="0x1000" size="0x000800" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
                 <memory-segment start="0x2000" size="0x001000" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
                 <!-- We don't support external SRAM (for now) -->
-<!--                <memory-segment start="0x3000" size="0xFFCFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
-<!--                                external="true"/>-->
+                <!--                <memory-segment start="0x3000" size="0xFFCFFF" type="ram" rw="RW" exec="0" name="EXTERNAL_SRAM"-->
+                <!--                                external="true"/>-->
             </address-space>
             <address-space name="eeprom" id="eeprom" start="0x00000" size="0x0800">
                 <memory-segment start="0x00000" size="0x0800" type="eeprom" rw="RW" exec="0" name="EEPROM"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
index a09538e9..4eb976da 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATXMEGA64A3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0"
                  tempmin="0" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64A3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64A3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x11000" endianness="little">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
index 2a2950e7..aacb1c1a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A3U.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega64A3U-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64A3U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64A3U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
index 46763234..b59c0fc7 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64A4U.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega64A4U-M7" package="VQFN44PW" pinout="QFP_QFN_44" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64A4U" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64A4U" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
index bbe701c5..b65e0842 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B1.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATxmega64B1-CU" package="VFBGA100" pinout="BGA_100" speedmax="32000000" tempmax="85"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64B1" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64B1" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
index 337b1c51..0251c16c 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64B3.xml
@@ -6,7 +6,7 @@
         <variant ordercode="ATxmega64B3-MH" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="85"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64B3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64B3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
index 66f36fe6..5ba4cff6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64C3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega64C3-M7" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64C3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
index c4633c71..6344508a 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D3.xml
@@ -10,7 +10,7 @@
         <variant ordercode="ATxmega64D3-MN" package="QFN64" pinout="QFP_QFN_64" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64D3" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64D3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x0000" size="0x11000" endianness="little">
                 <memory-segment start="0x0000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
index f328d387..ef817ce6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA64D4.xml
@@ -12,7 +12,7 @@
         <variant ordercode="ATxmega64D4-M7" package="VFBGA49" pinout="BGA_49" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega64D4" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega64D4" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x11000" endianness="little">
                 <memory-segment start="0x00000" size="0x10000" type="flash" rw="RW" exec="1" name="APP_SECTION"
diff --git a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
index a29e9603..946ad8c6 100644
--- a/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
+++ b/src/Targets/TargetDescriptionFiles/AVR8/XMEGA/ATXMEGA8E5.xml
@@ -14,7 +14,7 @@
         <variant ordercode="ATxmega8E5-M4N" package="UQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
                  tempmin="-40" vccmax="3.6" vccmin="1.6"/>
     </variants>
-    <device name="ATxmega8E5" architecture="AVR8_XMEGA" avr-family="AVR XMEGA" family="AVR8">
+    <device name="ATxmega8E5" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
         <address-spaces>
             <address-space name="prog" id="prog" start="0x00000" size="0x2800" endianness="little">
                 <memory-segment start="0x00000" size="0x2000" type="flash" rw="RW" exec="1" name="APP_SECTION"