Started correcting issues with TDFs found by the TDF validation script
This commit is contained in:
@@ -1,7 +1,13 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<target-description-file>
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<target-description-file>
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<variants>
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<variants>
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<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.8" vccmax="5.5"/>
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<variant ordercode="ATtiny2313A-SUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="SOIC20"/>
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<variant ordercode="ATtiny2313A-SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="SOIC20"/>
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<variant ordercode="ATtiny2313A-PU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="PDIP20"/>
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<variant ordercode="ATtiny2313A-MUR" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
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<variant ordercode="ATtiny2313A-MU" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
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<variant ordercode="ATtiny2313A-MMHR" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
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<variant ordercode="ATtiny2313A-MMH" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
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</variants>
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</variants>
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<device name="ATtiny2313A" architecture="AVR8" family="tinyAVR">
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<device name="ATtiny2313A" architecture="AVR8" family="tinyAVR">
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<address-spaces>
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<address-spaces>
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@@ -37,14 +43,38 @@
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<instance name="PORTB" caption="I/O Port">
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<instance name="PORTB" caption="I/O Port">
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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caption="I/O Port"/>
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caption="I/O Port"/>
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<signals>
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<signal group="P" function="default" pad="PB0" index="0"/>
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<signal group="P" function="default" pad="PB1" index="1"/>
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<signal group="P" function="default" pad="PB2" index="2"/>
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<signal group="P" function="default" pad="PB3" index="3"/>
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<signal group="P" function="default" pad="PB4" index="4"/>
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<signal group="P" function="default" pad="PB5" index="5"/>
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<signal group="P" function="default" pad="PB6" index="6"/>
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<signal group="P" function="default" pad="PB7" index="7"/>
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</signals>
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</instance>
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</instance>
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<instance name="PORTD" caption="I/O Port">
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<instance name="PORTD" caption="I/O Port">
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<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
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<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
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caption="I/O Port"/>
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caption="I/O Port"/>
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<signals>
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<signal group="P" function="default" pad="PD0" index="0"/>
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<signal group="P" function="default" pad="PD1" index="1"/>
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<signal group="P" function="default" pad="PD2" index="2"/>
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<signal group="P" function="default" pad="PD3" index="3"/>
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<signal group="P" function="default" pad="PD4" index="4"/>
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<signal group="P" function="default" pad="PD5" index="5"/>
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<signal group="P" function="default" pad="PD6" index="6"/>
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</signals>
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</instance>
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</instance>
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<instance name="PORTA" caption="I/O Port">
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<instance name="PORTA" caption="I/O Port">
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<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
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<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
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caption="I/O Port"/>
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caption="I/O Port"/>
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<signals>
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<signal group="P" function="default" pad="PA0" index="0"/>
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<signal group="P" function="default" pad="PA1" index="1"/>
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<signal group="P" function="default" pad="PA2" index="2"/>
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</signals>
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</instance>
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</instance>
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</module>
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</module>
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<module name="TC8">
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<module name="TC8">
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@@ -800,4 +830,50 @@
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</value-group>
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</value-group>
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</module>
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</module>
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</modules>
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</modules>
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<pinouts>
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<pinout name="PDIP_SOIC_20">
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<pin position="1" pad="PA2"/>
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<pin position="2" pad="PD0"/>
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<pin position="3" pad="PD1"/>
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<pin position="4" pad="PA1"/>
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<pin position="5" pad="PA0"/>
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<pin position="6" pad="PD2"/>
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<pin position="7" pad="PD3"/>
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<pin position="8" pad="PD4"/>
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<pin position="9" pad="PD5"/>
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<pin position="10" pad="GND"/>
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<pin position="11" pad="PD6"/>
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<pin position="12" pad="PB0"/>
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<pin position="13" pad="PB1"/>
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<pin position="14" pad="PB2"/>
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<pin position="15" pad="PB3"/>
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<pin position="16" pad="PB4"/>
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<pin position="17" pad="PB5"/>
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<pin position="18" pad="PB6"/>
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<pin position="19" pad="PB7"/>
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<pin position="20" pad="VCC"/>
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</pinout>
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<pinout name="QFN20">
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<pin position="1" pad="PD1"/>
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<pin position="2" pad="PA1"/>
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<pin position="3" pad="PA0"/>
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<pin position="4" pad="PD2"/>
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<pin position="5" pad="PD3"/>
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<pin position="6" pad="PD4"/>
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<pin position="7" pad="PD5"/>
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<pin position="8" pad="GND"/>
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<pin position="9" pad="PD6"/>
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<pin position="10" pad="PB0"/>
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<pin position="11" pad="PB1"/>
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<pin position="12" pad="PB2"/>
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<pin position="13" pad="PB3"/>
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<pin position="14" pad="PB4"/>
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<pin position="15" pad="PB5"/>
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<pin position="16" pad="PB6"/>
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<pin position="17" pad="PB7"/>
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<pin position="18" pad="VCC"/>
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<pin position="19" pad="PA2"/>
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<pin position="20" pad="PD0"/>
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</pinout>
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</pinouts>
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</target-description-file>
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</target-description-file>
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@@ -1,7 +1,17 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<target-description-file>
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<target-description-file>
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<variants>
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<variants>
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<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.8" vccmax="5.5"/>
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<variant ordercode="ATtiny261A-PU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="PDIP20"/>
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<variant ordercode="ATtiny261A-SUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
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<variant ordercode="ATtiny261A-SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
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<variant ordercode="ATtiny261A-XU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
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<variant ordercode="ATtiny261A-XUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
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<variant ordercode="ATtiny261A-MN" tempmin="-40" tempmax="105" pinout="QFN32" package="VQFN32"/>
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<variant ordercode="ATtiny261A-MNR" tempmin="-40" tempmax="105" pinout="QFN32" package="VQFN32"/>
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<variant ordercode="ATtiny261A-MUR" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
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<variant ordercode="ATtiny261A-MF" tempmin="-40" tempmax="125" pinout="QFN32" package="VQFN32"/>
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<variant ordercode="ATtiny261A-MFR" tempmin="-40" tempmax="125" pinout="QFN32" package="VQFN32"/>
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<variant ordercode="ATtiny261A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
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</variants>
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</variants>
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<device name="ATtiny261A" architecture="AVR8" family="tinyAVR">
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<device name="ATtiny261A" architecture="AVR8" family="tinyAVR">
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<address-spaces>
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<address-spaces>
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@@ -37,10 +47,30 @@
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<instance name="PORTA" caption="I/O Port">
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<instance name="PORTA" caption="I/O Port">
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<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
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<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
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caption="I/O Port"/>
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caption="I/O Port"/>
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<signals>
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<signal group="P" function="default" pad="PA0" index="0"/>
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<signal group="P" function="default" pad="PA1" index="1"/>
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<signal group="P" function="default" pad="PA2" index="2"/>
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<signal group="P" function="default" pad="PA3" index="3"/>
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<signal group="P" function="default" pad="PA4" index="4"/>
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<signal group="P" function="default" pad="PA5" index="5"/>
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<signal group="P" function="default" pad="PA6" index="6"/>
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<signal group="P" function="default" pad="PA7" index="7"/>
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</signals>
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</instance>
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</instance>
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<instance name="PORTB" caption="I/O Port">
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<instance name="PORTB" caption="I/O Port">
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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caption="I/O Port"/>
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caption="I/O Port"/>
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<signals>
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<signal group="P" function="default" pad="PB0" index="0"/>
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<signal group="P" function="default" pad="PB1" index="1"/>
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<signal group="P" function="default" pad="PB2" index="2"/>
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<signal group="P" function="default" pad="PB3" index="3"/>
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<signal group="P" function="default" pad="PB4" index="4"/>
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<signal group="P" function="default" pad="PB5" index="5"/>
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<signal group="P" function="default" pad="PB6" index="6"/>
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<signal group="P" function="default" pad="PB7" index="7"/>
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</signals>
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</instance>
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</instance>
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</module>
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</module>
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<module name="ADC">
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<module name="ADC">
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@@ -884,4 +914,62 @@
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</value-group>
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</value-group>
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</module>
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</module>
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</modules>
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</modules>
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<pinouts>
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<pinout name="PDIP_SOIC_TSSOP_20">
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<pin position="1" pad="PB0"/>
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<pin position="2" pad="PB1"/>
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<pin position="3" pad="PB2"/>
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<pin position="4" pad="PB3"/>
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<pin position="5" pad="VCC"/>
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<pin position="6" pad="GND"/>
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<pin position="7" pad="PB4"/>
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<pin position="8" pad="PB5"/>
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<pin position="9" pad="PB6"/>
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<pin position="10" pad="PB7"/>
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<pin position="11" pad="PA7"/>
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<pin position="12" pad="PA6"/>
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<pin position="13" pad="PA5"/>
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<pin position="14" pad="PA4"/>
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<pin position="15" pad="AVCC"/>
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<pin position="16" pad="AGND"/>
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<pin position="17" pad="PA3"/>
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<pin position="18" pad="PA2"/>
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<pin position="19" pad="PA1"/>
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<pin position="20" pad="VA0"/>
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</pinout>
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<pinout name="QFN32">
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<pin position="1" pad="NC"/>
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<pin position="2" pad="PB3"/>
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<pin position="3" pad="NC"/>
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<pin position="4" pad="VCC"/>
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<pin position="5" pad="GND"/>
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<pin position="6" pad="NC"/>
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<pin position="7" pad="PB4"/>
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<pin position="8" pad="PB5"/>
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<pin position="9" pad="NC"/>
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<pin position="10" pad="PB6"/>
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<pin position="11" pad="PB7"/>
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<pin position="12" pad="NC"/>
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<pin position="13" pad="PA7"/>
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<pin position="14" pad="PA6"/>
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<pin position="15" pad="PA5"/>
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<pin position="16" pad="NC"/>
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<pin position="17" pad="PA4"/>
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<pin position="18" pad="AVCC"/>
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<pin position="19" pad="NC"/>
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<pin position="20" pad="NC"/>
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<pin position="21" pad="AGND"/>
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<pin position="22" pad="PA3"/>
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<pin position="23" pad="PA2"/>
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<pin position="24" pad="NC"/>
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<pin position="25" pad="PA1"/>
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<pin position="26" pad="PA0"/>
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<pin position="27" pad="NC"/>
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<pin position="28" pad="NC"/>
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<pin position="29" pad="NC"/>
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<pin position="30" pad="PB0"/>
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<pin position="31" pad="PB1"/>
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<pin position="32" pad="PB2"/>
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|
</pinout>
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</pinouts>
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||||||
</target-description-file>
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</target-description-file>
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@@ -1,7 +1,13 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<target-description-file>
|
<target-description-file>
|
||||||
<variants>
|
<variants>
|
||||||
<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.8" vccmax="5.5"/>
|
<variant ordercode="ATtiny4313-PU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="PDIP20"/>
|
||||||
|
<variant ordercode="ATtiny4313-SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny4313-SUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny4313-MMH" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
|
||||||
|
<variant ordercode="ATtiny4313-MMHR" tempmin="-40" tempmax="85" pinout="QFN20" package="VQFN20"/>
|
||||||
|
<variant ordercode="ATtiny4313-MU" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
|
||||||
|
<variant ordercode="ATtiny4313-MUR" tempmin="-40" tempmax="85" pinout="QFN20" package="WQFN20"/>
|
||||||
</variants>
|
</variants>
|
||||||
<device name="ATtiny4313" architecture="AVR8" family="tinyAVR">
|
<device name="ATtiny4313" architecture="AVR8" family="tinyAVR">
|
||||||
<address-spaces>
|
<address-spaces>
|
||||||
@@ -37,14 +43,38 @@
|
|||||||
<instance name="PORTB" caption="I/O Port">
|
<instance name="PORTB" caption="I/O Port">
|
||||||
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PB0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PB1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PB2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PB3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PB4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PB5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PB6" index="6"/>
|
||||||
|
<signal group="P" function="default" pad="PB7" index="7"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
<instance name="PORTD" caption="I/O Port">
|
<instance name="PORTD" caption="I/O Port">
|
||||||
<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
|
<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PD0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PD1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PD2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PD3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PD4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PD5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PD6" index="6"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
<instance name="PORTA" caption="I/O Port">
|
<instance name="PORTA" caption="I/O Port">
|
||||||
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PA0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PA1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PA2" index="2"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
</module>
|
</module>
|
||||||
<module name="TC8">
|
<module name="TC8">
|
||||||
@@ -800,4 +830,50 @@
|
|||||||
</value-group>
|
</value-group>
|
||||||
</module>
|
</module>
|
||||||
</modules>
|
</modules>
|
||||||
|
<pinouts>
|
||||||
|
<pinout name="PDIP_SOIC_20">
|
||||||
|
<pin position="1" pad="PA2"/>
|
||||||
|
<pin position="2" pad="PD0"/>
|
||||||
|
<pin position="3" pad="PD1"/>
|
||||||
|
<pin position="4" pad="PA1"/>
|
||||||
|
<pin position="5" pad="PA0"/>
|
||||||
|
<pin position="6" pad="PD2"/>
|
||||||
|
<pin position="7" pad="PD3"/>
|
||||||
|
<pin position="8" pad="PD4"/>
|
||||||
|
<pin position="9" pad="PD5"/>
|
||||||
|
<pin position="10" pad="GND"/>
|
||||||
|
<pin position="11" pad="PD6"/>
|
||||||
|
<pin position="12" pad="PB0"/>
|
||||||
|
<pin position="13" pad="PB1"/>
|
||||||
|
<pin position="14" pad="PB2"/>
|
||||||
|
<pin position="15" pad="PB3"/>
|
||||||
|
<pin position="16" pad="PB4"/>
|
||||||
|
<pin position="17" pad="PB5"/>
|
||||||
|
<pin position="18" pad="PB6"/>
|
||||||
|
<pin position="19" pad="PB7"/>
|
||||||
|
<pin position="20" pad="VCC"/>
|
||||||
|
</pinout>
|
||||||
|
<pinout name="QFN20">
|
||||||
|
<pin position="1" pad="PD1"/>
|
||||||
|
<pin position="2" pad="PA1"/>
|
||||||
|
<pin position="3" pad="PA0"/>
|
||||||
|
<pin position="4" pad="PD2"/>
|
||||||
|
<pin position="5" pad="PD3"/>
|
||||||
|
<pin position="6" pad="PD4"/>
|
||||||
|
<pin position="7" pad="PD5"/>
|
||||||
|
<pin position="8" pad="GND"/>
|
||||||
|
<pin position="9" pad="PD6"/>
|
||||||
|
<pin position="10" pad="PB0"/>
|
||||||
|
<pin position="11" pad="PB1"/>
|
||||||
|
<pin position="12" pad="PB2"/>
|
||||||
|
<pin position="13" pad="PB3"/>
|
||||||
|
<pin position="14" pad="PB4"/>
|
||||||
|
<pin position="15" pad="PB5"/>
|
||||||
|
<pin position="16" pad="PB6"/>
|
||||||
|
<pin position="17" pad="PB7"/>
|
||||||
|
<pin position="18" pad="VCC"/>
|
||||||
|
<pin position="19" pad="PA2"/>
|
||||||
|
<pin position="20" pad="PD0"/>
|
||||||
|
</pinout>
|
||||||
|
</pinouts>
|
||||||
</target-description-file>
|
</target-description-file>
|
||||||
|
|||||||
@@ -1,7 +1,13 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<target-description-file>
|
<target-description-file>
|
||||||
<variants>
|
<variants>
|
||||||
<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.8" vccmax="5.5"/>
|
<variant ordercode="ATtiny461A-PU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="PDIP20"/>
|
||||||
|
<variant ordercode="ATtiny461A-SUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny461A-SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny461A-XU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
|
||||||
|
<variant ordercode="ATtiny461A-XUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
|
||||||
|
<variant ordercode="ATtiny461A-MUR" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
|
||||||
|
<variant ordercode="ATtiny461A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
|
||||||
</variants>
|
</variants>
|
||||||
<device name="ATtiny461A" architecture="AVR8" family="tinyAVR">
|
<device name="ATtiny461A" architecture="AVR8" family="tinyAVR">
|
||||||
<address-spaces>
|
<address-spaces>
|
||||||
@@ -37,10 +43,30 @@
|
|||||||
<instance name="PORTA" caption="I/O Port">
|
<instance name="PORTA" caption="I/O Port">
|
||||||
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PA0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PA1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PA2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PA3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PA4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PA5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PA6" index="6"/>
|
||||||
|
<signal group="P" function="default" pad="PA7" index="7"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
<instance name="PORTB" caption="I/O Port">
|
<instance name="PORTB" caption="I/O Port">
|
||||||
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PB0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PB1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PB2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PB3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PB4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PB5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PB6" index="6"/>
|
||||||
|
<signal group="P" function="default" pad="PB7" index="7"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
</module>
|
</module>
|
||||||
<module name="ADC">
|
<module name="ADC">
|
||||||
@@ -884,4 +910,62 @@
|
|||||||
</value-group>
|
</value-group>
|
||||||
</module>
|
</module>
|
||||||
</modules>
|
</modules>
|
||||||
|
<pinouts>
|
||||||
|
<pinout name="PDIP_SOIC_TSSOP_20">
|
||||||
|
<pin position="1" pad="PB0"/>
|
||||||
|
<pin position="2" pad="PB1"/>
|
||||||
|
<pin position="3" pad="PB2"/>
|
||||||
|
<pin position="4" pad="PB3"/>
|
||||||
|
<pin position="5" pad="VCC"/>
|
||||||
|
<pin position="6" pad="GND"/>
|
||||||
|
<pin position="7" pad="PB4"/>
|
||||||
|
<pin position="8" pad="PB5"/>
|
||||||
|
<pin position="9" pad="PB6"/>
|
||||||
|
<pin position="10" pad="PB7"/>
|
||||||
|
<pin position="11" pad="PA7"/>
|
||||||
|
<pin position="12" pad="PA6"/>
|
||||||
|
<pin position="13" pad="PA5"/>
|
||||||
|
<pin position="14" pad="PA4"/>
|
||||||
|
<pin position="15" pad="AVCC"/>
|
||||||
|
<pin position="16" pad="AGND"/>
|
||||||
|
<pin position="17" pad="PA3"/>
|
||||||
|
<pin position="18" pad="PA2"/>
|
||||||
|
<pin position="19" pad="PA1"/>
|
||||||
|
<pin position="20" pad="VA0"/>
|
||||||
|
</pinout>
|
||||||
|
<pinout name="QFN32">
|
||||||
|
<pin position="1" pad="NC"/>
|
||||||
|
<pin position="2" pad="PB3"/>
|
||||||
|
<pin position="3" pad="NC"/>
|
||||||
|
<pin position="4" pad="VCC"/>
|
||||||
|
<pin position="5" pad="GND"/>
|
||||||
|
<pin position="6" pad="NC"/>
|
||||||
|
<pin position="7" pad="PB4"/>
|
||||||
|
<pin position="8" pad="PB5"/>
|
||||||
|
<pin position="9" pad="NC"/>
|
||||||
|
<pin position="10" pad="PB6"/>
|
||||||
|
<pin position="11" pad="PB7"/>
|
||||||
|
<pin position="12" pad="NC"/>
|
||||||
|
<pin position="13" pad="PA7"/>
|
||||||
|
<pin position="14" pad="PA6"/>
|
||||||
|
<pin position="15" pad="PA5"/>
|
||||||
|
<pin position="16" pad="NC"/>
|
||||||
|
<pin position="17" pad="PA4"/>
|
||||||
|
<pin position="18" pad="AVCC"/>
|
||||||
|
<pin position="19" pad="NC"/>
|
||||||
|
<pin position="20" pad="NC"/>
|
||||||
|
<pin position="21" pad="AGND"/>
|
||||||
|
<pin position="22" pad="PA3"/>
|
||||||
|
<pin position="23" pad="PA2"/>
|
||||||
|
<pin position="24" pad="NC"/>
|
||||||
|
<pin position="25" pad="PA1"/>
|
||||||
|
<pin position="26" pad="PA0"/>
|
||||||
|
<pin position="27" pad="NC"/>
|
||||||
|
<pin position="28" pad="NC"/>
|
||||||
|
<pin position="29" pad="NC"/>
|
||||||
|
<pin position="30" pad="PB0"/>
|
||||||
|
<pin position="31" pad="PB1"/>
|
||||||
|
<pin position="32" pad="PB2"/>
|
||||||
|
</pinout>
|
||||||
|
</pinouts>
|
||||||
</target-description-file>
|
</target-description-file>
|
||||||
|
|||||||
@@ -1,7 +1,13 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<target-description-file>
|
<target-description-file>
|
||||||
<variants>
|
<variants>
|
||||||
<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.8" vccmax="5.5"/>
|
<variant ordercode="ATtiny861A-PU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="PDIP20"/>
|
||||||
|
<variant ordercode="ATtiny861A-SUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny861A-SU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="SOIC20"/>
|
||||||
|
<variant ordercode="ATtiny861A-XU" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
|
||||||
|
<variant ordercode="ATtiny861A-XUR" tempmin="-40" tempmax="85" pinout="PDIP_SOIC_TSSOP_20" package="TSSOP20"/>
|
||||||
|
<variant ordercode="ATtiny861A-MUR" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
|
||||||
|
<variant ordercode="ATtiny861A-MU" tempmin="-40" tempmax="85" pinout="QFN32" package="VQFN32"/>
|
||||||
</variants>
|
</variants>
|
||||||
<device name="ATtiny861A" architecture="AVR8" family="tinyAVR">
|
<device name="ATtiny861A" architecture="AVR8" family="tinyAVR">
|
||||||
<address-spaces>
|
<address-spaces>
|
||||||
@@ -37,10 +43,30 @@
|
|||||||
<instance name="PORTA" caption="I/O Port">
|
<instance name="PORTA" caption="I/O Port">
|
||||||
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PA0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PA1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PA2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PA3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PA4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PA5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PA6" index="6"/>
|
||||||
|
<signal group="P" function="default" pad="PA7" index="7"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
<instance name="PORTB" caption="I/O Port">
|
<instance name="PORTB" caption="I/O Port">
|
||||||
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
|
||||||
caption="I/O Port"/>
|
caption="I/O Port"/>
|
||||||
|
<signals>
|
||||||
|
<signal group="P" function="default" pad="PB0" index="0"/>
|
||||||
|
<signal group="P" function="default" pad="PB1" index="1"/>
|
||||||
|
<signal group="P" function="default" pad="PB2" index="2"/>
|
||||||
|
<signal group="P" function="default" pad="PB3" index="3"/>
|
||||||
|
<signal group="P" function="default" pad="PB4" index="4"/>
|
||||||
|
<signal group="P" function="default" pad="PB5" index="5"/>
|
||||||
|
<signal group="P" function="default" pad="PB6" index="6"/>
|
||||||
|
<signal group="P" function="default" pad="PB7" index="7"/>
|
||||||
|
</signals>
|
||||||
</instance>
|
</instance>
|
||||||
</module>
|
</module>
|
||||||
<module name="ADC">
|
<module name="ADC">
|
||||||
@@ -888,4 +914,62 @@
|
|||||||
</value-group>
|
</value-group>
|
||||||
</module>
|
</module>
|
||||||
</modules>
|
</modules>
|
||||||
|
<pinouts>
|
||||||
|
<pinout name="PDIP_SOIC_TSSOP_20">
|
||||||
|
<pin position="1" pad="PB0"/>
|
||||||
|
<pin position="2" pad="PB1"/>
|
||||||
|
<pin position="3" pad="PB2"/>
|
||||||
|
<pin position="4" pad="PB3"/>
|
||||||
|
<pin position="5" pad="VCC"/>
|
||||||
|
<pin position="6" pad="GND"/>
|
||||||
|
<pin position="7" pad="PB4"/>
|
||||||
|
<pin position="8" pad="PB5"/>
|
||||||
|
<pin position="9" pad="PB6"/>
|
||||||
|
<pin position="10" pad="PB7"/>
|
||||||
|
<pin position="11" pad="PA7"/>
|
||||||
|
<pin position="12" pad="PA6"/>
|
||||||
|
<pin position="13" pad="PA5"/>
|
||||||
|
<pin position="14" pad="PA4"/>
|
||||||
|
<pin position="15" pad="AVCC"/>
|
||||||
|
<pin position="16" pad="AGND"/>
|
||||||
|
<pin position="17" pad="PA3"/>
|
||||||
|
<pin position="18" pad="PA2"/>
|
||||||
|
<pin position="19" pad="PA1"/>
|
||||||
|
<pin position="20" pad="VA0"/>
|
||||||
|
</pinout>
|
||||||
|
<pinout name="QFN32">
|
||||||
|
<pin position="1" pad="NC"/>
|
||||||
|
<pin position="2" pad="PB3"/>
|
||||||
|
<pin position="3" pad="NC"/>
|
||||||
|
<pin position="4" pad="VCC"/>
|
||||||
|
<pin position="5" pad="GND"/>
|
||||||
|
<pin position="6" pad="NC"/>
|
||||||
|
<pin position="7" pad="PB4"/>
|
||||||
|
<pin position="8" pad="PB5"/>
|
||||||
|
<pin position="9" pad="NC"/>
|
||||||
|
<pin position="10" pad="PB6"/>
|
||||||
|
<pin position="11" pad="PB7"/>
|
||||||
|
<pin position="12" pad="NC"/>
|
||||||
|
<pin position="13" pad="PA7"/>
|
||||||
|
<pin position="14" pad="PA6"/>
|
||||||
|
<pin position="15" pad="PA5"/>
|
||||||
|
<pin position="16" pad="NC"/>
|
||||||
|
<pin position="17" pad="PA4"/>
|
||||||
|
<pin position="18" pad="AVCC"/>
|
||||||
|
<pin position="19" pad="NC"/>
|
||||||
|
<pin position="20" pad="NC"/>
|
||||||
|
<pin position="21" pad="AGND"/>
|
||||||
|
<pin position="22" pad="PA3"/>
|
||||||
|
<pin position="23" pad="PA2"/>
|
||||||
|
<pin position="24" pad="NC"/>
|
||||||
|
<pin position="25" pad="PA1"/>
|
||||||
|
<pin position="26" pad="PA0"/>
|
||||||
|
<pin position="27" pad="NC"/>
|
||||||
|
<pin position="28" pad="NC"/>
|
||||||
|
<pin position="29" pad="NC"/>
|
||||||
|
<pin position="30" pad="PB0"/>
|
||||||
|
<pin position="31" pad="PB1"/>
|
||||||
|
<pin position="32" pad="PB2"/>
|
||||||
|
</pinout>
|
||||||
|
</pinouts>
|
||||||
</target-description-file>
|
</target-description-file>
|
||||||
|
|||||||
Reference in New Issue
Block a user