2021-04-04 21:04:12 +01:00
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<?xml version="1.0" encoding="UTF-8"?>
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2021-05-31 01:01:14 +01:00
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<target-description-file>
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2021-06-02 23:24:05 +01:00
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<variants>
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2021-06-12 01:43:30 +01:00
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<variant ordercode="ATtiny828-MU" package="VQFN32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
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<variant ordercode="ATtiny828-AU" package="TQFP32" pinout="QFP_QFN_32" tempmax="85" tempmin="-40"/>
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2021-06-02 23:24:05 +01:00
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</variants>
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2021-04-04 21:04:12 +01:00
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<device name="ATtiny828" architecture="AVR8" family="tinyAVR">
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2021-06-02 23:24:05 +01:00
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<address-spaces>
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<address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
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<memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
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pagesize="0x40"/>
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<memory-segment start="0x1f00" size="0x0100" type="flash" rw="RW" exec="1" name="BOOT_SECTION_1"
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pagesize="0x40"/>
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<memory-segment start="0x1e00" size="0x0200" type="flash" rw="RW" exec="1" name="BOOT_SECTION_2"
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pagesize="0x40"/>
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<memory-segment start="0x1c00" size="0x0400" type="flash" rw="RW" exec="1" name="BOOT_SECTION_3"
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pagesize="0x40"/>
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<memory-segment start="0x1800" size="0x0800" type="flash" rw="RW" exec="1" name="BOOT_SECTION_4"
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pagesize="0x40"/>
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</address-space>
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<address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
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<memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
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</address-space>
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<address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0003">
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<memory-segment start="0" size="0x0003" type="fuses" rw="RW" exec="0" name="FUSES"/>
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</address-space>
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<address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
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<memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
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</address-space>
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<address-space endianness="little" name="data" id="data" start="0x0000" size="0x0300">
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<memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
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<memory-segment name="MAPPED_IO" start="0x0020" size="0x00e0" type="io" external="false"/>
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<memory-segment name="IRAM" start="0x0100" size="0x0200" type="ram" external="false"/>
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</address-space>
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<address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0100">
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<memory-segment start="0x0000" size="0x0100" type="eeprom" rw="RW" exec="0" name="EEPROM"
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pagesize="0x04"/>
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</address-space>
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<address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
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<address-space endianness="little" name="osccal" id="osccal" start="0" size="2">
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<memory-segment start="0" size="2" type="osccal" rw="R" exec="0" name="OSCCAL"/>
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</address-space>
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</address-spaces>
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<peripherals>
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<module name="SPI">
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<instance name="SPI" caption="Serial Peripheral Interface">
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<register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data"
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caption="Serial Peripheral Interface"/>
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</instance>
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</module>
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<module name="PORT">
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<instance name="PORTA" caption="I/O Port">
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<register-group name="PORTA" name-in-module="PORTA" offset="0x00" address-space="data"
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caption="I/O Port"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTA" group="P" index="0" pad="PA0"/>
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<signal function="PORTA" group="P" index="1" pad="PA1"/>
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<signal function="PORTA" group="P" index="2" pad="PA2"/>
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<signal function="PORTA" group="P" index="3" pad="PA3"/>
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<signal function="PORTA" group="P" index="4" pad="PA4"/>
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<signal function="PORTA" group="P" index="5" pad="PA5"/>
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<signal function="PORTA" group="P" index="6" pad="PA6"/>
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<signal function="PORTA" group="P" index="7" pad="PA7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTB" caption="I/O Port">
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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caption="I/O Port"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTB" group="P" index="0" pad="PB0"/>
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<signal function="PORTB" group="P" index="1" pad="PB1"/>
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<signal function="PORTB" group="P" index="2" pad="PB2"/>
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<signal function="PORTB" group="P" index="3" pad="PB3"/>
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<signal function="PORTB" group="P" index="4" pad="PB4"/>
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<signal function="PORTB" group="P" index="5" pad="PB5"/>
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<signal function="PORTB" group="P" index="6" pad="PB6"/>
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<signal function="PORTB" group="P" index="7" pad="PB7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTC" caption="I/O Port">
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<register-group name="PORTC" name-in-module="PORTC" offset="0x00" address-space="data"
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caption="I/O Port"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTC" group="P" index="0" pad="PC0"/>
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<signal function="PORTC" group="P" index="1" pad="PC1"/>
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<signal function="PORTC" group="P" index="2" pad="PC2"/>
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<signal function="PORTC" group="P" index="3" pad="PC3"/>
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<signal function="PORTC" group="P" index="4" pad="PC4"/>
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<signal function="PORTC" group="P" index="5" pad="PC5"/>
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<signal function="PORTC" group="P" index="6" pad="PC6"/>
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<signal function="PORTC" group="P" index="7" pad="PC7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTD" caption="I/O Port">
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<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
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caption="I/O Port"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTD" group="P" index="0" pad="PD0"/>
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<signal function="PORTD" group="P" index="1" pad="PD1"/>
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<signal function="PORTD" group="P" index="2" pad="PD2"/>
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<signal function="PORTD" group="P" index="3" pad="PD3"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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</module>
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<module name="CPU">
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<instance name="CPU" caption="CPU Registers">
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<register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data"
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caption="CPU Registers"/>
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<parameters>
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<param name="CORE_VERSION" value="V2"/>
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<param name="NEW_INSTRUCTIONS" value="lpm rd,z+"/>
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</parameters>
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</instance>
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</module>
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<module name="TC8">
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<instance name="TC0" caption="Timer/Counter, 8-bit">
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<register-group name="TC0" name-in-module="TC0" offset="0x00" address-space="data"
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caption="Timer/Counter, 8-bit"/>
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</instance>
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</module>
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<module name="TC16">
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<instance name="TC1" caption="Timer/Counter, 16-bit">
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<register-group name="TC1" name-in-module="TC1" offset="0x00" address-space="data"
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caption="Timer/Counter, 16-bit"/>
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</instance>
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</module>
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<module name="TOCPM">
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<instance name="TOCPM" caption="Timer/Counter Output Compare Pin">
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<register-group name="TOCPM" name-in-module="TOCPM" offset="0x00" address-space="data"
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caption="Timer/Counter Output Compare Pin"/>
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</instance>
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</module>
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<module name="ADC">
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<instance name="ADC" caption="Analog-to-Digital Converter">
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<register-group name="ADC" name-in-module="ADC" offset="0x00" address-space="data"
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caption="Analog-to-Digital Converter"/>
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</instance>
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</module>
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<module name="AC">
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<instance name="AC" caption="Analog Comparator">
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<register-group name="AC" name-in-module="AC" offset="0x00" address-space="data"
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caption="Analog Comparator"/>
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</instance>
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</module>
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<module name="EXINT">
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<instance name="EXINT" caption="External Interrupts">
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<register-group name="EXINT" name-in-module="EXINT" offset="0x00" address-space="data"
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caption="External Interrupts"/>
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</instance>
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</module>
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<module name="WDT">
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<instance name="WDT" caption="Watchdog Timer">
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<register-group name="WDT" name-in-module="WDT" offset="0x00" address-space="data"
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caption="Watchdog Timer"/>
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</instance>
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</module>
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<module name="EEPROM">
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<instance name="EEPROM" caption="EEPROM">
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<register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data"
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caption="EEPROM"/>
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</instance>
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</module>
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<module name="TWI">
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<instance name="TWI" caption="Two Wire Serial Interface">
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<register-group name="TWI" name-in-module="TWI" offset="0x00" address-space="data"
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caption="Two Wire Serial Interface"/>
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</instance>
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</module>
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<module name="USART">
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<instance name="USART" caption="USART">
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<register-group name="USART" name-in-module="USART" offset="0x00" address-space="data"
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caption="USART"/>
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</instance>
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</module>
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<module name="FUSE">
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<instance name="FUSE" caption="Fuses">
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<register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses" caption="Fuses"/>
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</instance>
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</module>
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<module name="LOCKBIT">
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<instance name="LOCKBIT" caption="Lockbits">
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<register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits"
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caption="Lockbits"/>
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</instance>
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</module>
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</peripherals>
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<interrupts>
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<interrupt index="0" name="RESET"
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caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
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<interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
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<interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
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<interrupt index="3" name="PCINT0" caption="Pin Change Interrupt Request 0"/>
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<interrupt index="4" name="PCINT1" caption="Pin Change Interrupt Request 1"/>
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<interrupt index="5" name="PCINT2" caption="Pin Change Interrupt Request 2"/>
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<interrupt index="6" name="PCINT3" caption="Pin Change Interrupt Request 3"/>
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<interrupt index="7" name="WDT" caption="Watchdog Time-out Interrupt"/>
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<interrupt index="8" name="TIMER1_CAPT" caption="Timer/Counter1 Capture Event"/>
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<interrupt index="9" name="TIMER1_COMPA" caption="Timer/Counter1 Compare Match A"/>
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<interrupt index="10" name="TIMER1_COMPB" caption="Timer/Counter1 Compare Match B"/>
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<interrupt index="11" name="TIMER1_OVF" caption="Timer/Counter1 Overflow"/>
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<interrupt index="12" name="TIMER0_COMPA" caption="Timer/Counter0 Compare Match A"/>
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<interrupt index="13" name="TIMER0_COMPB" caption="Timer/Counter0 Compare Match B"/>
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<interrupt index="14" name="TIMER0_OVF" caption="Timer/Counter0 Overflow"/>
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<interrupt index="15" name="SPI_STC" caption="SPI Serial Transfer Complete"/>
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<interrupt index="16" name="USART_START" caption="USART, Start"/>
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<interrupt index="17" name="USART_RX" caption="USART Rx Complete"/>
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<interrupt index="18" name="USART_UDRE" caption="USART, Data Register Empty"/>
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<interrupt index="19" name="USART_TX" caption="USART Tx Complete"/>
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<interrupt index="20" name="ADC" caption="ADC Conversion Complete"/>
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<interrupt index="21" name="EE_READY" caption="EEPROM Ready"/>
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<interrupt index="22" name="ANALOG_COMP" caption="Analog Comparator"/>
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<interrupt index="23" name="TWI_SLAVE" caption="Two-wire Serial Interface"/>
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<interrupt index="24" name="SPM_Ready" caption="Store Program Memory Read"/>
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<interrupt index="25" name="QTRIP" caption="Touch Sensing"/>
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</interrupts>
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<interfaces>
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<interface name="ISP" type="isp"/>
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<interface name="HVPP" type="hvpp"/>
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<interface name="debugWIRE" type="dw"/>
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</interfaces>
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<property-groups>
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<property-group name="SIGNATURES">
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<property name="JTAGID" value="0x9314"/>
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<property name="SIGNATURE0" value="0x1e"/>
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<property name="SIGNATURE1" value="0x93"/>
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<property name="SIGNATURE2" value="0x14"/>
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</property-group>
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<property-group name="OCD">
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<property name="OCD_REVISION" value="1"/>
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<property name="OCD_DATAREG" value="0x31"/>
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<property name="PROGBASE" value="0x0000"/>
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</property-group>
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<property-group name="JTAG_INTERFACE">
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<property name="ALLOWFULLPAGESTREAM" value="0x00"/>
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</property-group>
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<property-group name="ISP_INTERFACE">
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<property name="IspEnterProgMode_timeout" value="200"/>
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<property name="IspEnterProgMode_stabDelay" value="100"/>
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<property name="IspEnterProgMode_cmdexeDelay" value="25"/>
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<property name="IspEnterProgMode_synchLoops" value="32"/>
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<property name="IspEnterProgMode_byteDelay" value="0"/>
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<property name="IspEnterProgMode_pollIndex" value="3"/>
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<property name="IspEnterProgMode_pollValue" value="0x53"/>
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<property name="IspLeaveProgMode_preDelay" value="1"/>
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<property name="IspLeaveProgMode_postDelay" value="1"/>
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<property name="IspChipErase_eraseDelay" value="45"/>
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<property name="IspChipErase_pollMethod" value="1"/>
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<property name="IspProgramFlash_mode" value="0x41"/>
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<property name="IspProgramFlash_blockSize" value="64"/>
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<property name="IspProgramFlash_delay" value="10"/>
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<property name="IspProgramFlash_cmd1" value="0x40"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd2" value="0x4C"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_mode" value="0x41"/>
|
|
|
|
|
<property name="IspProgramEeprom_blockSize" value="4"/>
|
|
|
|
|
<property name="IspProgramEeprom_delay" value="20"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd1" value="0xC1"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd2" value="0xC2"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadFuse_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadLock_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadSign_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadOsccal_pollIndex" value="4"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="PP_INTERFACE">
|
|
|
|
|
<property name="PpControlStack"
|
|
|
|
|
value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
|
|
|
|
|
<property name="PpEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="PpEnterProgMode_progModeDelay" value="0"/>
|
|
|
|
|
<property name="PpEnterProgMode_latchCycles" value="5"/>
|
|
|
|
|
<property name="PpEnterProgMode_toggleVtg" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_powerOffDelay" value="15"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayMs" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayUs" value="0"/>
|
|
|
|
|
<property name="PpLeaveProgMode_stabDelay" value="15"/>
|
|
|
|
|
<property name="PpLeaveProgMode_resetDelay" value="15"/>
|
|
|
|
|
<property name="PpChipErase_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpChipErase_pollTimeout" value="10"/>
|
|
|
|
|
<property name="PpProgramFlash_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramFlash_mode" value="0x0D"/>
|
|
|
|
|
<property name="PpProgramFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramEeprom_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramEeprom_mode" value="0x05"/>
|
|
|
|
|
<property name="PpProgramEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramFuse_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramFuse_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramLock_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramLock_pollTimeout" value="5"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="ISP_INTERFACE_STK600">
|
|
|
|
|
<property name="IspEnterProgMode_timeout" value="200"/>
|
|
|
|
|
<property name="IspEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="IspEnterProgMode_cmdexeDelay" value="25"/>
|
|
|
|
|
<property name="IspEnterProgMode_synchLoops" value="32"/>
|
|
|
|
|
<property name="IspEnterProgMode_byteDelay" value="0"/>
|
|
|
|
|
<property name="IspEnterProgMode_pollIndex" value="3"/>
|
|
|
|
|
<property name="IspEnterProgMode_pollValue" value="0x53"/>
|
|
|
|
|
<property name="IspLeaveProgMode_preDelay" value="1"/>
|
|
|
|
|
<property name="IspLeaveProgMode_postDelay" value="1"/>
|
|
|
|
|
<property name="IspChipErase_eraseDelay" value="45"/>
|
|
|
|
|
<property name="IspChipErase_pollMethod" value="1"/>
|
|
|
|
|
<property name="IspProgramFlash_mode" value="0x41"/>
|
|
|
|
|
<property name="IspProgramFlash_blockSize" value="64"/>
|
|
|
|
|
<property name="IspProgramFlash_delay" value="6"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd1" value="0x40"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd2" value="0x4C"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_mode" value="0x41"/>
|
|
|
|
|
<property name="IspProgramEeprom_blockSize" value="4"/>
|
|
|
|
|
<property name="IspProgramEeprom_delay" value="5"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd1" value="0xC1"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd2" value="0xC2"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadFuse_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadLock_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadSign_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadOsccal_pollIndex" value="4"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="PP_INTERFACE_STK600">
|
|
|
|
|
<property name="PpControlStack"
|
|
|
|
|
value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
|
|
|
|
|
<property name="PpEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="PpEnterProgMode_progModeDelay" value="0"/>
|
|
|
|
|
<property name="PpEnterProgMode_latchCycles" value="5"/>
|
|
|
|
|
<property name="PpEnterProgMode_toggleVtg" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_powerOffDelay" value="20"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayMs" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayUs" value="0"/>
|
|
|
|
|
<property name="PpLeaveProgMode_stabDelay" value="15"/>
|
|
|
|
|
<property name="PpLeaveProgMode_resetDelay" value="15"/>
|
|
|
|
|
<property name="PpChipErase_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpChipErase_pollTimeout" value="10"/>
|
|
|
|
|
<property name="PpProgramFlash_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramFlash_mode" value="0x0D"/>
|
|
|
|
|
<property name="PpProgramFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramEeprom_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramEeprom_mode" value="0x05"/>
|
|
|
|
|
<property name="PpProgramEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramFuse_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramFuse_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramLock_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramLock_pollTimeout" value="5"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
</property-groups>
|
|
|
|
|
</device>
|
|
|
|
|
<modules>
|
|
|
|
|
<module caption="Fuses" name="FUSE">
|
|
|
|
|
<register-group caption="Fuses" name="FUSE">
|
|
|
|
|
<register caption="" name="EXTENDED" offset="0x02" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Select boot size" mask="0x06" name="BOOTSZ" values="ENUM_BOOTSZ"/>
|
|
|
|
|
<bitfield caption="Boot Reset vector Enabled" mask="0x01" name="BOOTRST"/>
|
|
|
|
|
<bitfield caption="BOD mode of operation when the device is in sleep mode" mask="0xC0" name="BODPD"
|
|
|
|
|
values="ENUM_BODMODE"/>
|
|
|
|
|
<bitfield caption="BOD mode of operation when the device is active or idle" mask="0x30"
|
|
|
|
|
name="BODACT" values="ENUM_BODMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="HIGH" offset="0x01" size="1" initval="0xDF">
|
|
|
|
|
<bitfield caption="Reset Disabled (Enable PC6 as i/o pin)]" mask="0x80" name="RSTDISBL"/>
|
|
|
|
|
<bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
|
|
|
|
|
<bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
|
|
|
|
|
<bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
|
|
|
|
|
<bitfield caption="Preserve EEPROM through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
|
|
|
|
|
<bitfield caption="Brown-out Detector trigger level" mask="0x07" name="BODLEVEL"
|
|
|
|
|
values="ENUM_BODLEVEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="LOW" offset="0x00" size="1" initval="0x6E">
|
|
|
|
|
<bitfield caption="Divide clock by 8 internally" mask="0x80" name="CKDIV8"/>
|
|
|
|
|
<bitfield caption="Clock output on PORTB0" mask="0x40" name="CKOUT"/>
|
|
|
|
|
<bitfield caption="Select Clock Source" mask="0x33" name="SUT_CKSEL" values="ENUM_SUT_CKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ENUM_SUT_CKSEL">
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms" name="EXTCLK_6CK_14CK_0MS"
|
|
|
|
|
value="0x00"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms" name="EXTCLK_6CK_14CK_0MS"
|
|
|
|
|
value="0x01"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms" name="EXTCLK_6CK_14CK_4MS1"
|
|
|
|
|
value="0x10"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms" name="EXTCLK_6CK_14CK_4MS1"
|
|
|
|
|
value="0x11"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS"
|
|
|
|
|
value="0x20"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS"
|
|
|
|
|
value="0x30"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS"
|
|
|
|
|
value="0x21"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS"
|
|
|
|
|
value="0x31"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_0MS" value="0x02"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_4MS1" value="0x12"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_65MS" value="0x22"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_65MS" value="0x32"/>
|
|
|
|
|
<value caption="Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 0 ms"
|
|
|
|
|
name="INTULPOSC_32KHZ_6CK_14CK_0MS" value="0x03"/>
|
|
|
|
|
<value caption="Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 4.1 ms"
|
|
|
|
|
name="INTULPOSC_32KHZ_6CK_14CK_4MS1" value="0x13"/>
|
|
|
|
|
<value caption="Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms"
|
|
|
|
|
name="INTULPOSC_32KHZ_6CK_14CK_65MS" value="0x23"/>
|
|
|
|
|
<value caption="Int. ULP Osc. 32kHz; Start-up time PWRDWN/RESET: 6 + 14 CK + 65 ms"
|
|
|
|
|
name="INTULPOSC_32KHZ_6CK_14CK_65MS" value="0x33"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BODLEVEL">
|
|
|
|
|
<value caption="Brown-out detection disabled" name="DISABLED" value="0x07"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=4.3 V" name="4V3" value="0x04"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=2.7 V" name="2V7" value="0x05"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=1.8 V" name="1V8" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BOOTSZ">
|
|
|
|
|
<value caption="Boot Flash size=128 words Boot address=$0F80" name="128W_0F80" value="0x03"/>
|
|
|
|
|
<value caption="Boot Flash size=256 words Boot address=$0F00" name="256W_0F00" value="0x02"/>
|
|
|
|
|
<value caption="Boot Flash size=512 words Boot address=$0E00" name="512W_0E00" value="0x01"/>
|
|
|
|
|
<value caption="Boot Flash size=1024 words Boot address=$0C00" name="1024W_0C00" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BODMODE">
|
|
|
|
|
<value caption="Sampled" name="BOD_SAMPLED" value="0x01"/>
|
|
|
|
|
<value caption="Enabled" name="BOD_ENABLED" value="0x02"/>
|
|
|
|
|
<value caption="Disabled" name="BOD_DISABLED" value="0x03"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Lockbits" name="LOCKBIT">
|
|
|
|
|
<register-group caption="Lockbits" name="LOCKBIT">
|
|
|
|
|
<register caption="" name="LOCKBIT" offset="0x00" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
|
|
|
|
|
<bitfield caption="Boot Loader Protection Mode" mask="0x0C" name="BLB0" values="ENUM_BLB"/>
|
|
|
|
|
<bitfield caption="Boot Loader Protection Mode" mask="0x30" name="BLB1" values="ENUM_BLB2"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ENUM_LB">
|
|
|
|
|
<value caption="Further programming and verification disabled" name="PROG_VER_DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="Further programming disabled" name="PROG_DISABLED" value="0x02"/>
|
|
|
|
|
<value caption="No memory lock features enabled" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BLB">
|
|
|
|
|
<value caption="LPM and SPM prohibited in Application Section" name="LPM_SPM_DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="LPM prohibited in Application Section" name="LPM_DISABLE" value="0x01"/>
|
|
|
|
|
<value caption="SPM prohibited in Application Section" name="SPM_DISABLE" value="0x02"/>
|
|
|
|
|
<value caption="No lock on SPM and LPM in Application Section" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BLB2">
|
|
|
|
|
<value caption="LPM and SPM prohibited in Boot Section" name="LPM_SPM_DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="LPM prohibited in Boot Section" name="LPM_DISABLE" value="0x01"/>
|
|
|
|
|
<value caption="SPM prohibited in Boot Section" name="SPM_DISABLE" value="0x02"/>
|
|
|
|
|
<value caption="No lock on SPM and LPM in Boot Section" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Serial Peripheral Interface" name="SPI">
|
|
|
|
|
<register-group caption="Serial Peripheral Interface" name="SPI">
|
|
|
|
|
<register caption="SPI Data Register" name="SPDR" offset="0x4E" size="1" mask="0xFF" ocd-rw=""/>
|
|
|
|
|
<register caption="SPI Status Register" name="SPSR" offset="0x4D" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
|
|
|
|
|
<bitfield caption="Write Collision Flag" mask="0x40" name="WCOL"/>
|
|
|
|
|
<bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="SPI Control Register" name="SPCR" offset="0x4C" size="1">
|
|
|
|
|
<bitfield caption="SPI Interrupt Enable" mask="0x80" name="SPIE"/>
|
|
|
|
|
<bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
|
|
|
|
|
<bitfield caption="Data Order" mask="0x20" name="DORD"/>
|
|
|
|
|
<bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
|
|
|
|
|
<bitfield caption="Clock polarity" mask="0x08" name="CPOL"/>
|
|
|
|
|
<bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
|
|
|
|
|
<bitfield caption="SPI Clock Rate Selects" mask="0x03" name="SPR" values="COMM_SCK_RATE_3BIT"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="COMM_SCK_RATE_3BIT">
|
|
|
|
|
<value caption="fosc/4" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="fosc/16" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="fosc/64" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="fosc/128" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="fosc/2" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="fosc/8" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="fosc/32" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="fosc/64" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="I/O Port" name="PORT">
|
|
|
|
|
<register-group caption="I/O Port" name="PORTA">
|
|
|
|
|
<register caption="Pull-up Enable Control Register" name="PUEA" offset="0x23" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port A Data Register" name="PORTA" offset="0x22" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Data Direction Register, Port A" name="DDRA" offset="0x21" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port A Input Pins" name="PINA" offset="0x20" size="1" mask="0xFF"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="I/O Port" name="PORTB">
|
|
|
|
|
<register caption="Pull-up Enable Control Register" name="PUEB" offset="0x27" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port B Data Register" name="PORTB" offset="0x26" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Data Direction Register, Port B" name="DDRB" offset="0x25" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port B Input Pins" name="PINB" offset="0x24" size="1" mask="0xFF"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="I/O Port" name="PORTC">
|
|
|
|
|
<register caption="Port High Drive Enable Register" name="PHDE" offset="0x34" size="1">
|
|
|
|
|
<bitfield caption="Port C High Drive Enable" mask="0x04" name="PHDEC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pull-up Enable Control Register" name="PUEC" offset="0x2B" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port C Data Register" name="PORTC" offset="0x2A" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Data Direction Register, Port C" name="DDRC" offset="0x29" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port C Input Pins" name="PINC" offset="0x28" size="1" mask="0xFF"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="I/O Port" name="PORTD">
|
|
|
|
|
<register caption="Pull-up Enable Control Register" name="PUED" offset="0x2F" size="1" mask="0x0F"/>
|
|
|
|
|
<register caption="Port D Data Register" name="PORTD" offset="0x2E" size="1" mask="0x0F"/>
|
|
|
|
|
<register caption="Data Direction Register, Port D" name="DDRD" offset="0x2D" size="1" mask="0x0F"/>
|
|
|
|
|
<register caption="Port D Input Pins" name="PIND" offset="0x2C" size="1" mask="0x0F"/>
|
|
|
|
|
</register-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="CPU Registers" name="CPU">
|
|
|
|
|
<register-group caption="CPU Registers" name="CPU">
|
|
|
|
|
<register caption="Power Reduction Register" name="PRR" offset="0x64" size="1">
|
|
|
|
|
<bitfield caption="Power Reduction TWI" mask="0x80" name="PRTWI"/>
|
|
|
|
|
<bitfield caption="Power Reduction Timer/Counter0" mask="0x20" name="PRTIM0"/>
|
|
|
|
|
<bitfield caption="Power Reduction Timer/Counter1" mask="0x08" name="PRTIM1"/>
|
|
|
|
|
<bitfield caption="Power Reduction SPI" mask="0x04" name="PRSPI"/>
|
|
|
|
|
<bitfield caption="Power Reduction USART 0" mask="0x02" name="PRUSART0"/>
|
|
|
|
|
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Configuration Change Protection" name="CCP" offset="0x56" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Clock Prescale Register" name="CLKPR" offset="0x61" size="1">
|
|
|
|
|
<bitfield caption="Clock Prescaler Select Bits" mask="0x0F" name="CLKPS"
|
|
|
|
|
values="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="SREG" offset="0x5F" size="1">
|
|
|
|
|
<bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
|
|
|
|
|
<bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
|
|
|
|
|
<bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
|
|
|
|
|
<bitfield caption="Sign Bit" mask="0x10" name="S"/>
|
|
|
|
|
<bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
|
|
|
|
|
<bitfield caption="Negative Flag" mask="0x04" name="N"/>
|
|
|
|
|
<bitfield caption="Zero Flag" mask="0x02" name="Z"/>
|
|
|
|
|
<bitfield caption="Carry Flag" mask="0x01" name="C"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Stack Pointer " name="SP" offset="0x5D" size="2" mask="0x03FF"/>
|
|
|
|
|
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Vector Select" mask="0x02" name="IVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="MCU Status Register" name="MCUSR" offset="0x54" size="1">
|
|
|
|
|
<bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
|
|
|
|
|
<bitfield caption="Brown-out Reset Flag" mask="0x04" name="BORF"/>
|
|
|
|
|
<bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
|
|
|
|
|
<bitfield caption="Power-on reset flag" mask="0x01" name="PORF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Purpose I/O Register 2" name="GPIOR2" offset="0x4B" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="General Purpose I/O Register 1" name="GPIOR1" offset="0x4A" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="General Purpose I/O Register 0" name="GPIOR0" offset="0x3E" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Sleep Mode Control Register" name="SMCR" offset="0x53" size="1">
|
|
|
|
|
<bitfield caption="Sleep Mode Select Bits" mask="0x06" name="SM" values="CPU_SLEEP_MODE2"/>
|
|
|
|
|
<bitfield caption="Sleep Enable" mask="0x01" name="SE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Store Program Memory Control and Status Register" name="SPMCSR" offset="0x57"
|
|
|
|
|
size="1">
|
|
|
|
|
<bitfield caption="SPM Interrupt Enable" mask="0x80" name="SPMIE"/>
|
|
|
|
|
<bitfield caption="Read-While-Write Section Busy" mask="0x40" name="RWWSB"/>
|
|
|
|
|
<bitfield caption="Read Device Signature Imprint Table" mask="0x20" name="RSIG"/>
|
|
|
|
|
<bitfield caption="Read-While-Write section read enable" mask="0x10" name="RWWSRE"/>
|
|
|
|
|
<bitfield caption="Read/Write Fuse and Lock Bits" mask="0x08" name="RWFLB"/>
|
|
|
|
|
<bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
|
|
|
|
|
<bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
|
|
|
|
|
<bitfield caption="Store Program Memory Enable" mask="0x01" name="SPMEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Calibration Register 8MHz" name="OSCCAL0" offset="0x66" size="1"
|
|
|
|
|
mask="0xFF"/>
|
|
|
|
|
<register caption="Oscillator Calibration Register 32kHz" name="OSCCAL1" offset="0x67" size="1"
|
|
|
|
|
mask="0x03"/>
|
|
|
|
|
<register caption="Oscillator Temperature Calibration Register A" name="OSCTCAL0A" offset="0xF0"
|
|
|
|
|
size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Oscillator Temperature Calibration Register B" name="OSCTCAL0B" offset="0xF1"
|
|
|
|
|
size="1" mask="0xFF"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Oscillator Calibration Values" name="OSCCAL_VALUE_ADDRESSES">
|
|
|
|
|
<value value="0x00" caption="8.0 MHz" name="8_0_MHz"/>
|
|
|
|
|
<value value="0x03" caption="32 kHz" name="32_kHz"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="CPU_CLK_PRESCALE_4_BITS_SMALL">
|
|
|
|
|
<value caption="1" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="2" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="4" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="8" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="16" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="32" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="64" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="128" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="256" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="CPU_SLEEP_MODE2">
|
|
|
|
|
<value caption="Idle" name="IDLE" value="0x00"/>
|
|
|
|
|
<value caption="ADC Noise Reduction (If Available)" name="ADC" value="0x01"/>
|
|
|
|
|
<value caption="Power Down" name="PDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Timer/Counter, 8-bit" name="TC8">
|
|
|
|
|
<register-group caption="Timer/Counter, 8-bit" name="TC0">
|
|
|
|
|
<register caption="Timer/Counter0 Output Compare Register" name="OCR0B" offset="0x48" size="1"
|
|
|
|
|
mask="0xFF"/>
|
|
|
|
|
<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1"
|
|
|
|
|
mask="0xFF"/>
|
|
|
|
|
<register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Timer/Counter Control Register B" name="TCCR0B" offset="0x45" size="1">
|
|
|
|
|
<bitfield caption="Force Output Compare A" mask="0x80" name="FOC0A"/>
|
|
|
|
|
<bitfield caption="Force Output Compare B" mask="0x40" name="FOC0B"/>
|
|
|
|
|
<bitfield caption="" mask="0x08" name="WGM02"/>
|
|
|
|
|
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
|
|
|
|
|
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
|
|
|
|
|
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0 Interrupt Mask Register" name="TIMSK0" offset="0x6E" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Match B Interrupt Enable" mask="0x04"
|
|
|
|
|
name="OCIE0B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Match A Interrupt Enable" mask="0x02"
|
|
|
|
|
name="OCIE0A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Overflow Interrupt Enable" mask="0x01" name="TOIE0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0 Interrupt Flag register" name="TIFR0" offset="0x35" size="1"
|
|
|
|
|
ocd-rw="R">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x04" name="OCF0B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
|
|
|
|
<bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSRSYNC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
|
|
|
|
<value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Timer/Counter, 16-bit" name="TC16">
|
|
|
|
|
<register-group caption="Timer/Counter, 16-bit" name="TC1">
|
|
|
|
|
<register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Output CompareB Match Interrupt Enable" mask="0x04"
|
|
|
|
|
name="OCIE1B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Output CompareA Match Interrupt Enable" mask="0x02"
|
|
|
|
|
name="OCIE1A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Overflow Interrupt Enable" mask="0x01" name="TOIE1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter Interrupt Flag register" name="TIFR1" offset="0x36" size="1"
|
|
|
|
|
ocd-rw="R">
|
|
|
|
|
<bitfield caption="Input Capture Flag 1" mask="0x20" name="ICF1"/>
|
|
|
|
|
<bitfield caption="Output Compare Flag 1B" mask="0x04" name="OCF1B"/>
|
|
|
|
|
<bitfield caption="Output Compare Flag 1A" mask="0x02" name="OCF1A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Overflow Flag" mask="0x01" name="TOV1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register A" name="TCCR1A" offset="0x80" size="1">
|
|
|
|
|
<bitfield caption="Compare Output Mode 1A, bits" mask="0xC0" name="COM1A"/>
|
|
|
|
|
<bitfield caption="Compare Output Mode 1B, bits" mask="0x30" name="COM1B"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register B" name="TCCR1B" offset="0x81" size="1">
|
|
|
|
|
<bitfield caption="Input Capture 1 Noise Canceler" mask="0x80" name="ICNC1"/>
|
|
|
|
|
<bitfield caption="Input Capture 1 Edge Select" mask="0x40" name="ICES1"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x18" name="WGM1" lsb="2"/>
|
|
|
|
|
<bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
|
|
|
|
|
values="CLK_SEL_3BIT_EXT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register C" name="TCCR1C" offset="0x82" size="1" ocd-rw="">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="FOC1A"/>
|
|
|
|
|
<bitfield caption="" mask="0x40" name="FOC1B"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF"/>
|
|
|
|
|
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
|
|
|
|
mask="0xFFFF"/>
|
|
|
|
|
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
|
|
|
|
mask="0xFFFF"/>
|
|
|
|
|
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
|
|
|
|
mask="0xFFFF"/>
|
|
|
|
|
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
|
|
|
|
<bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSRSYNC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
|
|
|
|
<value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Timer/Counter Output Compare Pin" name="TOCPM">
|
|
|
|
|
<register-group caption="Timer/Counter Output Compare Pin" name="TOCPM">
|
|
|
|
|
<register caption="Timer Output Compare Pin Mux Selection 1" name="TOCPMSA1" offset="0xE9" size="1">
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 7 Selection Bits" mask="0xC0" name="TOCC7S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 6 Selection Bits" mask="0x30" name="TOCC6S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 5 Selection Bits" mask="0x0C" name="TOCC5S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 4 Selection Bits" mask="0x03" name="TOCC4S"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer Output Compare Pin Mux Selection 0" name="TOCPMSA0" offset="0xE8" size="1">
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 3 Selection Bits" mask="0xC0" name="TOCC3S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 2 Selection Bits" mask="0x30" name="TOCC2S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 1 Selection Bits" mask="0x0C" name="TOCC1S"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 0 Selection Bits" mask="0x03" name="TOCC0S"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer Output Compare Pin Mux Channel Output Enable" name="TOCPMCOE" offset="0xE2"
|
|
|
|
|
size="1">
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 7 Output Enable" mask="0x80" name="TOCC7OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 6 Output Enable" mask="0x40" name="TOCC6OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 5 Output Enable" mask="0x20" name="TOCC5OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 4 Output Enable" mask="0x10" name="TOCC4OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 3 Output Enable" mask="0x08" name="TOCC3OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 2 Output Enable" mask="0x04" name="TOCC2OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 1 Output Enable" mask="0x02" name="TOCC1OE"/>
|
|
|
|
|
<bitfield caption="Timer Output Compare Channel 0 Output Enable" mask="0x01" name="TOCC0OE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Analog-to-Digital Converter" name="ADC">
|
|
|
|
|
<register-group caption="Analog-to-Digital Converter" name="ADC">
|
|
|
|
|
<register caption="The ADC multiplexer Selection Register A" name="ADMUXA" offset="0x7C" size="1">
|
|
|
|
|
<bitfield caption="Analog Channel Selection Bits 4:0" mask="0x1F" name="MUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="The ADC multiplexer Selection Register B" name="ADMUXB" offset="0x7D" size="1">
|
|
|
|
|
<bitfield caption="Reference Selection Bit" mask="0x20" name="REFS"/>
|
|
|
|
|
<bitfield caption="Analog Channel Selection Bit 5" mask="0x01" name="MUX5"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="The ADC Control and Status register" name="ADCSRA" offset="0x7A" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
|
|
|
|
|
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
|
|
|
|
|
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
|
|
|
|
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
|
|
|
|
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
|
|
|
|
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"
|
|
|
|
|
values="ANALOG_ADC_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF"/>
|
|
|
|
|
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
|
|
|
|
|
<bitfield caption="" mask="0x08" name="ADLAR"/>
|
|
|
|
|
<bitfield caption="ADC Auto Trigger Sources" mask="0x07" name="ADTS"
|
|
|
|
|
values="ANALOG_ADC_AUTO_TRIGGER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 2" name="DIDR3" offset="0xDF" size="1">
|
|
|
|
|
<bitfield caption="ADC27 Digital input Disable" mask="0x08" name="ADC27D"/>
|
|
|
|
|
<bitfield caption="ADC26 Digital input Disable" mask="0x04" name="ADC26D"/>
|
|
|
|
|
<bitfield caption="ADC25 Digital input Disable" mask="0x02" name="ADC25D"/>
|
|
|
|
|
<bitfield caption="ADC24 Digital input Disable" mask="0x01" name="ADC24D"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 2" name="DIDR2" offset="0xDE" size="1">
|
|
|
|
|
<bitfield caption="ADC23 Digital input Disable" mask="0x80" name="ADC23D"/>
|
|
|
|
|
<bitfield caption="ADC22 Digital input Disable" mask="0x40" name="ADC22D"/>
|
|
|
|
|
<bitfield caption="ADC21 Digital input Disable" mask="0x20" name="ADC21D"/>
|
|
|
|
|
<bitfield caption="ADC20 Digital input Disable" mask="0x10" name="ADC20D"/>
|
|
|
|
|
<bitfield caption="ADC19 Digital input Disable" mask="0x08" name="ADC19D"/>
|
|
|
|
|
<bitfield caption="ADC18 Digital input Disable" mask="0x04" name="ADC18D"/>
|
|
|
|
|
<bitfield caption="ADC17 Digital input Disable" mask="0x02" name="ADC17D"/>
|
|
|
|
|
<bitfield caption="ADC16 Digital input Disable" mask="0x01" name="ADC16D"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 1" name="DIDR1" offset="0x7F" size="1">
|
|
|
|
|
<bitfield caption="ADC15 Digital input Disable" mask="0x80" name="ADC15D"/>
|
|
|
|
|
<bitfield caption="ADC14 Digital input Disable" mask="0x40" name="ADC14D"/>
|
|
|
|
|
<bitfield caption="ADC13 Digital input Disable" mask="0x20" name="ADC13D"/>
|
|
|
|
|
<bitfield caption="ADC12 Digital input Disable" mask="0x10" name="ADC12D"/>
|
|
|
|
|
<bitfield caption="ADC11 Digital input Disable" mask="0x08" name="ADC11D"/>
|
|
|
|
|
<bitfield caption="ADC10 Digital input Disable" mask="0x04" name="ADC10D"/>
|
|
|
|
|
<bitfield caption="ADC9 Digital input Disable" mask="0x02" name="ADC9D"/>
|
|
|
|
|
<bitfield caption="ADC8 Digital input Disable" mask="0x01" name="ADC8D"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 0" name="DIDR0" offset="0x7E" size="1">
|
|
|
|
|
<bitfield caption="ADC7 Digital input Disable" mask="0x80" name="ADC7D"/>
|
|
|
|
|
<bitfield caption="ADC6 Digital input Disable" mask="0x40" name="ADC6D"/>
|
|
|
|
|
<bitfield caption="ADC5 Digital input Disable" mask="0x20" name="ADC5D"/>
|
|
|
|
|
<bitfield caption="ADC4 Digital input Disable" mask="0x10" name="ADC4D"/>
|
|
|
|
|
<bitfield caption="ADC3 Digital input Disable" mask="0x08" name="ADC3D"/>
|
|
|
|
|
<bitfield caption="ADC2 Digital input Disable" mask="0x04" name="ADC2D"/>
|
|
|
|
|
<bitfield caption="ADC1 Digital input Disable" mask="0x02" name="ADC1D"/>
|
|
|
|
|
<bitfield caption="ADC0 Digital input Disable" mask="0x01" name="ADC0D"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_ADC_PRESCALER">
|
|
|
|
|
<value caption="2" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="2" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="4" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="8" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="16" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="32" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="64" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="128" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_ADC_AUTO_TRIGGER">
|
|
|
|
|
<value caption="Free Running mode" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Analog Comparator" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="External Interrupt Request 0" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Timer/Counter0 Compare Match A" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Timer/Counter0 Overflow" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Timer/Counter1 Compare Match B" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Timer/Counter1 Overflow" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Timer/Counter1 Capture Event" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Analog Comparator" name="AC">
|
|
|
|
|
<register-group caption="Analog Comparator" name="AC">
|
|
|
|
|
<register caption="Analog Comparator Control And Status Register B" name="ACSRB" offset="0x4F" size="1">
|
|
|
|
|
<bitfield caption="Hysteresis Select" mask="0x80" name="HSEL"/>
|
|
|
|
|
<bitfield caption="Hysteresis Level" mask="0x40" name="HLEV"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Negative Input Multiplexer" mask="0x0C" name="ACNMUX"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Positive Input Multiplexer Bits 1:0" mask="0x03"
|
|
|
|
|
name="ACPMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator Control And Status Register A" name="ACSRA" offset="0x50" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator Disable" mask="0x80" name="ACD"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Positive Input Multiplexer Bit 2" mask="0x40" name="ACPMUX2"/>
|
|
|
|
|
<bitfield caption="Analog Compare Output" mask="0x20" name="ACO"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Interrupt Flag" mask="0x10" name="ACI"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Interrupt Enable" mask="0x08" name="ACIE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Input Capture Enable" mask="0x04" name="ACIC"/>
|
|
|
|
|
<bitfield caption="Analog Comparator Interrupt Mode Select bits" mask="0x03" name="ACIS"
|
|
|
|
|
values="ANALOG_COMP_INTERRUPT"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_COMP_INTERRUPT">
|
|
|
|
|
<value caption="Interrupt on Toggle" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on Falling Edge" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on Rising Edge" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="External Interrupts" name="EXINT">
|
|
|
|
|
<register-group caption="External Interrupts" name="EXINT">
|
|
|
|
|
<register caption="External Interrupt Control Register" name="EICRA" offset="0x69" size="1">
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control 1 Bits" mask="0x0C" name="ISC1"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control 0 Bits" mask="0x03" name="ISC0"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Interrupt Mask Register" name="EIMSK" offset="0x3D" size="1">
|
|
|
|
|
<bitfield caption="External Interrupt Request Enables" mask="0x03" name="INT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Interrupt Flag Register" name="EIFR" offset="0x3C" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="External Interrupt Flags" mask="0x03" name="INTF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x68" size="1">
|
|
|
|
|
<bitfield caption="Pin Change Interrupt Enables" mask="0x0F" name="PCIE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Mask Register 3" name="PCMSK3" offset="0x73" size="1">
|
|
|
|
|
<bitfield caption="Pin Change Enable Masks" mask="0x0F" name="PCINT" lsb="24"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Mask Register 2" name="PCMSK2" offset="0x6D" size="1">
|
|
|
|
|
<bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT" lsb="16"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Mask Register 1" name="PCMSK1" offset="0x6C" size="1">
|
|
|
|
|
<bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT" lsb="8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Mask Register 0" name="PCMSK0" offset="0x6B" size="1">
|
|
|
|
|
<bitfield caption="Pin Change Enable Masks" mask="0xFF" name="PCINT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x3B" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="Pin Change Interrupt Flags" mask="0x0F" name="PCIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Interrupt Sense Control" name="INTERRUPT_SENSE_CONTROL">
|
|
|
|
|
<value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Any Logical Change of INTX" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Watchdog Timer" name="WDT">
|
|
|
|
|
<register-group caption="Watchdog Timer" name="WDT">
|
|
|
|
|
<register caption="Watchdog Timer Control and Status Register" name="WDTCSR" offset="0x60" size="1">
|
|
|
|
|
<bitfield caption="Watchdog Timer Interrupt Flag" mask="0x80" name="WDIF"/>
|
|
|
|
|
<bitfield caption="Watchdog Timer Interrupt Enable" mask="0x40" name="WDIE"/>
|
|
|
|
|
<bitfield caption="Watchdog Timer Prescaler Bits" mask="0x27" name="WDP"
|
|
|
|
|
values="WDOG_TIMER_PRESCALE_4BITS_32KHZ"/>
|
|
|
|
|
<bitfield caption="Watch Dog Enable" mask="0x08" name="WDE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="WDOG_TIMER_PRESCALE_4BITS_32KHZ">
|
|
|
|
|
<value caption="Oscillator Cycles 512 (16 ms)" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Oscillator Cycles 1K (32 ms)" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Oscillator Cycles 2K (64 ms)" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Oscillator Cycles 4K (0.125 s)" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Oscillator Cycles 8K (0.25 s)" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Oscillator Cycles 16K (0.5 s)" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Oscillator Cycles 32K (1.0 s)" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Oscillator Cycles 64K (2.0 s)" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="Oscillator Cycles 128K (4.0 s)" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
<value caption="Oscillator Cycles 256K (8.0 s)" name="VAL_0x09" value="0x09"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="EEPROM" name="EEPROM">
|
|
|
|
|
<register-group caption="EEPROM" name="EEPROM">
|
|
|
|
|
<register caption="EEPROM Read/Write Access" name="EEAR" offset="0x41" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
|
|
|
|
|
<bitfield caption="EEPROM Programming Mode Bits" mask="0x30" name="EEPM" values="EEP_MODE"/>
|
|
|
|
|
<bitfield caption="EEProm Ready Interrupt Enable" mask="0x08" name="EERIE"/>
|
|
|
|
|
<bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMPE"/>
|
|
|
|
|
<bitfield caption="EEPROM Write Enable" mask="0x02" name="EEPE"/>
|
|
|
|
|
<bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="EEP_MODE">
|
|
|
|
|
<value caption="Erase and Write in one operation" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Erase Only" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Write Only" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="Two Wire Serial Interface" name="TWI">
|
|
|
|
|
<register-group caption="Two Wire Serial Interface" name="TWI">
|
|
|
|
|
<register caption="TWI Slave Control Register A" name="TWSCRA" offset="0xB8" size="1">
|
|
|
|
|
<bitfield caption="TWI SDA Hold Time Enable" mask="0x80" name="TWSHE"/>
|
|
|
|
|
<bitfield caption="TWI Data Interrupt Enable" mask="0x20" name="TWDIE"/>
|
|
|
|
|
<bitfield caption="TWI Address/Stop Interrupt Enable" mask="0x10" name="TWASIE"/>
|
|
|
|
|
<bitfield caption="Two-Wire Interface Enable" mask="0x08" name="TWEN"/>
|
|
|
|
|
<bitfield caption="TWI Stop Interrupt Enable" mask="0x04" name="TWSIE"/>
|
|
|
|
|
<bitfield caption="TWI Promiscuous Mode Enable" mask="0x02" name="TWPME"/>
|
|
|
|
|
<bitfield caption="TWI Smart Mode Enable" mask="0x01" name="TWSME"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="TWI Slave Control Register B" name="TWSCRB" offset="0xB9" size="1">
|
|
|
|
|
<bitfield caption="TWI High Noise Mode" mask="0x08" name="TWHNM"/>
|
|
|
|
|
<bitfield caption="TWI Acknowledge Action" mask="0x04" name="TWAA"/>
|
|
|
|
|
<bitfield caption="" mask="0x03" name="TWCMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="TWI Slave Status Register A" name="TWSSRA" offset="0xBA" size="1">
|
|
|
|
|
<bitfield caption="TWI Data Interrupt Flag." mask="0x80" name="TWDIF"/>
|
|
|
|
|
<bitfield caption="TWI Address/Stop Interrupt Flag" mask="0x40" name="TWASIF"/>
|
|
|
|
|
<bitfield caption="TWI Clock Hold" mask="0x20" name="TWCH"/>
|
|
|
|
|
<bitfield caption="TWI Receive Acknowledge" mask="0x10" name="TWRA"/>
|
|
|
|
|
<bitfield caption="TWI Collision" mask="0x08" name="TWC"/>
|
|
|
|
|
<bitfield caption="TWI Bus Error" mask="0x04" name="TWBE"/>
|
|
|
|
|
<bitfield caption="TWI Read/Write Direction" mask="0x02" name="TWDIR"/>
|
|
|
|
|
<bitfield caption="TWI Address or Stop" mask="0x01" name="TWAS"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="TWI Slave Address Register" name="TWSA" offset="0xBC" size="1" mask="0xFF"
|
|
|
|
|
ocd-rw="R"/>
|
|
|
|
|
<register caption="TWI Slave Data Register" name="TWSD" offset="0xBD" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="TWI slave data bit" mask="0xFF" name="TWSD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="TWI Slave Address Mask Register" name="TWSAM" offset="0xBB" size="1">
|
|
|
|
|
<bitfield caption="TWI Address Mask Bits" mask="0xFE" name="TWSAM" lsb="1"/>
|
|
|
|
|
<bitfield caption="TWI Address Enable" mask="0x01" name="TWAE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
<module caption="USART" name="USART">
|
|
|
|
|
<register-group caption="USART" name="USART">
|
|
|
|
|
<register caption="USART I/O Data Register" name="UDR" offset="0xC6" size="1" mask="0xFF" ocd-rw=""/>
|
|
|
|
|
<register caption="USART Control and Status Register A" name="UCSRA" offset="0xC0" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="USART Receive Complete" mask="0x80" name="RXC"/>
|
|
|
|
|
<bitfield caption="USART Transmitt Complete" mask="0x40" name="TXC"/>
|
|
|
|
|
<bitfield caption="USART Data Register Empty" mask="0x20" name="UDRE"/>
|
|
|
|
|
<bitfield caption="Framing Error" mask="0x10" name="FE"/>
|
|
|
|
|
<bitfield caption="Data overRun" mask="0x08" name="DOR"/>
|
|
|
|
|
<bitfield caption="Parity Error" mask="0x04" name="UPE"/>
|
|
|
|
|
<bitfield caption="Double the USART transmission speed" mask="0x02" name="U2X"/>
|
|
|
|
|
<bitfield caption="Multi-processor Communication Mode" mask="0x01" name="MPCM"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control and Status Register B" name="UCSRB" offset="0xC1" size="1">
|
|
|
|
|
<bitfield caption="RX Complete Interrupt Enable" mask="0x80" name="RXCIE"/>
|
|
|
|
|
<bitfield caption="TX Complete Interrupt Enable" mask="0x40" name="TXCIE"/>
|
|
|
|
|
<bitfield caption="USART Data register Empty Interrupt Enable" mask="0x20" name="UDRIE"/>
|
|
|
|
|
<bitfield caption="Receiver Enable" mask="0x10" name="RXEN"/>
|
|
|
|
|
<bitfield caption="Transmitter Enable" mask="0x08" name="TXEN"/>
|
|
|
|
|
<bitfield caption="Character Size" mask="0x04" name="UCSZ2"/>
|
|
|
|
|
<bitfield caption="Receive Data Bit 8" mask="0x02" name="RXB8"/>
|
|
|
|
|
<bitfield caption="Transmit Data Bit 8" mask="0x01" name="TXB8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control and Status Register C" name="UCSRC" offset="0xC2" size="1">
|
|
|
|
|
<bitfield caption="USART Mode Select" mask="0xC0" name="UMSEL" values="COMM_USART_MODE"/>
|
|
|
|
|
<bitfield caption="Parity Mode Bits" mask="0x30" name="UPM" values="COMM_UPM_PARITY_MODE"/>
|
|
|
|
|
<bitfield caption="Stop Bit Select" mask="0x08" name="USBS" values="COMM_STOP_BIT_SEL"/>
|
|
|
|
|
<bitfield caption="Character Size" mask="0x06" name="UCSZ"/>
|
|
|
|
|
<bitfield caption="Clock Polarity" mask="0x01" name="UCPOL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control and Status Register D" name="UCSRD" offset="0xC3" size="1">
|
|
|
|
|
<bitfield caption="USART RX Start Interrupt Enable" mask="0x80" name="RXSIE"/>
|
|
|
|
|
<bitfield caption="USART RX Start Flag" mask="0x40" name="RXS"/>
|
|
|
|
|
<bitfield caption="USART RX Start Frame Detection Enable" mask="0x20" name="SFDE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Baud Rate Register Bytes" name="UBRR" offset="0xC4" size="2" mask="0x0FFF"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="COMM_USART_MODE">
|
|
|
|
|
<value caption="Asynchronous Operation" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Synchronous Operation" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="COMM_UPM_PARITY_MODE">
|
|
|
|
|
<value caption="Disabled" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Enabled, Even Parity" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Enabled, Odd Parity" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="COMM_STOP_BIT_SEL">
|
|
|
|
|
<value caption="1-bit" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="2-bit" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
</value-group>
|
2021-04-04 21:04:12 +01:00
|
|
|
</module>
|
2021-06-02 23:24:05 +01:00
|
|
|
</modules>
|
2021-06-12 01:43:30 +01:00
|
|
|
<pinouts>
|
|
|
|
|
<pinout name="QFP_QFN_32">
|
|
|
|
|
<pin pad="PC2" position="1"/>
|
|
|
|
|
<pin pad="PC3" position="2"/>
|
|
|
|
|
<pin pad="PC4" position="3"/>
|
|
|
|
|
<pin pad="VCC" position="4"/>
|
|
|
|
|
<pin pad="GND" position="5"/>
|
|
|
|
|
<pin pad="PC5" position="6"/>
|
|
|
|
|
<pin pad="PC6" position="7"/>
|
|
|
|
|
<pin pad="PC7" position="8"/>
|
|
|
|
|
<pin pad="PA0" position="9"/>
|
|
|
|
|
<pin pad="PA1" position="10"/>
|
|
|
|
|
<pin pad="PA2" position="11"/>
|
|
|
|
|
<pin pad="PA3" position="12"/>
|
|
|
|
|
<pin pad="PA4" position="13"/>
|
|
|
|
|
<pin pad="PA5" position="14"/>
|
|
|
|
|
<pin pad="PA6" position="15"/>
|
|
|
|
|
<pin pad="PA7" position="16"/>
|
|
|
|
|
<pin pad="PB0" position="17"/>
|
|
|
|
|
<pin pad="AVCC" position="18"/>
|
|
|
|
|
<pin pad="PB1" position="19"/>
|
|
|
|
|
<pin pad="PB2" position="20"/>
|
|
|
|
|
<pin pad="GND" position="21"/>
|
|
|
|
|
<pin pad="PB3" position="22"/>
|
|
|
|
|
<pin pad="PB4" position="23"/>
|
|
|
|
|
<pin pad="PB5" position="24"/>
|
|
|
|
|
<pin pad="PB6" position="25"/>
|
|
|
|
|
<pin pad="PB7" position="26"/>
|
|
|
|
|
<pin pad="PD0" position="27"/>
|
|
|
|
|
<pin pad="PD1" position="28"/>
|
|
|
|
|
<pin pad="PD2" position="29"/>
|
|
|
|
|
<pin pad="PD3" position="30"/>
|
|
|
|
|
<pin pad="PC0" position="31"/>
|
|
|
|
|
<pin pad="PC1" position="32"/>
|
|
|
|
|
</pinout>
|
|
|
|
|
</pinouts>
|
2021-05-31 01:01:14 +01:00
|
|
|
</target-description-file>
|
