2021-04-04 21:04:12 +01:00
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<?xml version="1.0" encoding="UTF-8"?>
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2021-05-31 01:01:14 +01:00
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<target-description-file>
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2021-04-04 21:04:12 +01:00
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<variants>
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2023-12-13 20:40:14 +00:00
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<variant ordercode="ATXMEGA192C3-AU" package="TQFP64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0" tempmin="0" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATXMEGA192C3-MH" package="QFN64" speedmax="32000000" pinout="QFP_QFN_64" tempmax="0" tempmin="0" vccmax="3.6" vccmin="1.6"/>
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2021-04-04 21:04:12 +01:00
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</variants>
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2023-12-13 20:33:41 +00:00
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<device name="ATxmega192C3" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
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2021-06-02 23:24:05 +01:00
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<address-spaces>
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<address-space name="prog" id="prog" start="0x00000" size="0x32000" endianness="little">
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2023-12-13 20:40:14 +00:00
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<memory-segment start="0x00000" size="0x30000" type="flash" rw="RW" exec="1" name="APP_SECTION" pagesize="512"/>
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<memory-segment start="0x2E000" size="0x2000" type="flash" rw="RW" exec="1" name="APPTABLE_SECTION" pagesize="512"/>
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<memory-segment start="0x30000" size="0x2000" type="flash" rw="RW" exec="1" name="BOOT_SECTION" pagesize="512"/>
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2021-06-02 23:24:05 +01:00
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</address-space>
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<address-space name="data" id="data" start="0x0000" size="0x4000" endianness="little">
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<memory-segment start="0x0000" size="0x1000" type="io" rw="RW" exec="0" name="IO"/>
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<memory-segment start="0x1000" size="0x0800" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
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<memory-segment start="0x2000" size="0x4000" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
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</address-space>
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<address-space name="eeprom" id="eeprom" start="0x00000" size="0x0800">
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2023-12-13 20:40:14 +00:00
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<memory-segment start="0x00000" size="0x0800" type="eeprom" rw="RW" exec="0" name="EEPROM" pagesize="32"/>
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2021-06-02 23:24:05 +01:00
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</address-space>
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<address-space name="signatures" id="signatures" start="0x0000" size="0x0003">
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<memory-segment start="0x0000" size="0x0003" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
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</address-space>
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<address-space name="fuses" id="fuses" start="0x0000" size="0x0006">
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<memory-segment start="0x0000" size="0x0006" type="fuses" rw="RW" exec="0" name="FUSES"/>
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</address-space>
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<address-space name="lockbits" id="lockbits" start="0x0000" size="0x0001">
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<memory-segment start="0x0000" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
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</address-space>
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<address-space name="user_signatures" id="user_signatures" start="0x0000" size="0x0200">
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2023-12-13 20:40:14 +00:00
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<memory-segment start="0x0000" size="0x0200" type="user_signatures" rw="RW" exec="0" name="USER_SIGNATURES" pagesize="512"/>
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2021-06-02 23:24:05 +01:00
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</address-space>
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<address-space name="prod_signatures" id="prod_signatures" start="0x0000" size="0x0040">
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2023-12-13 20:40:14 +00:00
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<memory-segment start="0x0000" size="0x0040" type="other" rw="R" exec="0" name="PROD_SIGNATURES" pagesize="512"/>
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2021-06-02 23:24:05 +01:00
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</address-space>
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</address-spaces>
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<peripherals>
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<module name="GPIO" id="I6085" version="XMEGAD">
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<instance name="GPIO">
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<register-group address-space="data" offset="0x0000" name-in-module="GPIO" name="GPIO"/>
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</instance>
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</module>
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<module name="VPORT" id="I6075" version="XMEGAAU">
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<instance name="VPORT0">
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<register-group address-space="data" offset="0x0010" name-in-module="VPORT" name="VPORT0"/>
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</instance>
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<instance name="VPORT1">
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<register-group address-space="data" offset="0x0014" name-in-module="VPORT" name="VPORT1"/>
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</instance>
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<instance name="VPORT2">
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<register-group address-space="data" offset="0x0018" name-in-module="VPORT" name="VPORT2"/>
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</instance>
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<instance name="VPORT3">
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<register-group address-space="data" offset="0x001C" name-in-module="VPORT" name="VPORT3"/>
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</instance>
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</module>
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<module name="XOCD" id="I6043">
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<instance name="OCD">
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<register-group address-space="data" offset="0x002E" name-in-module="OCD" name="OCD"/>
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</instance>
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</module>
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<module name="CPU" id="I6000">
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<instance name="CPU">
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<register-group address-space="data" offset="0x0030" name-in-module="CPU" name="CPU"/>
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<parameters>
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<param name="CORE_VERSION" value="V3XJ"/>
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</parameters>
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</instance>
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</module>
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<module name="CLK" id="I6073" version="XMEGAC">
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<instance name="CLK">
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<register-group address-space="data" offset="0x0040" name-in-module="CLK" name="CLK"/>
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</instance>
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</module>
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<module name="PR" id="I6073" version="XMEGAC">
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<instance name="PR">
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<register-group address-space="data" offset="0x0070" name-in-module="PR" name="PR"/>
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</instance>
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</module>
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<module name="SLEEP" id="I6081">
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<instance name="SLEEP">
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<register-group address-space="data" offset="0x0048" name-in-module="SLEEP" name="SLEEP"/>
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</instance>
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</module>
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<module name="OSC" id="I6079" version="XMEGAAU">
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<instance name="OSC">
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<register-group address-space="data" offset="0x0050" name-in-module="OSC" name="OSC"/>
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</instance>
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</module>
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<module name="DFLL" id="I6055" version="XMEGAAU">
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<instance name="DFLLRC32M">
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<register-group address-space="data" offset="0x0060" name-in-module="DFLL" name="DFLLRC32M"/>
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</instance>
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<instance name="DFLLRC2M">
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<register-group address-space="data" offset="0x0068" name-in-module="DFLL" name="DFLLRC2M"/>
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</instance>
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</module>
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<module name="RST" id="I6083" version="XMEGAAU">
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<instance name="RST">
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<register-group address-space="data" offset="0x0078" name-in-module="RST" name="RST"/>
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</instance>
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</module>
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<module name="WDT" id="I6078">
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<instance name="WDT">
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<register-group address-space="data" offset="0x0080" name-in-module="WDT" name="WDT"/>
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</instance>
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</module>
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<module name="MCU" id="I6091" version="XMEGAD">
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<instance name="MCU">
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<register-group address-space="data" offset="0x0090" name-in-module="MCU" name="MCU"/>
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</instance>
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</module>
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<module name="PMIC" id="I6057">
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<instance name="PMIC">
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<register-group address-space="data" offset="0x00A0" name-in-module="PMIC" name="PMIC"/>
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</instance>
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</module>
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<module name="PORTCFG" id="I6075" version="XMEGAD">
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<instance name="PORTCFG">
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<register-group address-space="data" offset="0x00B0" name-in-module="PORTCFG" name="PORTCFG"/>
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</instance>
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</module>
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<module name="CRC" id="I6111" version="XMEGAD">
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<instance name="CRC">
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<register-group address-space="data" offset="0x0D0" name-in-module="CRC" name="CRC"/>
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</instance>
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</module>
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<module name="EVSYS" id="I6061" version="XMEGAC">
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<instance name="EVSYS">
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<register-group address-space="data" offset="0x0180" name-in-module="EVSYS" name="EVSYS"/>
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</instance>
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</module>
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<module name="NVM" id="I6076" version="XMEGAAU">
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<instance name="NVM">
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<register-group address-space="data" offset="0x01C0" name-in-module="NVM" name="NVM"/>
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</instance>
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</module>
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<module name="ADC" id="I6110">
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<instance name="ADCA">
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<register-group address-space="data" offset="0x0200" name-in-module="ADC" name="ADCA"/>
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</instance>
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</module>
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<module name="AC" id="I6077" version="XMEGAD">
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<instance name="ACA">
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<register-group address-space="data" offset="0x0380" name-in-module="AC" name="ACA"/>
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</instance>
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</module>
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<module name="RTC" id="I6093">
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<instance name="RTC">
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<register-group address-space="data" offset="0x0400" name-in-module="RTC" name="RTC"/>
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</instance>
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</module>
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<module name="TWI" id="I6089" version="XMEGAAU">
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<instance name="TWIC">
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<register-group address-space="data" offset="0x480" name-in-module="TWI" name="TWIC"/>
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</instance>
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<instance name="TWIE">
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<register-group address-space="data" offset="0x4A0" name-in-module="TWI" name="TWIE"/>
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</instance>
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</module>
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<module name="USB" id="I3005" version="XMEGAAU">
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<instance name="USB">
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<register-group address-space="data" offset="0x4C0" name-in-module="USB" name="USB"/>
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</instance>
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</module>
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<module name="PORT" id="I6075" version="XMEGAAU">
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<instance name="PORTA">
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<register-group address-space="data" offset="0x0600" name-in-module="PORT" name="PORTA"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTA" group="P" index="0" pad="PA0"/>
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<signal function="PORTA" group="P" index="1" pad="PA1"/>
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<signal function="PORTA" group="P" index="2" pad="PA2"/>
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<signal function="PORTA" group="P" index="3" pad="PA3"/>
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<signal function="PORTA" group="P" index="4" pad="PA4"/>
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<signal function="PORTA" group="P" index="5" pad="PA5"/>
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<signal function="PORTA" group="P" index="6" pad="PA6"/>
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<signal function="PORTA" group="P" index="7" pad="PA7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTB">
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<register-group address-space="data" offset="0x0620" name-in-module="PORT" name="PORTB"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTB" group="P" index="0" pad="PB0"/>
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<signal function="PORTB" group="P" index="1" pad="PB1"/>
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<signal function="PORTB" group="P" index="2" pad="PB2"/>
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<signal function="PORTB" group="P" index="3" pad="PB3"/>
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<signal function="PORTB" group="P" index="4" pad="PB4"/>
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<signal function="PORTB" group="P" index="5" pad="PB5"/>
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<signal function="PORTB" group="P" index="6" pad="PB6"/>
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<signal function="PORTB" group="P" index="7" pad="PB7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTC">
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<register-group address-space="data" offset="0x0640" name-in-module="PORT" name="PORTC"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTC" group="P" index="0" pad="PC0"/>
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<signal function="PORTC" group="P" index="1" pad="PC1"/>
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<signal function="PORTC" group="P" index="2" pad="PC2"/>
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<signal function="PORTC" group="P" index="3" pad="PC3"/>
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<signal function="PORTC" group="P" index="4" pad="PC4"/>
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<signal function="PORTC" group="P" index="5" pad="PC5"/>
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<signal function="PORTC" group="P" index="6" pad="PC6"/>
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<signal function="PORTC" group="P" index="7" pad="PC7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTD">
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<register-group address-space="data" offset="0x0660" name-in-module="PORT" name="PORTD"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTD" group="P" index="0" pad="PD0"/>
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<signal function="PORTD" group="P" index="1" pad="PD1"/>
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<signal function="PORTD" group="P" index="2" pad="PD2"/>
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<signal function="PORTD" group="P" index="3" pad="PD3"/>
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<signal function="PORTD" group="P" index="4" pad="PD4"/>
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<signal function="PORTD" group="P" index="5" pad="PD5"/>
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<signal function="PORTD" group="P" index="6" pad="PD6"/>
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<signal function="PORTD" group="P" index="7" pad="PD7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTE">
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<register-group address-space="data" offset="0x0680" name-in-module="PORT" name="PORTE"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTE" group="P" index="0" pad="PE0"/>
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<signal function="PORTE" group="P" index="1" pad="PE1"/>
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<signal function="PORTE" group="P" index="2" pad="PE2"/>
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<signal function="PORTE" group="P" index="3" pad="PE3"/>
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<signal function="PORTE" group="P" index="4" pad="PE4"/>
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<signal function="PORTE" group="P" index="5" pad="PE5"/>
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<signal function="PORTE" group="P" index="6" pad="PE6"/>
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<signal function="PORTE" group="P" index="7" pad="PE7"/>
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</signals>
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2021-06-02 23:24:05 +01:00
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</instance>
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<instance name="PORTF">
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<register-group address-space="data" offset="0x06A0" name-in-module="PORT" name="PORTF"/>
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2021-06-12 01:43:30 +01:00
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<signals>
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<signal function="PORTF" group="P" index="0" pad="PF0"/>
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<signal function="PORTF" group="P" index="1" pad="PF1"/>
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<signal function="PORTF" group="P" index="2" pad="PF2"/>
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<signal function="PORTF" group="P" index="3" pad="PF3"/>
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<signal function="PORTF" group="P" index="4" pad="PF4"/>
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<signal function="PORTF" group="P" index="5" pad="PF5"/>
|
|
|
|
|
<signal function="PORTF" group="P" index="6" pad="PF6"/>
|
|
|
|
|
<signal function="PORTF" group="P" index="7" pad="PF7"/>
|
|
|
|
|
</signals>
|
2021-06-02 23:24:05 +01:00
|
|
|
</instance>
|
|
|
|
|
<instance name="PORTR">
|
|
|
|
|
<register-group address-space="data" offset="0x07E0" name-in-module="PORT" name="PORTR"/>
|
2021-06-12 01:43:30 +01:00
|
|
|
<signals>
|
|
|
|
|
<signal function="PORTR" group="P" index="0" pad="PR0"/>
|
|
|
|
|
<signal function="PORTR" group="P" index="1" pad="PR1"/>
|
|
|
|
|
</signals>
|
2021-06-02 23:24:05 +01:00
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC" id="I6090" version="XMEGAD">
|
|
|
|
|
<instance name="TCC0">
|
|
|
|
|
<register-group address-space="data" offset="0x800" name-in-module="TC0" name="TCC0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCC1">
|
|
|
|
|
<register-group address-space="data" offset="0x840" name-in-module="TC1" name="TCC1"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCD0">
|
|
|
|
|
<register-group address-space="data" offset="0x900" name-in-module="TC0" name="TCD0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCE0">
|
|
|
|
|
<register-group address-space="data" offset="0xA00" name-in-module="TC0" name="TCE0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCF0">
|
|
|
|
|
<register-group address-space="data" offset="0xB00" name-in-module="TC0" name="TCF0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC2" id="I6090" version="XMEGAD">
|
|
|
|
|
<instance name="TCC2">
|
|
|
|
|
<register-group address-space="data" offset="0x800" name-in-module="TC2" name="TCC2"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCD2">
|
|
|
|
|
<register-group address-space="data" offset="0x900" name-in-module="TC2" name="TCD2"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCE2">
|
|
|
|
|
<register-group address-space="data" offset="0xA00" name-in-module="TC2" name="TCE2"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCF2">
|
|
|
|
|
<register-group address-space="data" offset="0xB00" name-in-module="TC2" name="TCF2"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="AWEX" id="I6090" version="XMEGAAU">
|
|
|
|
|
<instance name="AWEXC">
|
|
|
|
|
<register-group address-space="data" offset="0x880" name-in-module="AWEX" name="AWEXC"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="HIRES" id="I6090" version="XMEGAAU">
|
|
|
|
|
<instance name="HIRESC">
|
|
|
|
|
<register-group address-space="data" offset="0x890" name-in-module="HIRES" name="HIRESC"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="USART" id="I6090" version="XMEGAAU">
|
|
|
|
|
<instance name="USARTC0">
|
|
|
|
|
<register-group address-space="data" offset="0x8A0" name-in-module="USART" name="USARTC0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="USARTD0">
|
|
|
|
|
<register-group address-space="data" offset="0x9A0" name-in-module="USART" name="USARTD0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="USARTE0">
|
|
|
|
|
<register-group address-space="data" offset="0xAA0" name-in-module="USART" name="USARTE0"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SPI" id="I6090" version="XMEGAAU">
|
|
|
|
|
<instance name="SPIC">
|
|
|
|
|
<register-group address-space="data" offset="0x8C0" name-in-module="SPI" name="SPIC"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="SPID">
|
|
|
|
|
<register-group address-space="data" offset="0x9C0" name-in-module="SPI" name="SPID"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="IRCOM" id="I6090" version="XMEGAD">
|
|
|
|
|
<instance name="IRCOM">
|
|
|
|
|
<register-group address-space="data" offset="0x8F8" name-in-module="IRCOM" name="IRCOM"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FUSE" id="I6570" version="XMEGAD">
|
|
|
|
|
<instance name="FUSE">
|
|
|
|
|
<register-group address-space="fuses" offset="0x00" name-in-module="NVM_FUSES" name="FUSE"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="LOCKBIT" id="I6570" version="XMEGAD">
|
|
|
|
|
<instance name="LOCKBIT">
|
2023-12-13 20:40:14 +00:00
|
|
|
<register-group address-space="lockbits" offset="0x00" name-in-module="NVM_LOCKBITS" name="LOCKBIT"/>
|
2021-06-02 23:24:05 +01:00
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SIGROW" id="I3610" version="XMEGAC">
|
|
|
|
|
<instance name="PROD_SIGNATURES">
|
2023-12-13 20:40:14 +00:00
|
|
|
<register-group address-space="prod_signatures" offset="0x00" name-in-module="NVM_PROD_SIGNATURES" name="PROD_SIGNATURES"/>
|
2021-06-02 23:24:05 +01:00
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
</peripherals>
|
|
|
|
|
<interrupts>
|
|
|
|
|
<interrupt-group index="1" module-instance="OSC" name-in-module="OSC"/>
|
|
|
|
|
<interrupt-group index="2" module-instance="PORTC" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="4" module-instance="PORTR" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="10" module-instance="RTC" name-in-module="RTC"/>
|
|
|
|
|
<interrupt-group index="12" module-instance="TWIC" name-in-module="TWI"/>
|
|
|
|
|
<interrupt-group index="14" module-instance="TCC0" name-in-module="TC0"/>
|
|
|
|
|
<interrupt-group index="14" module-instance="TCC2" name-in-module="TC2"/>
|
|
|
|
|
<interrupt-group index="20" module-instance="TCC1" name-in-module="TC1"/>
|
|
|
|
|
<interrupt-group index="24" module-instance="SPIC" name-in-module="SPI"/>
|
|
|
|
|
<interrupt-group index="25" module-instance="USARTC0" name-in-module="USART"/>
|
|
|
|
|
<interrupt-group index="32" module-instance="NVM" name-in-module="NVM"/>
|
|
|
|
|
<interrupt-group index="34" module-instance="PORTB" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="43" module-instance="PORTE" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="45" module-instance="TWIE" name-in-module="TWI"/>
|
|
|
|
|
<interrupt-group index="47" module-instance="TCE0" name-in-module="TC0"/>
|
|
|
|
|
<interrupt-group index="47" module-instance="TCE2" name-in-module="TC2"/>
|
|
|
|
|
<interrupt-group index="58" module-instance="USARTE0" name-in-module="USART"/>
|
|
|
|
|
<interrupt-group index="64" module-instance="PORTD" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="66" module-instance="PORTA" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="68" module-instance="ACA" name-in-module="AC"/>
|
|
|
|
|
<interrupt-group index="71" module-instance="ADCA" name-in-module="ADC"/>
|
|
|
|
|
<interrupt-group index="77" module-instance="TCD0" name-in-module="TC0"/>
|
|
|
|
|
<interrupt-group index="77" module-instance="TCD2" name-in-module="TC2"/>
|
|
|
|
|
<interrupt-group index="87" module-instance="SPID" name-in-module="SPI"/>
|
|
|
|
|
<interrupt-group index="88" module-instance="USARTD0" name-in-module="USART"/>
|
|
|
|
|
<interrupt-group index="104" module-instance="PORTF" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="108" module-instance="TCF0" name-in-module="TC0"/>
|
|
|
|
|
<interrupt-group index="108" module-instance="TCF2" name-in-module="TC2"/>
|
|
|
|
|
<interrupt-group index="125" module-instance="USB" name-in-module="USB"/>
|
|
|
|
|
</interrupts>
|
|
|
|
|
<interfaces>
|
|
|
|
|
<interface type="pdi" name="PDI"/>
|
|
|
|
|
</interfaces>
|
|
|
|
|
<property-groups>
|
|
|
|
|
<property-group name="SIGNATURES">
|
|
|
|
|
<property name="SIGNATURE0" value="0x1E"/>
|
|
|
|
|
<property name="SIGNATURE1" value="0x97"/>
|
|
|
|
|
<property name="SIGNATURE2" value="0x51"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="PDI_INTERFACE">
|
|
|
|
|
<property name="APP_SECTION_OFFSET" value="0x00800000"/>
|
|
|
|
|
<property name="APPTABLE_SECTION_OFFSET" value="0x0082E000"/>
|
|
|
|
|
<property name="BOOT_SECTION_OFFSET" value="0x00830000"/>
|
|
|
|
|
<property name="DATAMEM_OFFSET" value="0x01000000"/>
|
|
|
|
|
<property name="EEPROM_OFFSET" value="0x008C0000"/>
|
|
|
|
|
<property name="USER_SIGNATURES_OFFSET" value="0x008E0400"/>
|
|
|
|
|
<property name="PROD_SIGNATURES_OFFSET" value="0x008E0200"/>
|
|
|
|
|
<property name="FUSE_REGISTERS_OFFSET" value="0x008F0020"/>
|
|
|
|
|
<property name="LOCK_REGISTERS_OFFSET" value="0x008F0027"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
</property-groups>
|
|
|
|
|
</device>
|
2021-04-04 21:04:12 +01:00
|
|
|
<modules>
|
|
|
|
|
<module name="GPIO" id="I6085" version="XMEGAD" caption="General Purpose IO">
|
|
|
|
|
<register-group caption="General Purpose IO Registers" name="GPIO" size="4">
|
|
|
|
|
<register caption="General Purpose IO Register 0" name="GPIOR0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 1" name="GPIOR1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 2" name="GPIOR2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 3" name="GPIOR3" offset="0x03" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="VPORT" id="I6075" version="XMEGAAU" caption="Virtual Ports">
|
|
|
|
|
<register-group caption="Virtual Port" name="VPORT" size="4">
|
|
|
|
|
<register caption="I/O Port Data Direction" name="DIR" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output" name="OUT" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="I/O Port Input" name="IN" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Port Interrupt 1 Flag" mask="0x02" name="INT1IF"/>
|
|
|
|
|
<bitfield caption="Port Interrupt 0 Flag" mask="0x01" name="INT0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="XOCD" caption="On-Chip Debug System" id="I6043">
|
|
|
|
|
<register-group name="OCD" caption="On-Chip Debug System" size="2">
|
|
|
|
|
<register name="OCDR0" caption="OCD Register 0" size="1" offset="0x00">
|
|
|
|
|
<bitfield name="OCDRD" caption="OCDR Dirty" mask="0xFF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="OCDR1" caption="OCD Register 1" size="1" offset="0x01">
|
|
|
|
|
<bitfield name="OCDRD" caption="OCDR Dirty" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CPU" id="I6000" caption="CPU">
|
|
|
|
|
<register-group caption="CPU registerMap" name="CPU" size="16">
|
|
|
|
|
<register caption="Configuration Change Protection" name="CCP" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="CCP signature" mask="0xFF" name="CCP" values="CCP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Ramp D" name="RAMPD" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Ramp X" name="RAMPX" offset="0x09" size="1"/>
|
|
|
|
|
<register caption="Ramp Y" name="RAMPY" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Ramp Z" name="RAMPZ" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Extended Indirect Jump" name="EIND" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Stack Pointer Low" name="SPL" offset="0x0D" size="1"/>
|
|
|
|
|
<register caption="Stack Pointer High" name="SPH" offset="0x0E" size="1"/>
|
|
|
|
|
<register caption="Status Register" name="SREG" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="Global Interrupt Enable Flag" mask="0x80" name="I"/>
|
|
|
|
|
<bitfield caption="Transfer Bit" mask="0x40" name="T"/>
|
|
|
|
|
<bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
|
|
|
|
|
<bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S"/>
|
|
|
|
|
<bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
|
|
|
|
|
<bitfield caption="Negative Flag" mask="0x04" name="N"/>
|
|
|
|
|
<bitfield caption="Zero Flag" mask="0x02" name="Z"/>
|
|
|
|
|
<bitfield caption="Carry Flag" mask="0x01" name="C"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="CCP signatures" name="CCP">
|
|
|
|
|
<value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
|
|
|
|
|
<value caption="IO Register Protection" name="IOREG" value="0xD8"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CLK" id="I6073" version="XMEGAC" caption="Clock System">
|
|
|
|
|
<register-group caption="Clock System" name="CLK" size="5">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="System Clock Selection" mask="0x07" name="SCLKSEL" values="CLK_SCLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Prescaler Control Register" name="PSCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Prescaler A Division Factor" mask="0x7C" name="PSADIV" values="CLK_PSADIV"/>
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Prescaler B and C Division factor" mask="0x03" name="PSBCDIV" values="CLK_PSBCDIV"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Lock register" name="LOCK" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Clock System Lock" mask="0x01" name="LOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="RTC Control Register" name="RTCCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Clock Source" mask="0x0E" name="RTCSRC" values="CLK_RTCSRC"/>
|
|
|
|
|
<bitfield caption="Clock Source Enable" mask="0x01" name="RTCEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USB Control Register" name="USBCTRL" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Prescaler Division Factor" mask="0x38" name="USBPSDIV" values="CLK_USBPSDIV"/>
|
|
|
|
|
<bitfield caption="Clock Source" mask="0x06" name="USBSRC" values="CLK_USBSRC"/>
|
|
|
|
|
<bitfield caption="Clock Source Enable" mask="0x01" name="USBSEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="System Clock Selection" name="CLK_SCLKSEL">
|
|
|
|
|
<value caption="Internal 2 MHz RC Oscillator" name="RC2M" value="0x00"/>
|
|
|
|
|
<value caption="Internal 32 MHz RC Oscillator" name="RC32M" value="0x01"/>
|
|
|
|
|
<value caption="Internal 32.768 kHz RC Oscillator" name="RC32K" value="0x02"/>
|
|
|
|
|
<value caption="External Crystal Oscillator or Clock" name="XOSC" value="0x03"/>
|
|
|
|
|
<value caption="Phase Locked Loop" name="PLL" value="0x04"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler A Division Factor" name="CLK_PSADIV">
|
|
|
|
|
<value caption="Divide by 1" name="1" value="0x00"/>
|
|
|
|
|
<value caption="Divide by 2" name="2" value="0x01"/>
|
|
|
|
|
<value caption="Divide by 4" name="4" value="0x03"/>
|
|
|
|
|
<value caption="Divide by 8" name="8" value="0x05"/>
|
|
|
|
|
<value caption="Divide by 16" name="16" value="0x07"/>
|
|
|
|
|
<value caption="Divide by 32" name="32" value="0x09"/>
|
|
|
|
|
<value caption="Divide by 64" name="64" value="0x0B"/>
|
|
|
|
|
<value caption="Divide by 128" name="128" value="0x0D"/>
|
|
|
|
|
<value caption="Divide by 256" name="256" value="0x0F"/>
|
|
|
|
|
<value caption="Divide by 512" name="512" value="0x11"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler B and C Division Factor" name="CLK_PSBCDIV">
|
|
|
|
|
<value caption="Divide B by 1 and C by 1" name="1_1" value="0x00"/>
|
|
|
|
|
<value caption="Divide B by 1 and C by 2" name="1_2" value="0x01"/>
|
|
|
|
|
<value caption="Divide B by 4 and C by 1" name="4_1" value="0x02"/>
|
|
|
|
|
<value caption="Divide B by 2 and C by 2" name="2_2" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="RTC Clock Source" name="CLK_RTCSRC">
|
|
|
|
|
<value caption="1.024 kHz from internal 32kHz ULP" name="ULP" value="0x00"/>
|
|
|
|
|
<value caption="1.024 kHz from 32.768 kHz crystal oscillator on TOSC" name="TOSC" value="0x01"/>
|
|
|
|
|
<value caption="1.024 kHz from internal 32.768 kHz RC oscillator" name="RCOSC" value="0x02"/>
|
|
|
|
|
<value caption="32.768 kHz from 32.768 kHz crystal oscillator on TOSC" name="TOSC32" value="0x05"/>
|
|
|
|
|
<value caption="32.768 kHz from internal 32.768 kHz RC oscillator" name="RCOSC32" value="0x06"/>
|
|
|
|
|
<value caption="External Clock from TOSC1" name="EXTCLK" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="USB Prescaler Division Factor" name="CLK_USBPSDIV">
|
|
|
|
|
<value caption="Divide by 1" name="1" value="0x00"/>
|
|
|
|
|
<value caption="Divide by 2" name="2" value="0x01"/>
|
|
|
|
|
<value caption="Divide by 4" name="4" value="0x02"/>
|
|
|
|
|
<value caption="Divide by 8" name="8" value="0x03"/>
|
|
|
|
|
<value caption="Divide by 16" name="16" value="0x04"/>
|
|
|
|
|
<value caption="Divide by 32" name="32" value="0x05"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="USB Clock Source" name="CLK_USBSRC">
|
|
|
|
|
<value caption="PLL" name="PLL" value="0x00"/>
|
|
|
|
|
<value caption="Internal 32 MHz RC Oscillator" name="RC32M" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PR" id="I6073" version="XMEGAC" caption="Power Reduction">
|
|
|
|
|
<register-group caption="Power Reduction" name="PR" size="7">
|
|
|
|
|
<register caption="General Power Reduction" name="PRGEN" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="USB" mask="0x40" name="USB"/>
|
|
|
|
|
<bitfield caption="AES" mask="0x10" name="AES"/>
|
|
|
|
|
<bitfield caption="Real-time Counter" mask="0x04" name="RTC"/>
|
|
|
|
|
<bitfield caption="Event System" mask="0x02" name="EVSYS"/>
|
|
|
|
|
<bitfield caption="DMA-Controller" mask="0x01" name="DMA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port A" name="PRPA" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Port A ADC" mask="0x02" name="ADC"/>
|
|
|
|
|
<bitfield caption="Port A Analog Comparator" mask="0x01" name="AC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port C" name="PRPC" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Port C Two-wire Interface" mask="0x40" name="TWI"/>
|
|
|
|
|
<bitfield caption="Port C USART1" mask="0x20" name="USART1"/>
|
|
|
|
|
<bitfield caption="Port C USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port C SPI" mask="0x08" name="SPI"/>
|
|
|
|
|
<bitfield caption="Port C AWEX" mask="0x04" name="HIRES"/>
|
|
|
|
|
<bitfield caption="Port C Timer/Counter1" mask="0x02" name="TC1"/>
|
|
|
|
|
<bitfield caption="Port C Timer/Counter0" mask="0x01" name="TC0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port D" name="PRPD" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Port D USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port D SPI" mask="0x08" name="SPI"/>
|
|
|
|
|
<bitfield caption="Port D Timer/Counter0" mask="0x01" name="TC0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port E" name="PRPE" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Port E Two-wire Interface" mask="0x40" name="TWI"/>
|
|
|
|
|
<bitfield caption="Port E USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port E Timer/Counter0" mask="0x01" name="TC0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port F" name="PRPF" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Port F USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port F Timer/Counter0" mask="0x01" name="TC0"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SLEEP" id="I6081" caption="Sleep Controller">
|
|
|
|
|
<register-group caption="Sleep Controller" name="SLEEP" size="1">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Sleep Mode" mask="0x0E" name="SMODE" values="SLEEP_SMODE"/>
|
|
|
|
|
<bitfield caption="Sleep Enable" mask="0x01" name="SEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Sleep Mode" name="SLEEP_SMODE">
|
|
|
|
|
<value caption="Idle mode" name="IDLE" value="0x00"/>
|
|
|
|
|
<value caption="Power-down Mode" name="PDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Power-save Mode" name="PSAVE" value="0x03"/>
|
|
|
|
|
<value caption="Standby Mode" name="STDBY" value="0x06"/>
|
|
|
|
|
<value caption="Extended Standby Mode" name="ESTDBY" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="OSC" id="I6079" version="XMEGAAU" caption="Oscillator">
|
|
|
|
|
<register-group caption="Oscillator" name="OSC" size="7">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="PLL Enable" mask="0x10" name="PLLEN"/>
|
|
|
|
|
<bitfield caption="External Oscillator Enable" mask="0x08" name="XOSCEN"/>
|
|
|
|
|
<bitfield caption="Internal 32.768 kHz RC Oscillator Enable" mask="0x04" name="RC32KEN"/>
|
|
|
|
|
<bitfield caption="Internal 32 MHz RC Oscillator Enable" mask="0x02" name="RC32MEN"/>
|
|
|
|
|
<bitfield caption="Internal 2 MHz RC Oscillator Enable" mask="0x01" name="RC2MEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="PLL Ready" mask="0x10" name="PLLRDY"/>
|
|
|
|
|
<bitfield caption="External Oscillator Ready" mask="0x08" name="XOSCRDY"/>
|
|
|
|
|
<bitfield caption="Internal 32.768 kHz RC Oscillator Ready" mask="0x04" name="RC32KRDY"/>
|
|
|
|
|
<bitfield caption="Internal 32 MHz RC Oscillator Ready" mask="0x02" name="RC32MRDY"/>
|
|
|
|
|
<bitfield caption="Internal 2 MHz RC Oscillator Ready" mask="0x01" name="RC2MRDY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Oscillator Control Register" name="XOSCCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Frequency Range" mask="0xC0" name="FRQRANGE" values="OSC_FRQRANGE"/>
|
|
|
|
|
<bitfield caption="32.768 kHz XTAL OSC Low-power Mode" mask="0x20" name="X32KLPM"/>
|
|
|
|
|
<bitfield caption="16 MHz Crystal Oscillator High Power mode" mask="0x10" name="XOSCPWR"/>
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="External Oscillator Selection and Startup Time" mask="0x0F" name="XOSCSEL" values="OSC_XOSCSEL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Failure Detection Register" name="XOSCFAIL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="PLL Failure Detection Interrupt Flag" mask="0x08" name="PLLFDIF"/>
|
|
|
|
|
<bitfield caption="PLL Failure Detection Enable" mask="0x04" name="PLLFDEN"/>
|
|
|
|
|
<bitfield caption="XOSC Failure Detection Interrupt Flag" mask="0x02" name="XOSCFDIF"/>
|
|
|
|
|
<bitfield caption="XOSC Failure Detection Enable" mask="0x01" name="XOSCFDEN"/>
|
|
|
|
|
</register>
|
2023-12-13 20:40:14 +00:00
|
|
|
<register caption="32.768 kHz Internal Oscillator Calibration Register" name="RC32KCAL" offset="0x04" size="1"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<register caption="PLL Control Register" name="PLLCTRL" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Clock Source" mask="0xC0" name="PLLSRC" values="OSC_PLLSRC"/>
|
|
|
|
|
<bitfield caption="Divide by 2" mask="0x20" name="PLLDIV"/>
|
|
|
|
|
<bitfield caption="Multiplication Factor" mask="0x1F" name="PLLFAC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="DFLL Control Register" name="DFLLCTRL" offset="0x06" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="32 MHz DFLL Calibration Reference" mask="0x06" name="RC32MCREF" values="OSC_RC32MCREF"/>
|
|
|
|
|
<bitfield caption="2 MHz DFLL Calibration Reference" mask="0x01" name="RC2MCREF" values="OSC_RC2MCREF"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Oscillator Frequency Range" name="OSC_FRQRANGE">
|
|
|
|
|
<value caption="0.4 - 2 MHz" name="04TO2" value="0x00"/>
|
|
|
|
|
<value caption="2 - 9 MHz" name="2TO9" value="0x01"/>
|
|
|
|
|
<value caption="9 - 12 MHz" name="9TO12" value="0x02"/>
|
|
|
|
|
<value caption="12 - 16 MHz" name="12TO16" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="External Oscillator Selection and Startup Time" name="OSC_XOSCSEL">
|
|
|
|
|
<value caption="External Clock - 6 CLK" name="EXTCLK" value="0x00"/>
|
|
|
|
|
<value caption="32.768 kHz TOSC - 32K CLK" name="32KHz" value="0x02"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 256 CLK" name="XTAL_256CLK" value="0x03"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 1K CLK" name="XTAL_1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 16K CLK" name="XTAL_16KCLK" value="0x0B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="PLL Clock Source" name="OSC_PLLSRC">
|
|
|
|
|
<value caption="Internal 2 MHz RC Oscillator" name="RC2M" value="0x00"/>
|
|
|
|
|
<value caption="Internal 32 MHz RC Oscillator" name="RC32M" value="0x02"/>
|
|
|
|
|
<value caption="External Oscillator" name="XOSC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="2 MHz DFLL Calibration Reference" name="OSC_RC2MCREF">
|
|
|
|
|
<value caption="Internal 32.768 kHz RC Oscillator" name="RC32K" value="0x00"/>
|
|
|
|
|
<value caption="External 32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="32 MHz DFLL Calibration Reference" name="OSC_RC32MCREF">
|
|
|
|
|
<value caption="Internal 32.768 kHz RC Oscillator" name="RC32K" value="0x00"/>
|
|
|
|
|
<value caption="External 32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x01"/>
|
|
|
|
|
<value caption="USB Start of Frame" name="USBSOF" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="OSC">
|
|
|
|
|
<interrupt index="0" name="OSCF" caption="Oscillator Failure Interrupt (NMI)"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="DFLL" id="I6055" version="XMEGAAU" caption="DFLL">
|
|
|
|
|
<register-group caption="DFLL" name="DFLL" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="DFLL Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Register A" name="CALA" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="DFLL Calibration Value A" mask="0x7F" name="CALL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Register B" name="CALB" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="DFLL Calibration Value B" mask="0x3F" name="CALH"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Compare Register 0" name="COMP0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Oscillator Compare Register 1" name="COMP1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Oscillator Compare Register 2" name="COMP2" offset="0x06" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="RST" id="I6083" version="XMEGAAU" caption="Reset">
|
|
|
|
|
<register-group caption="Reset" name="RST" size="2">
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Spike Detection Reset Flag" mask="0x40" name="SDRF"/>
|
|
|
|
|
<bitfield caption="Software Reset Flag" mask="0x20" name="SRF"/>
|
|
|
|
|
<bitfield caption="Programming and Debug Interface Interface Reset Flag" mask="0x10" name="PDIRF"/>
|
|
|
|
|
<bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
|
|
|
|
|
<bitfield caption="Brown-out Reset Flag" mask="0x04" name="BORF"/>
|
|
|
|
|
<bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
|
|
|
|
|
<bitfield caption="Power-on Reset Flag" mask="0x01" name="PORF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Software Reset" mask="0x01" name="SWRST"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="WDT" id="I6078" caption="Watch-Dog Timer">
|
|
|
|
|
<register-group caption="Watch-Dog Timer" name="WDT" size="3">
|
|
|
|
|
<register caption="Control" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Period" mask="0x3C" name="PER" values="WDT_PER"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x02" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Change Enable" mask="0x01" name="CEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Windowed Mode Control" name="WINCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Windowed Mode Period" mask="0x3C" name="WPER" values="WDT_WPER"/>
|
|
|
|
|
<bitfield caption="Windowed Mode Enable" mask="0x02" name="WEN"/>
|
|
|
|
|
<bitfield caption="Windowed Mode Change Enable" mask="0x01" name="WCEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Syncronization busy" mask="0x01" name="SYNCBUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Period setting" name="WDT_PER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.128s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.256s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.512s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Closed window period" name="WDT_WPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.128s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.256s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.512s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="MCU" id="I6091" version="XMEGAD" caption="MCU Control">
|
|
|
|
|
<register-group caption="MCU Control" name="MCU" size="12">
|
|
|
|
|
<register caption="Device ID byte 0" name="DEVID0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Device ID byte 1" name="DEVID1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="Device ID byte 2" name="DEVID2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Revision ID" name="REVID" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Analog Startup Delay" name="ANAINIT" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Analog startup delay Port A" mask="0x03" name="STARTUPDLYA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event System Lock" name="EVSYSLOCK" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 0-3 Lock" mask="0x01" name="EVSYS0LOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="AWEX Lock" name="AWEXLOCK" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="AWeX on T/C C0 Lock" mask="0x01" name="AWEXCLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PMIC" caption="Programmable Multi-level Interrupt Controller" id="I6057">
|
|
|
|
|
<register-group name="PMIC" caption="Programmable Multi-level Interrupt Controller" size="16">
|
|
|
|
|
<register name="STATUS" caption="Status Register" size="1" offset="0x00">
|
|
|
|
|
<bitfield name="NMIEX" caption="Non-maskable Interrupt Executing" mask="0x80"/>
|
|
|
|
|
<bitfield name="HILVLEX" caption="High Level Interrupt Executing" mask="0x04"/>
|
|
|
|
|
<bitfield name="MEDLVLEX" caption="Medium Level Interrupt Executing" mask="0x02"/>
|
|
|
|
|
<bitfield name="LOLVLEX" caption="Low Level Interrupt Executing" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="INTPRI" caption="Interrupt Priority" size="1" offset="0x01">
|
|
|
|
|
<bitfield name="INTPRI" caption="Interrupt Priority" mask="0xFF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="CTRL" caption="Control Register" size="1" offset="0x02">
|
|
|
|
|
<bitfield name="RREN" caption="Round-Robin Priority Enable" mask="0x80"/>
|
|
|
|
|
<bitfield name="IVSEL" caption="Interrupt Vector Select" mask="0x40"/>
|
|
|
|
|
<bitfield name="HILVLEN" caption="High Level Enable" mask="0x04"/>
|
|
|
|
|
<bitfield name="MEDLVLEN" caption="Medium Level Enable" mask="0x02"/>
|
|
|
|
|
<bitfield name="LOLVLEN" caption="Low Level Enable" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PORTCFG" id="I6075" version="XMEGAD" caption="Port Configuration">
|
|
|
|
|
<register-group caption="I/O port Configuration" name="PORTCFG" size="7">
|
|
|
|
|
<register caption="Multi-pin Configuration Mask" name="MPCMASK" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Virtual Port Control Register A" name="VPCTRLA" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Virtual Port 1 Mapping" mask="0xF0" name="VP1MAP" values="PORTCFG_VP13MAP"/>
|
|
|
|
|
<bitfield caption="Virtual Port 0 Mapping" mask="0x0F" name="VP0MAP" values="PORTCFG_VP02MAP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Virtual Port Control Register B" name="VPCTRLB" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Virtual Port 3 Mapping" mask="0xF0" name="VP3MAP" values="PORTCFG_VP13MAP"/>
|
|
|
|
|
<bitfield caption="Virtual Port 2 Mapping" mask="0x0F" name="VP2MAP" values="PORTCFG_VP02MAP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Clock and Event Out Register" name="CLKEVOUT" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Peripheral Clock Output Port" mask="0x03" name="CLKOUT" values="PORTCFG_CLKOUT"/>
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Peripheral Clock Output Select" mask="0x0C" name="CLKOUTSEL" values="PORTCFG_CLKOUTSEL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Event Output Port" mask="0x30" name="EVOUT" values="PORTCFG_EVOUT"/>
|
|
|
|
|
<bitfield caption="RTC Clock Output" mask="0x40" name="RTCOUT"/>
|
|
|
|
|
<bitfield caption="Peripheral Clock and Event Output pin Select" mask="0x80" name="CLKEVPIN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Output Select" name="EVOUTSEL" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Event Output Select" mask="0x07" name="EVOUTSEL" values="PORTCFG_EVOUTSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Virtual Port Mapping" name="PORTCFG_VP02MAP">
|
|
|
|
|
<value caption="Mapped To PORTA" name="PORTA" value="0x00"/>
|
|
|
|
|
<value caption="Mapped To PORTB" name="PORTB" value="0x01"/>
|
|
|
|
|
<value caption="Mapped To PORTC" name="PORTC" value="0x02"/>
|
|
|
|
|
<value caption="Mapped To PORTD" name="PORTD" value="0x03"/>
|
|
|
|
|
<value caption="Mapped To PORTE" name="PORTE" value="0x04"/>
|
|
|
|
|
<value caption="Mapped To PORTF" name="PORTF" value="0x05"/>
|
|
|
|
|
<value caption="Mapped To PORTG" name="PORTG" value="0x06"/>
|
|
|
|
|
<value caption="Mapped To PORTH" name="PORTH" value="0x07"/>
|
|
|
|
|
<value caption="Mapped To PORTJ" name="PORTJ" value="0x08"/>
|
|
|
|
|
<value caption="Mapped To PORTK" name="PORTK" value="0x09"/>
|
|
|
|
|
<value caption="Mapped To PORTL" name="PORTL" value="0x0A"/>
|
|
|
|
|
<value caption="Mapped To PORTM" name="PORTM" value="0x0B"/>
|
|
|
|
|
<value caption="Mapped To PORTN" name="PORTN" value="0x0C"/>
|
|
|
|
|
<value caption="Mapped To PORTP" name="PORTP" value="0x0D"/>
|
|
|
|
|
<value caption="Mapped To PORTQ" name="PORTQ" value="0x0E"/>
|
|
|
|
|
<value caption="Mapped To PORTR" name="PORTR" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Virtual Port Mapping" name="PORTCFG_VP13MAP">
|
|
|
|
|
<value caption="Mapped To PORTA" name="PORTA" value="0x00"/>
|
|
|
|
|
<value caption="Mapped To PORTB" name="PORTB" value="0x01"/>
|
|
|
|
|
<value caption="Mapped To PORTC" name="PORTC" value="0x02"/>
|
|
|
|
|
<value caption="Mapped To PORTD" name="PORTD" value="0x03"/>
|
|
|
|
|
<value caption="Mapped To PORTE" name="PORTE" value="0x04"/>
|
|
|
|
|
<value caption="Mapped To PORTF" name="PORTF" value="0x05"/>
|
|
|
|
|
<value caption="Mapped To PORTG" name="PORTG" value="0x06"/>
|
|
|
|
|
<value caption="Mapped To PORTH" name="PORTH" value="0x07"/>
|
|
|
|
|
<value caption="Mapped To PORTJ" name="PORTJ" value="0x08"/>
|
|
|
|
|
<value caption="Mapped To PORTK" name="PORTK" value="0x09"/>
|
|
|
|
|
<value caption="Mapped To PORTL" name="PORTL" value="0x0A"/>
|
|
|
|
|
<value caption="Mapped To PORTM" name="PORTM" value="0x0B"/>
|
|
|
|
|
<value caption="Mapped To PORTN" name="PORTN" value="0x0C"/>
|
|
|
|
|
<value caption="Mapped To PORTP" name="PORTP" value="0x0D"/>
|
|
|
|
|
<value caption="Mapped To PORTQ" name="PORTQ" value="0x0E"/>
|
|
|
|
|
<value caption="Mapped To PORTR" name="PORTR" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="System Clock Output Port" name="PORTCFG_CLKOUT">
|
|
|
|
|
<value caption="System Clock Output Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock Output on Port C pin 7" name="PC7" value="0x01"/>
|
|
|
|
|
<value caption="System Clock Output on Port D pin 7" name="PD7" value="0x02"/>
|
|
|
|
|
<value caption="System Clock Output on Port E pin 7" name="PE7" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Peripheral Clock Output Select" name="PORTCFG_CLKOUTSEL">
|
|
|
|
|
<value caption="1x Peripheral Clock Output to pin" name="CLK1X" value="0x00"/>
|
|
|
|
|
<value caption="2x Peripheral Clock Output to pin" name="CLK2X" value="0x01"/>
|
|
|
|
|
<value caption="4x Peripheral Clock Output to pin" name="CLK4X" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Output Port" name="PORTCFG_EVOUT">
|
|
|
|
|
<value caption="Event Output Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 7 Output on Port C pin 7" name="PC7" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 7 Output on Port D pin 7" name="PD7" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 7 Output on Port E pin 7" name="PE7" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Output Select" name="PORTCFG_EVOUTSEL">
|
|
|
|
|
<value caption="Event Channel 0 output to pin" name="0" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 1 output to pin" name="1" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 2 output to pin" name="2" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 3 output to pin" name="3" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CRC" id="I6111" version="XMEGAD" caption="Cyclic Redundancy Checker">
|
|
|
|
|
<register-group caption="Cyclic Redundancy Checker" name="CRC" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Reset" mask="0xC0" name="RESET" values="CRC_RESET"/>
|
|
|
|
|
<bitfield caption="CRC Mode" mask="0x20" name="CRC32"/>
|
|
|
|
|
<bitfield caption="Input Source" mask="0x0F" name="SOURCE" values="CRC_SOURCE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Zero detection" mask="0x02" name="ZERO"/>
|
|
|
|
|
<bitfield caption="Busy" mask="0x01" name="BUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Data Input" name="DATAIN" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 0" name="CHECKSUM0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 1" name="CHECKSUM1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 2" name="CHECKSUM2" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 3" name="CHECKSUM3" offset="0x07" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Reset" name="CRC_RESET">
|
|
|
|
|
<value caption="No Reset" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Reset CRC with CHECKSUM to all zeros" name="RESET0" value="0x02"/>
|
|
|
|
|
<value caption="Reset CRC with CHECKSUM to all ones" name="RESET1" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input Source" name="CRC_SOURCE">
|
|
|
|
|
<value caption="Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="I/O Interface" name="IO" value="0x01"/>
|
|
|
|
|
<value caption="Flash" name="FLASH" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="EVSYS" id="I6061" version="XMEGAC" caption="Event System">
|
|
|
|
|
<register-group caption="Event System" name="EVSYS" size="18">
|
|
|
|
|
<register caption="Event Channel 0 Multiplexer" name="CH0MUX" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 0 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 1 Multiplexer" name="CH1MUX" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 1 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 2 Multiplexer" name="CH2MUX" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 2 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 3 Multiplexer" name="CH3MUX" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 3 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 0 Control Register" name="CH0CTRL" offset="0x08" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Quadrature Decoder Index Recognition Mode" mask="0x60" name="QDIRM" values="EVSYS_QDIRM"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Quadrature Decoder Index Enable" mask="0x10" name="QDIEN"/>
|
|
|
|
|
<bitfield caption="Quadrature Decoder Enable" mask="0x08" name="QDEN"/>
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 1 Control Register" name="CH1CTRL" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 2 Control Register" name="CH2CTRL" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 3 Control Register" name="CH3CTRL" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Strobe" name="STROBE" offset="0x10" size="1"/>
|
|
|
|
|
<register caption="Event Data" name="DATA" offset="0x11" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Quadrature Decoder Index Recognition Mode" name="EVSYS_QDIRM">
|
|
|
|
|
<value caption="QDPH0 = 0, QDPH90 = 0" name="00" value="0x00"/>
|
|
|
|
|
<value caption="QDPH0 = 0, QDPH90 = 1" name="01" value="0x01"/>
|
|
|
|
|
<value caption="QDPH0 = 1, QDPH90 = 0" name="10" value="0x02"/>
|
|
|
|
|
<value caption="QDPH0 = 1, QDPH90 = 1" name="11" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Digital filter coefficient" name="EVSYS_DIGFILT">
|
|
|
|
|
<value caption="1 SAMPLE" name="1SAMPLE" value="0x00"/>
|
|
|
|
|
<value caption="2 SAMPLES" name="2SAMPLES" value="0x01"/>
|
|
|
|
|
<value caption="3 SAMPLES" name="3SAMPLES" value="0x02"/>
|
|
|
|
|
<value caption="4 SAMPLES" name="4SAMPLES" value="0x03"/>
|
|
|
|
|
<value caption="5 SAMPLES" name="5SAMPLES" value="0x04"/>
|
|
|
|
|
<value caption="6 SAMPLES" name="6SAMPLES" value="0x05"/>
|
|
|
|
|
<value caption="7 SAMPLES" name="7SAMPLES" value="0x06"/>
|
|
|
|
|
<value caption="8 SAMPLES" name="8SAMPLES" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Channel multiplexer input selection" name="EVSYS_CHMUX">
|
|
|
|
|
<value caption="Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="RTC Overflow" name="RTC_OVF" value="0x08"/>
|
|
|
|
|
<value caption="RTC Compare Match" name="RTC_CMP" value="0x09"/>
|
|
|
|
|
<value caption="USB Setup, SOF, CRC error and UNF/OVF" name="USB" value="0x0A"/>
|
|
|
|
|
<value caption="Analog Comparator A Channel 0" name="ACA_CH0" value="0x10"/>
|
|
|
|
|
<value caption="Analog Comparator A Channel 1" name="ACA_CH1" value="0x11"/>
|
|
|
|
|
<value caption="Analog Comparator A Window" name="ACA_WIN" value="0x12"/>
|
|
|
|
|
<value caption="ADC A Channel" name="ADCA_CH0" value="0x20"/>
|
|
|
|
|
<value caption="Port A, Pin0" name="PORTA_PIN0" value="0x50"/>
|
|
|
|
|
<value caption="Port A, Pin1" name="PORTA_PIN1" value="0x51"/>
|
|
|
|
|
<value caption="Port A, Pin2" name="PORTA_PIN2" value="0x52"/>
|
|
|
|
|
<value caption="Port A, Pin3" name="PORTA_PIN3" value="0x53"/>
|
|
|
|
|
<value caption="Port A, Pin4" name="PORTA_PIN4" value="0x54"/>
|
|
|
|
|
<value caption="Port A, Pin5" name="PORTA_PIN5" value="0x55"/>
|
|
|
|
|
<value caption="Port A, Pin6" name="PORTA_PIN6" value="0x56"/>
|
|
|
|
|
<value caption="Port A, Pin7" name="PORTA_PIN7" value="0x57"/>
|
|
|
|
|
<value caption="Port B, Pin0" name="PORTB_PIN0" value="0x58"/>
|
|
|
|
|
<value caption="Port B, Pin1" name="PORTB_PIN1" value="0x59"/>
|
|
|
|
|
<value caption="Port B, Pin2" name="PORTB_PIN2" value="0x5A"/>
|
|
|
|
|
<value caption="Port B, Pin3" name="PORTB_PIN3" value="0x5B"/>
|
|
|
|
|
<value caption="Port B, Pin4" name="PORTB_PIN4" value="0x5C"/>
|
|
|
|
|
<value caption="Port B, Pin5" name="PORTB_PIN5" value="0x5D"/>
|
|
|
|
|
<value caption="Port B, Pin6" name="PORTB_PIN6" value="0x5E"/>
|
|
|
|
|
<value caption="Port B, Pin7" name="PORTB_PIN7" value="0x5F"/>
|
|
|
|
|
<value caption="Port C, Pin0" name="PORTC_PIN0" value="0x60"/>
|
|
|
|
|
<value caption="Port C, Pin1" name="PORTC_PIN1" value="0x61"/>
|
|
|
|
|
<value caption="Port C, Pin2" name="PORTC_PIN2" value="0x62"/>
|
|
|
|
|
<value caption="Port C, Pin3" name="PORTC_PIN3" value="0x63"/>
|
|
|
|
|
<value caption="Port C, Pin4" name="PORTC_PIN4" value="0x64"/>
|
|
|
|
|
<value caption="Port C, Pin5" name="PORTC_PIN5" value="0x65"/>
|
|
|
|
|
<value caption="Port C, Pin6" name="PORTC_PIN6" value="0x66"/>
|
|
|
|
|
<value caption="Port C, Pin7" name="PORTC_PIN7" value="0x67"/>
|
|
|
|
|
<value caption="Port D, Pin0" name="PORTD_PIN0" value="0x68"/>
|
|
|
|
|
<value caption="Port D, Pin1" name="PORTD_PIN1" value="0x69"/>
|
|
|
|
|
<value caption="Port D, Pin2" name="PORTD_PIN2" value="0x6A"/>
|
|
|
|
|
<value caption="Port D, Pin3" name="PORTD_PIN3" value="0x6B"/>
|
|
|
|
|
<value caption="Port D, Pin4" name="PORTD_PIN4" value="0x6C"/>
|
|
|
|
|
<value caption="Port D, Pin5" name="PORTD_PIN5" value="0x6D"/>
|
|
|
|
|
<value caption="Port D, Pin6" name="PORTD_PIN6" value="0x6E"/>
|
|
|
|
|
<value caption="Port D, Pin7" name="PORTD_PIN7" value="0x6F"/>
|
|
|
|
|
<value caption="Port E, Pin0" name="PORTE_PIN0" value="0x70"/>
|
|
|
|
|
<value caption="Port E, Pin1" name="PORTE_PIN1" value="0x71"/>
|
|
|
|
|
<value caption="Port E, Pin2" name="PORTE_PIN2" value="0x72"/>
|
|
|
|
|
<value caption="Port E, Pin3" name="PORTE_PIN3" value="0x73"/>
|
|
|
|
|
<value caption="Port E, Pin4" name="PORTE_PIN4" value="0x74"/>
|
|
|
|
|
<value caption="Port E, Pin5" name="PORTE_PIN5" value="0x75"/>
|
|
|
|
|
<value caption="Port E, Pin6" name="PORTE_PIN6" value="0x76"/>
|
|
|
|
|
<value caption="Port E, Pin7" name="PORTE_PIN7" value="0x77"/>
|
|
|
|
|
<value caption="Port F, Pin0" name="PORTF_PIN0" value="0x78"/>
|
|
|
|
|
<value caption="Port F, Pin1" name="PORTF_PIN1" value="0x79"/>
|
|
|
|
|
<value caption="Port F, Pin2" name="PORTF_PIN2" value="0x7A"/>
|
|
|
|
|
<value caption="Port F, Pin3" name="PORTF_PIN3" value="0x7B"/>
|
|
|
|
|
<value caption="Port F, Pin4" name="PORTF_PIN4" value="0x7C"/>
|
|
|
|
|
<value caption="Port F, Pin5" name="PORTF_PIN5" value="0x7D"/>
|
|
|
|
|
<value caption="Port F, Pin6" name="PORTF_PIN6" value="0x7E"/>
|
|
|
|
|
<value caption="Port F, Pin7" name="PORTF_PIN7" value="0x7F"/>
|
|
|
|
|
<value caption="Prescaler, divide by 1" name="PRESCALER_1" value="0x80"/>
|
|
|
|
|
<value caption="Prescaler, divide by 2" name="PRESCALER_2" value="0x81"/>
|
|
|
|
|
<value caption="Prescaler, divide by 4" name="PRESCALER_4" value="0x82"/>
|
|
|
|
|
<value caption="Prescaler, divide by 8" name="PRESCALER_8" value="0x83"/>
|
|
|
|
|
<value caption="Prescaler, divide by 16" name="PRESCALER_16" value="0x84"/>
|
|
|
|
|
<value caption="Prescaler, divide by 32" name="PRESCALER_32" value="0x85"/>
|
|
|
|
|
<value caption="Prescaler, divide by 64" name="PRESCALER_64" value="0x86"/>
|
|
|
|
|
<value caption="Prescaler, divide by 128" name="PRESCALER_128" value="0x87"/>
|
|
|
|
|
<value caption="Prescaler, divide by 256" name="PRESCALER_256" value="0x88"/>
|
|
|
|
|
<value caption="Prescaler, divide by 512" name="PRESCALER_512" value="0x89"/>
|
|
|
|
|
<value caption="Prescaler, divide by 1024" name="PRESCALER_1024" value="0x8A"/>
|
|
|
|
|
<value caption="Prescaler, divide by 2048" name="PRESCALER_2048" value="0x8B"/>
|
|
|
|
|
<value caption="Prescaler, divide by 4096" name="PRESCALER_4096" value="0x8C"/>
|
|
|
|
|
<value caption="Prescaler, divide by 8192" name="PRESCALER_8192" value="0x8D"/>
|
|
|
|
|
<value caption="Prescaler, divide by 16384" name="PRESCALER_16384" value="0x8E"/>
|
|
|
|
|
<value caption="Prescaler, divide by 32768" name="PRESCALER_32768" value="0x8F"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Overflow" name="TCC0_OVF" value="0xC0"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Error" name="TCC0_ERR" value="0xC1"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Compare or Capture A" name="TCC0_CCA" value="0xC4"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Compare or Capture B" name="TCC0_CCB" value="0xC5"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Compare or Capture C" name="TCC0_CCC" value="0xC6"/>
|
|
|
|
|
<value caption="Timer/Counter C0 Compare or Capture D" name="TCC0_CCD" value="0xC7"/>
|
|
|
|
|
<value caption="Timer/Counter C1 Overflow" name="TCC1_OVF" value="0xC8"/>
|
|
|
|
|
<value caption="Timer/Counter C1 Error" name="TCC1_ERR" value="0xC9"/>
|
|
|
|
|
<value caption="Timer/Counter C1 Compare or Capture A" name="TCC1_CCA" value="0xCC"/>
|
|
|
|
|
<value caption="Timer/Counter C1 Compare or Capture B" name="TCC1_CCB" value="0xCD"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Overflow" name="TCD0_OVF" value="0xD0"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Error" name="TCD0_ERR" value="0xD1"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Compare or Capture A" name="TCD0_CCA" value="0xD4"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Compare or Capture B" name="TCD0_CCB" value="0xD5"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Compare or Capture C" name="TCD0_CCC" value="0xD6"/>
|
|
|
|
|
<value caption="Timer/Counter D0 Compare or Capture D" name="TCD0_CCD" value="0xD7"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Overflow" name="TCE0_OVF" value="0xE0"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Error" name="TCE0_ERR" value="0xE1"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Compare or Capture A" name="TCE0_CCA" value="0xE4"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Compare or Capture B" name="TCE0_CCB" value="0xE5"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Compare or Capture C" name="TCE0_CCC" value="0xE6"/>
|
|
|
|
|
<value caption="Timer/Counter E0 Compare or Capture D" name="TCE0_CCD" value="0xE7"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Overflow" name="TCF0_OVF" value="0xF0"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Error" name="TCF0_ERR" value="0xF1"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Compare or Capture A" name="TCF0_CCA" value="0xF4"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Compare or Capture B" name="TCF0_CCB" value="0xF5"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Compare or Capture C" name="TCF0_CCC" value="0xF6"/>
|
|
|
|
|
<value caption="Timer/Counter F0 Compare or Capture D" name="TCF0_CCD" value="0xF7"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="NVM" id="I6076" version="XMEGAAU" caption="Non Volatile Memory Controller">
|
|
|
|
|
<register-group caption="Non-volatile Memory Controller" name="NVM" size="17">
|
|
|
|
|
<register caption="Address Register 0" name="ADDR0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Address Register 1" name="ADDR1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="Address Register 2" name="ADDR2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Data Register 0" name="DATA0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Data Register 1" name="DATA1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Data Register 2" name="DATA2" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="Command" name="CMD" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x7F" name="CMD" values="NVM_CMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Command Execute" mask="0x01" name="CMDEX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="EEPROM Mapping Enable" mask="0x08" name="EEMAPEN"/>
|
|
|
|
|
<bitfield caption="Flash Power Reduction Enable" mask="0x04" name="FPRM"/>
|
|
|
|
|
<bitfield caption="EEPROM Power Reduction Enable" mask="0x02" name="EPRM"/>
|
|
|
|
|
<bitfield caption="SPM Lock" mask="0x01" name="SPMLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control" name="INTCTRL" offset="0x0D" size="1">
|
|
|
|
|
<bitfield caption="SPM Interrupt Level" mask="0x0C" name="SPMLVL" values="NVM_SPMLVL"/>
|
|
|
|
|
<bitfield caption="EEPROM Interrupt Level" mask="0x03" name="EELVL" values="NVM_EELVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="Non-volatile Memory Busy" mask="0x80" name="NVMBUSY"/>
|
|
|
|
|
<bitfield caption="Flash Memory Busy" mask="0x40" name="FBUSY"/>
|
|
|
|
|
<bitfield caption="EEPROM Page Buffer Active Loading" mask="0x02" name="EELOAD"/>
|
|
|
|
|
<bitfield caption="Flash Page Buffer Active Loading" mask="0x01" name="FLOAD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Lock Bits" name="LOCKBITS" offset="0x10" size="1">
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Boot Section" mask="0xC0" name="BLBB" values="NVM_BLBB"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Section" mask="0x30" name="BLBA" values="NVM_BLBA"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Table" mask="0x0C" name="BLBAT" values="NVM_BLBAT"/>
|
|
|
|
|
<bitfield caption="Lock Bits" mask="0x03" name="LB" values="NVM_LB"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="NVM Command" name="NVM_CMD">
|
|
|
|
|
<value caption="Noop/Ordinary LPM" name="NO_OPERATION" value="0x00"/>
|
|
|
|
|
<value caption="Read user signature row" name="READ_USER_SIG_ROW" value="0x01"/>
|
|
|
|
|
<value caption="Read calibration row" name="READ_CALIB_ROW" value="0x02"/>
|
|
|
|
|
<value caption="Read EEPROM" name="READ_EEPROM" value="0x06"/>
|
|
|
|
|
<value caption="Read fuse byte" name="READ_FUSES" value="0x07"/>
|
|
|
|
|
<value caption="Write lock bits" name="WRITE_LOCK_BITS" value="0x08"/>
|
|
|
|
|
<value caption="Erase user signature row" name="ERASE_USER_SIG_ROW" value="0x18"/>
|
|
|
|
|
<value caption="Write user signature row" name="WRITE_USER_SIG_ROW" value="0x1A"/>
|
|
|
|
|
<value caption="Erase Application Section" name="ERASE_APP" value="0x20"/>
|
|
|
|
|
<value caption="Erase Application Section page" name="ERASE_APP_PAGE" value="0x22"/>
|
|
|
|
|
<value caption="Load Flash page buffer" name="LOAD_FLASH_BUFFER" value="0x23"/>
|
|
|
|
|
<value caption="Write Application Section page" name="WRITE_APP_PAGE" value="0x24"/>
|
|
|
|
|
<value caption="Erase-and-write Application Section page" name="ERASE_WRITE_APP_PAGE" value="0x25"/>
|
|
|
|
|
<value caption="Erase/flush Flash page buffer" name="ERASE_FLASH_BUFFER" value="0x26"/>
|
|
|
|
|
<value caption="Erase Boot Section page" name="ERASE_BOOT_PAGE" value="0x2A"/>
|
|
|
|
|
<value caption="Erase Flash Page" name="ERASE_FLASH_PAGE" value="0x2B"/>
|
|
|
|
|
<value caption="Write Boot Section page" name="WRITE_BOOT_PAGE" value="0x2C"/>
|
|
|
|
|
<value caption="Erase-and-write Boot Section page" name="ERASE_WRITE_BOOT_PAGE" value="0x2D"/>
|
|
|
|
|
<value caption="Write Flash Page" name="WRITE_FLASH_PAGE" value="0x2E"/>
|
|
|
|
|
<value caption="Erase-and-write Flash Page" name="ERASE_WRITE_FLASH_PAGE" value="0x2F"/>
|
|
|
|
|
<value caption="Erase EEPROM" name="ERASE_EEPROM" value="0x30"/>
|
|
|
|
|
<value caption="Erase EEPROM page" name="ERASE_EEPROM_PAGE" value="0x32"/>
|
|
|
|
|
<value caption="Load EEPROM page buffer" name="LOAD_EEPROM_BUFFER" value="0x33"/>
|
|
|
|
|
<value caption="Write EEPROM page" name="WRITE_EEPROM_PAGE" value="0x34"/>
|
|
|
|
|
<value caption="Erase-and-write EEPROM page" name="ERASE_WRITE_EEPROM_PAGE" value="0x35"/>
|
|
|
|
|
<value caption="Erase/flush EEPROM page buffer" name="ERASE_EEPROM_BUFFER" value="0x36"/>
|
|
|
|
|
<value caption="Application section CRC" name="APP_CRC" value="0x38"/>
|
|
|
|
|
<value caption=" Boot Section CRC" name="BOOT_CRC" value="0x39"/>
|
|
|
|
|
<value caption="Flash Range CRC" name="FLASH_RANGE_CRC" value="0x3A"/>
|
|
|
|
|
<value caption="Erase Chip" name="CHIP_ERASE" value="0x40"/>
|
|
|
|
|
<value caption="Read NVM" name="READ_NVM" value="0x43"/>
|
|
|
|
|
<value caption="Write Fuse byte" name="WRITE_FUSE" value="0x4C"/>
|
|
|
|
|
<value caption="Erase Boot Section" name="ERASE_BOOT" value="0x68"/>
|
|
|
|
|
<value caption="Flash CRC" name="FLASH_CRC" value="0x78"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="SPM ready interrupt level" name="NVM_SPMLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="EEPROM ready interrupt level" name="NVM_EELVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - boot section" name="NVM_BLBB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application section" name="NVM_BLBA">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application table section" name="NVM_BLBAT">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Lock bits" name="NVM_LB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="NVM">
|
|
|
|
|
<interrupt index="0" name="EE" caption="EE Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="SPM" caption="SPM Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="ADC" id="I6110" caption="Analog/Digital Converter">
|
|
|
|
|
<register-group caption="ADC Channel" name="ADC_CH" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Channel Start Conversion" mask="0x80" name="START"/>
|
|
|
|
|
<bitfield caption="Gain Factor" mask="0x1C" name="GAIN" values="ADC_CH_GAIN"/>
|
|
|
|
|
<bitfield caption="Input Mode Select" mask="0x03" name="INPUTMODE" values="ADC_CH_INPUTMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="MUX Control" name="MUXCTRL" offset="0x01" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="MUX selection on Positive ADC input" mask="0x78" name="MUXPOS" values="ADC_CH_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX selection on Internal ADC input" mask="0x78" name="MUXINT" values="ADC_CH_MUXINT"/>
|
|
|
|
|
<bitfield caption="MUX selection on Negative ADC input" mask="0x07" name="MUXNEG" values="ADC_CH_MUXNEG"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Interrupt Control Register" name="INTCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0x0C" name="INTMODE" values="ADC_CH_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x03" name="INTLVL" values="ADC_CH_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Channel Interrupt Flag" mask="0x01" name="CHIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Result" name="RES" offset="0x04" size="2"/>
|
|
|
|
|
<register caption="Input Channel Scan" name="SCAN" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Positive MUX setting offset" mask="0xF0" name="OFFSET"/>
|
|
|
|
|
<bitfield caption="Number of Channels included in scan" mask="0x0F" name="SCANNUM"/>
|
|
|
|
|
<bitfield caption="Number of Channels included in scan" mask="0x0F" name="COUNT"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="Analog-to-Digital Converter" name="ADC" size="40">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Channel 0 Start Conversion" mask="0x04" name="CH0START"/>
|
|
|
|
|
<bitfield caption="ADC Flush" mask="0x02" name="FLUSH"/>
|
|
|
|
|
<bitfield caption="Enable ADC" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Current Limitation" mask="0x60" name="CURRLIMIT" values="ADC_CURRLIMIT"/>
|
|
|
|
|
<bitfield caption="Conversion Mode" mask="0x10" name="CONMODE"/>
|
|
|
|
|
<bitfield caption="Free Running Mode Enable" mask="0x08" name="FREERUN"/>
|
|
|
|
|
<bitfield caption="Result Resolution" mask="0x06" name="RESOLUTION" values="ADC_RESOLUTION"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Reference Control" name="REFCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Reference Selection" mask="0x70" name="REFSEL" values="ADC_REFSEL"/>
|
|
|
|
|
<bitfield caption="Bandgap enable" mask="0x02" name="BANDGAP"/>
|
|
|
|
|
<bitfield caption="Temperature Reference Enable" mask="0x01" name="TEMPREF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Control" name="EVCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Input Select" mask="0x18" name="EVSEL" values="ADC_EVSEL"/>
|
|
|
|
|
<bitfield caption="Event Action Select" mask="0x07" name="EVACT" values="ADC_EVACT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Clock Prescaler" name="PRESCALER" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Clock Prescaler Selection" mask="0x07" name="PRESCALER" values="ADC_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Channel 0 Interrupt Flag" mask="0x01" name="CH0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register" name="TEMP" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="Sampling Time Control Register" name="SAMPCTRL" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Sampling Time Control" name="SAMPVAL" mask="0x3F"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Value" name="CAL" offset="0x0C" size="2"/>
|
|
|
|
|
<register caption="Channel 0 Result" name="CH0RES" offset="0x10" size="2"/>
|
|
|
|
|
<register caption="Compare Value" name="CMP" offset="0x18" size="2"/>
|
|
|
|
|
<register-group caption="ADC Channel 0" name="CH0" offset="0x20" name-in-module="ADC_CH"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Current Limitation" name="ADC_CURRLIMIT">
|
|
|
|
|
<value caption="No current limit, 300ksps max sampling rate" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Low current limit, 250ksps max sampling rate" name="LOW" value="0x01"/>
|
|
|
|
|
<value caption="Medium current limit, 150ksps max sampling rate" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High current limit, 50ksps max sampling rate" name="HIGH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Positive input multiplexer selection" name="ADC_CH_MUXPOS">
|
|
|
|
|
<value caption="Input pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 2" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 3" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Input pin 4" name="PIN4" value="0x04"/>
|
|
|
|
|
<value caption="Input pin 5" name="PIN5" value="0x05"/>
|
|
|
|
|
<value caption="Input pin 6" name="PIN6" value="0x06"/>
|
|
|
|
|
<value caption="Input pin 7" name="PIN7" value="0x07"/>
|
|
|
|
|
<value caption="Input pin 8" name="PIN8" value="0x08"/>
|
|
|
|
|
<value caption="Input pin 9" name="PIN9" value="0x09"/>
|
|
|
|
|
<value caption="Input pin 10" name="PIN10" value="0x0A"/>
|
|
|
|
|
<value caption="Input pin 11" name="PIN11" value="0x0B"/>
|
|
|
|
|
<value caption="Input pin 12" name="PIN12" value="0x0C"/>
|
|
|
|
|
<value caption="Input pin 13" name="PIN13" value="0x0D"/>
|
|
|
|
|
<value caption="Input pin 14" name="PIN14" value="0x0E"/>
|
|
|
|
|
<value caption="Input pin 15" name="PIN15" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Internal input multiplexer selections" name="ADC_CH_MUXINT">
|
|
|
|
|
<value caption="Temperature Reference" name="TEMP" value="0x00"/>
|
|
|
|
|
<value caption="Bandgap Reference" name="BANDGAP" value="0x01"/>
|
|
|
|
|
<value caption="1/10 scaled VCC" name="SCALEDVCC" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Negative input multiplexer selection" name="ADC_CH_MUXNEG">
|
|
|
|
|
<value caption="Input pin 0 (if INPUTMODE = 2)" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 1 (if INPUTMODE = 2)" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 2 (if INPUTMODE = 2)" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 3 (if INPUTMODE = 2)" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Input pin 4 (if INPUTMODE = 3)" name="PIN4" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 5 (if INPUTMODE = 3)" name="PIN5" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 6 (if INPUTMODE = 3)" name="PIN6" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 7 (if INPUTMODE = 3)" name="PIN7" value="0x03"/>
|
|
|
|
|
<value caption="PAD Ground (if INPUTMODE = 2)" name="GND_MODE3" value="0x05"/>
|
|
|
|
|
<value caption="Internal Ground (if INPUTMODE = 2)" name="INTGND_MODE3" value="0x07"/>
|
|
|
|
|
<value caption="Internal Ground (if INPUTMODE = 3)" name="INTGND_MODE4" value="0x04"/>
|
|
|
|
|
<value caption="PAD Ground (if INPUTMODE = 3)" name="GND_MODE4" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input mode" name="ADC_CH_INPUTMODE">
|
|
|
|
|
<value caption="Internal inputs, no gain (INPUTMODE = 0)" name="INTERNAL" value="0x00"/>
|
|
|
|
|
<value caption="Single-ended input, no gain (INPUTMODE = 1)" name="SINGLEENDED" value="0x01"/>
|
|
|
|
|
<value caption="Differential input, no gain (INPUTMODE = 2)" name="DIFF" value="0x02"/>
|
|
|
|
|
<value caption="Differential input, with gain (INPUTMODE = 3)" name="DIFFWGAIN" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Gain factor" name="ADC_CH_GAIN">
|
|
|
|
|
<value caption="1x gain" name="1X" value="0x00"/>
|
|
|
|
|
<value caption="2x gain" name="2X" value="0x01"/>
|
|
|
|
|
<value caption="4x gain" name="4X" value="0x02"/>
|
|
|
|
|
<value caption="8x gain" name="8X" value="0x03"/>
|
|
|
|
|
<value caption="16x gain" name="16X" value="0x04"/>
|
|
|
|
|
<value caption="32x gain" name="32X" value="0x05"/>
|
|
|
|
|
<value caption="64x gain" name="64X" value="0x06"/>
|
|
|
|
|
<value caption="x/2 gain" name="DIV2" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Conversion result resolution" name="ADC_RESOLUTION">
|
|
|
|
|
<value caption="12-bit right-adjusted result" name="12BIT" value="0x00"/>
|
|
|
|
|
<value caption="8-bit right-adjusted result" name="8BIT" value="0x02"/>
|
|
|
|
|
<value caption="12-bit left-adjusted result" name="LEFT12BIT" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Voltage reference selection" name="ADC_REFSEL">
|
|
|
|
|
<value caption="Internal 1V" name="INT1V" value="0x00"/>
|
|
|
|
|
<value caption="Internal VCC / 1.6" name="INTVCC" value="0x01"/>
|
|
|
|
|
<value caption="External reference on PORT A" name="AREFA" value="0x02"/>
|
|
|
|
|
<value caption="External reference on PORT B" name="AREFB" value="0x03"/>
|
|
|
|
|
<value caption="Internal VCC / 2" name="INTVCC2" value="0x04"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event channel input selection" name="ADC_EVSEL">
|
|
|
|
|
<value caption="Event Channel 0" name="0" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 1" name="1" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 2" name="2" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 3" name="3" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event action selection" name="ADC_EVACT">
|
|
|
|
|
<value caption="No event action" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="First event triggers channel 0" name="CH0" value="0x01"/>
|
|
|
|
|
<value caption="The ADC is flushed and restarted for accurate timing" name="SYNCSWEEP" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt mode" name="ADC_CH_INTMODE">
|
|
|
|
|
<value caption="Interrupt on conversion complete" name="COMPLETE" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on result below compare value" name="BELOW" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on result above compare value" name="ABOVE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="ADC_CH_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Clock prescaler" name="ADC_PRESCALER">
|
|
|
|
|
<value caption="Divide clock by 4" name="DIV4" value="0x00"/>
|
|
|
|
|
<value caption="Divide clock by 8" name="DIV8" value="0x01"/>
|
|
|
|
|
<value caption="Divide clock by 16" name="DIV16" value="0x02"/>
|
|
|
|
|
<value caption="Divide clock by 32" name="DIV32" value="0x03"/>
|
|
|
|
|
<value caption="Divide clock by 64" name="DIV64" value="0x04"/>
|
|
|
|
|
<value caption="Divide clock by 128" name="DIV128" value="0x05"/>
|
|
|
|
|
<value caption="Divide clock by 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="Divide clock by 512" name="DIV512" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="ADC">
|
|
|
|
|
<interrupt index="0" name="CH0" caption="Interrupt 0"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="AC" id="I6077" version="XMEGAD" caption="Analog Comparator">
|
|
|
|
|
<register-group caption="Analog Comparator" name="AC" size="8">
|
|
|
|
|
<register caption="Analog Comparator 0 Control" name="AC0CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0xC0" name="INTMODE" values="AC_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x30" name="INTLVL" values="AC_INTLVL"/>
|
|
|
|
|
<bitfield caption="Hysteresis Mode" mask="0x06" name="HYSMODE" values="AC_HYSMODE"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 1 Control" name="AC1CTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0xC0" name="INTMODE" values="AC_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x30" name="INTLVL" values="AC_INTLVL"/>
|
|
|
|
|
<bitfield caption="Hysteresis Mode" mask="0x06" name="HYSMODE" values="AC_HYSMODE"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 0 MUX Control" name="AC0MUXCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="MUX Positive Input" mask="0x38" name="MUXPOS" values="AC_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX Negative Input" mask="0x07" name="MUXNEG" values="AC_MUXNEG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 1 MUX Control" name="AC1MUXCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="MUX Positive Input" mask="0x38" name="MUXPOS" values="AC_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX Negative Input" mask="0x07" name="MUXNEG" values="AC_MUXNEG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Output Enable" mask="0x02" name="AC1OUT"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Output Enable" mask="0x01" name="AC0OUT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="VCC Voltage Scaler Factor" mask="0x3F" name="SCALEFAC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Window Mode Control" name="WINCTRL" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Window Mode Enable" mask="0x10" name="WEN"/>
|
|
|
|
|
<bitfield caption="Window Interrupt Mode" mask="0x0C" name="WINTMODE" values="AC_WINTMODE"/>
|
|
|
|
|
<bitfield caption="Window Interrupt Level" mask="0x03" name="WINTLVL" values="AC_WINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Window Mode State" mask="0xC0" name="WSTATE" values="AC_WSTATE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 State" mask="0x20" name="AC1STATE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 State" mask="0x10" name="AC0STATE"/>
|
|
|
|
|
<bitfield caption="Window Mode Interrupt Flag" mask="0x04" name="WIF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Flag" mask="0x02" name="AC1IF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Interrupt Flag" mask="0x01" name="AC0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Interrupt mode" name="AC_INTMODE">
|
|
|
|
|
<value caption="Interrupt on both edges" name="BOTHEDGES" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on falling edge" name="FALLING" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on rising edge" name="RISING" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="AC_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Hysteresis mode selection" name="AC_HYSMODE">
|
|
|
|
|
<value caption="No hysteresis" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Small hysteresis" name="SMALL" value="0x01"/>
|
|
|
|
|
<value caption="Large hysteresis" name="LARGE" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Positive input multiplexer selection" name="AC_MUXPOS">
|
|
|
|
|
<value caption="Pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Pin 2" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Pin 3" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Pin 4" name="PIN4" value="0x04"/>
|
|
|
|
|
<value caption="Pin 5" name="PIN5" value="0x05"/>
|
|
|
|
|
<value caption="Pin 6" name="PIN6" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Negative input multiplexer selection" name="AC_MUXNEG">
|
|
|
|
|
<value caption="Pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Pin 3" name="PIN3" value="0x02"/>
|
|
|
|
|
<value caption="Pin 5" name="PIN5" value="0x03"/>
|
|
|
|
|
<value caption="Pin 7" name="PIN7" value="0x04"/>
|
|
|
|
|
<value caption="Bandgap Reference" name="BANDGAP" value="0x06"/>
|
|
|
|
|
<value caption="Internal voltage scaler" name="SCALER" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Windows interrupt mode" name="AC_WINTMODE">
|
|
|
|
|
<value caption="Interrupt on above window" name="ABOVE" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on inside window" name="INSIDE" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on below window" name="BELOW" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on outside window" name="OUTSIDE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Window interrupt level" name="AC_WINTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low priority" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium priority" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High priority" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Window mode state" name="AC_WSTATE">
|
|
|
|
|
<value caption="Signal above window" name="ABOVE" value="0x00"/>
|
|
|
|
|
<value caption="Signal inside window" name="INSIDE" value="0x01"/>
|
|
|
|
|
<value caption="Signal below window" name="BELOW" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="AC">
|
|
|
|
|
<interrupt index="0" name="AC0" caption="AC0 Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="AC1" caption="AC1 Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="ACW" caption="ACW Window Mode Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="RTC" id="I6093" caption="Real-Time Counter">
|
|
|
|
|
<register-group caption="Real-Time Counter" name="RTC" size="14">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Prescaling Factor" mask="0x07" name="PRESCALER" values="RTC_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Synchronization Busy Flag" mask="0x01" name="SYNCBUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x02" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Compare Match Interrupt Level" mask="0x0C" name="COMPINTLVL" values="RTC_COMPINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Overflow Interrupt Level" mask="0x03" name="OVFINTLVL" values="RTC_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Compare Match Interrupt Flag" mask="0x02" name="COMPIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary register" name="TEMP" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Count Register" name="CNT" offset="0x08" size="2"/>
|
|
|
|
|
<register caption="Period Register" name="PER" offset="0x0A" size="2"/>
|
|
|
|
|
<register caption="Compare Register" name="COMP" offset="0x0C" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Prescaler Factor" name="RTC_PRESCALER">
|
|
|
|
|
<value caption="RTC Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="RTC Clock" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="RTC Clock / 2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
|
|
|
|
|
<value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
|
|
|
|
|
<value caption="RTC Clock / 64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="RTC Clock / 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="RTC Clock / 1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare Interrupt level" name="RTC_COMPINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Overflow Interrupt level" name="RTC_OVFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="RTC">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="COMP" caption="Compare Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TWI" id="I6089" version="XMEGAAU" caption="Two-Wire Interface">
|
|
|
|
|
<register-group caption="" name="TWI_MASTER" size="7">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0xC0" name="INTLVL" values="TWI_MASTER_INTLVL"/>
|
|
|
|
|
<bitfield caption="Read Interrupt Enable" mask="0x20" name="RIEN"/>
|
|
|
|
|
<bitfield caption="Write Interrupt Enable" mask="0x10" name="WIEN"/>
|
|
|
|
|
<bitfield caption="Enable TWI Master" mask="0x08" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Inactive Bus Timeout" mask="0x0C" name="TIMEOUT" values="TWI_MASTER_TIMEOUT"/>
|
|
|
|
|
<bitfield caption="Quick Command Enable" mask="0x02" name="QCEN"/>
|
|
|
|
|
<bitfield caption="Smart Mode Enable" mask="0x01" name="SMEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Acknowledge Action" mask="0x04" name="ACKACT"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x03" name="CMD" values="TWI_MASTER_CMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF"/>
|
|
|
|
|
<bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF"/>
|
|
|
|
|
<bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD"/>
|
|
|
|
|
<bitfield caption="Received Acknowledge" mask="0x10" name="RXACK"/>
|
|
|
|
|
<bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST"/>
|
|
|
|
|
<bitfield caption="Bus Error" mask="0x04" name="BUSERR"/>
|
|
|
|
|
<bitfield caption="Bus State" mask="0x03" name="BUSSTATE" values="TWI_MASTER_BUSSTATE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register" name="BAUD" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Address Register" name="ADDR" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x06" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="" name="TWI_SLAVE" size="6">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0xC0" name="INTLVL" values="TWI_SLAVE_INTLVL"/>
|
|
|
|
|
<bitfield caption="Data Interrupt Enable" mask="0x20" name="DIEN"/>
|
|
|
|
|
<bitfield caption="Address/Stop Interrupt Enable" mask="0x10" name="APIEN"/>
|
|
|
|
|
<bitfield caption="Enable TWI Slave" mask="0x08" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Stop Interrupt Enable" mask="0x04" name="PIEN"/>
|
|
|
|
|
<bitfield caption="Promiscuous Mode Enable" mask="0x02" name="PMEN"/>
|
|
|
|
|
<bitfield caption="Smart Mode Enable" mask="0x01" name="SMEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Acknowledge Action" mask="0x04" name="ACKACT"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x03" name="CMD" values="TWI_SLAVE_CMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF"/>
|
|
|
|
|
<bitfield caption="Address/Stop Interrupt Flag" mask="0x40" name="APIF"/>
|
|
|
|
|
<bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD"/>
|
|
|
|
|
<bitfield caption="Received Acknowledge" mask="0x10" name="RXACK"/>
|
|
|
|
|
<bitfield caption="Collision" mask="0x08" name="COLL"/>
|
|
|
|
|
<bitfield caption="Bus Error" mask="0x04" name="BUSERR"/>
|
|
|
|
|
<bitfield caption="Read/Write Direction" mask="0x02" name="DIR"/>
|
|
|
|
|
<bitfield caption="Slave Address or Stop" mask="0x01" name="AP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Address Register" name="ADDR" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Address Mask Register" name="ADDRMASK" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK"/>
|
|
|
|
|
<bitfield caption="Address Enable" mask="0x01" name="ADDREN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="Two-Wire Interface" name="TWI" size="14">
|
|
|
|
|
<register caption="TWI Common Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="SDA Hold Time Enable" mask="0x06" name="SDAHOLD" values="TWI_SDAHOLD"/>
|
|
|
|
|
<bitfield caption="External Driver Interface Enable" mask="0x01" name="EDIEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register-group caption="TWI master module" name="MASTER" offset="0x0001" name-in-module="TWI_MASTER"/>
|
|
|
|
|
<register-group caption="TWI slave module" name="SLAVE" offset="0x0008" name-in-module="TWI_SLAVE"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="SDA Hold Time" name="TWI_SDAHOLD">
|
|
|
|
|
<value caption="SDA Hold Time off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="SDA Hold Time 50 ns" name="50NS" value="0x01"/>
|
|
|
|
|
<value caption="SDA Hold Time 300 ns" name="300NS" value="0x02"/>
|
|
|
|
|
<value caption="SDA Hold Time 400 ns" name="400NS" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Interrupt Level" name="TWI_MASTER_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Inactive Timeout" name="TWI_MASTER_TIMEOUT">
|
|
|
|
|
<value caption="Bus Timeout Disabled" name="DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="50 Microseconds" name="50US" value="0x01"/>
|
|
|
|
|
<value caption="100 Microseconds" name="100US" value="0x02"/>
|
|
|
|
|
<value caption="200 Microseconds" name="200US" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Command" name="TWI_MASTER_CMD">
|
|
|
|
|
<value caption="No Action" name="NOACT" value="0x00"/>
|
|
|
|
|
<value caption="Issue Repeated Start Condition" name="REPSTART" value="0x01"/>
|
|
|
|
|
<value caption="Receive or Transmit Data" name="RECVTRANS" value="0x02"/>
|
|
|
|
|
<value caption="Issue Stop Condition" name="STOP" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Bus State" name="TWI_MASTER_BUSSTATE">
|
|
|
|
|
<value caption="Unknown Bus State" name="UNKNOWN" value="0x00"/>
|
|
|
|
|
<value caption="Bus is Idle" name="IDLE" value="0x01"/>
|
|
|
|
|
<value caption="This Module Controls The Bus" name="OWNER" value="0x02"/>
|
|
|
|
|
<value caption="The Bus is Busy" name="BUSY" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Slave Interrupt Level" name="TWI_SLAVE_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Slave Command" name="TWI_SLAVE_CMD">
|
|
|
|
|
<value caption="No Action" name="NOACT" value="0x00"/>
|
|
|
|
|
<value caption="Used To Complete a Transaction" name="COMPTRANS" value="0x02"/>
|
|
|
|
|
<value caption="Used in Response to Address/Data Interrupt" name="RESPONSE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="TWI">
|
|
|
|
|
<interrupt index="0" name="TWIS" caption="TWI Slave Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="TWIM" caption="TWI Master Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="USB" id="I3005" version="XMEGAAU" caption="USB">
|
|
|
|
|
<register-group caption="USB Endpoint" name="USB_EP" size="8">
|
|
|
|
|
<register caption="Endpoint Status" name="STATUS" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Endpoint Stall Flag" mask="0x80" name="STALLF"/>
|
|
|
|
|
<bitfield caption="CRC Error Flag" mask="0x80" name="CRC"/>
|
|
|
|
|
<bitfield caption="Underflow Enpoint FLag" mask="0x40" name="UNF"/>
|
|
|
|
|
<bitfield caption="Overflow Enpoint Flag for Output Endpoints" mask="0x40" name="OVF"/>
|
|
|
|
|
<bitfield caption="Transaction Complete 0 Flag" mask="0x20" name="TRNCOMPL0"/>
|
|
|
|
|
<bitfield caption="Transaction Complete 1 Flag" mask="0x10" name="TRNCOMPL1"/>
|
|
|
|
|
<bitfield caption="SETUP Transaction Complete Flag" mask="0x10" name="SETUP"/>
|
|
|
|
|
<bitfield caption="Bank Select" mask="0x08" name="BANK"/>
|
|
|
|
|
<bitfield caption="Data Buffer 1 Not Acknowledge" mask="0x04" name="BUSNACK1"/>
|
|
|
|
|
<bitfield caption="Data Buffer 0 Not Acknowledge" mask="0x02" name="BUSNACK0"/>
|
|
|
|
|
<bitfield caption="Data Toggle" mask="0x01" name="TOGGLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Endpoint Control" name="CTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Endpoint Type" mask="0xC0" name="TYPE" values="USB_EP_TYPE"/>
|
|
|
|
|
<bitfield caption="Multi Packet Transfer Enable" mask="0x20" name="MULTIPKT"/>
|
|
|
|
|
<bitfield caption="Ping-Pong Enable" mask="0x10" name="PINGPONG"/>
|
|
|
|
|
<bitfield caption="Interrupt Disable" mask="0x08" name="INTDSBL"/>
|
|
|
|
|
<bitfield caption="Data Stall" mask="0x04" name="STALL"/>
|
|
|
|
|
<bitfield caption="Data Buffer Size" mask="0x07" name="BUFSIZE" values="USB_EP_BUFSIZE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USB Endpoint Counter" name="CNT" offset="0x02" size="2">
|
|
|
|
|
<bitfield caption="Zero Length Packet" mask="0x8000" name="ZLP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Data Pointer" name="DATAPTR" offset="0x04" size="2"/>
|
|
|
|
|
<register caption="Auxiliary Data" name="AUXDATA" offset="0x06" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="Universal Serial Bus" name="USB" size="60">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="USB Enable" mask="0x80" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Speed Select" mask="0x40" name="SPEED"/>
|
|
|
|
|
<bitfield caption="USB FIFO Enable" mask="0x20" name="FIFOEN"/>
|
|
|
|
|
<bitfield caption="Store Frame Number Enable" mask="0x10" name="STFRNUM"/>
|
|
|
|
|
<bitfield caption="Maximum Endpoint Addresses" mask="0x0F" name="MAXEP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Pull during Reset" mask="0x10" name="PULLRST"/>
|
|
|
|
|
<bitfield caption="Remote Wake-up" mask="0x04" name="RWAKEUP"/>
|
|
|
|
|
<bitfield caption="Global NACK" mask="0x02" name="GNACK"/>
|
|
|
|
|
<bitfield caption="Attach" mask="0x01" name="ATTACH"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Upstream Resume" mask="0x08" name="URESUME"/>
|
|
|
|
|
<bitfield caption="Resume" mask="0x04" name="RESUME"/>
|
|
|
|
|
<bitfield caption="Bus Suspended" mask="0x02" name="SUSPEND"/>
|
|
|
|
|
<bitfield caption="Bus Reset" mask="0x01" name="BUSRST"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Address Register" name="ADDR" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Device Address" mask="0x7F" name="ADDR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="FIFO Write Pointer Register" name="FIFOWP" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="FIFO Write Pointer" mask="0x1F" name="FIFOWP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="FIFO Read Pointer Register" name="FIFORP" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="FIFO Read Pointer" mask="0x1F" name="FIFORP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Endpoint Configuration Table Pointer" name="EPPTR" offset="0x06" size="2"/>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Start Of Frame Interrupt Enable" mask="0x80" name="SOFIE"/>
|
|
|
|
|
<bitfield caption="Bus Event Interrupt Enable" mask="0x40" name="BUSEVIE"/>
|
|
|
|
|
<bitfield caption="Bus Error Interrupt Enable" mask="0x20" name="BUSERRIE"/>
|
|
|
|
|
<bitfield caption="STALL Interrupt Enable" mask="0x10" name="STALLIE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x03" name="INTLVL" values="USB_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Transaction Complete Interrupt Enable" mask="0x02" name="TRNIE"/>
|
|
|
|
|
<bitfield caption="SETUP Transaction Complete Interrupt Enable" mask="0x01" name="SETUPIE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Clear Interrupt Flag Register A" name="INTFLAGSACLR" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Start Of Frame Interrupt Flag" mask="0x80" name="SOFIF"/>
|
|
|
|
|
<bitfield caption="Suspend Interrupt Flag" mask="0x40" name="SUSPENDIF"/>
|
|
|
|
|
<bitfield caption="Resume Interrupt Flag" mask="0x20" name="RESUMEIF"/>
|
|
|
|
|
<bitfield caption="Reset Interrupt Flag" mask="0x10" name="RSTIF"/>
|
|
|
|
|
<bitfield caption="Isochronous CRC Error Interrupt Flag" mask="0x08" name="CRCIF"/>
|
|
|
|
|
<bitfield caption="Underflow Interrupt Flag" mask="0x04" name="UNFIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x02" name="OVFIF"/>
|
|
|
|
|
<bitfield caption="STALL Interrupt Flag" mask="0x01" name="STALLIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Set Interrupt Flag Register A" name="INTFLAGSASET" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Start Of Frame Interrupt Flag" mask="0x80" name="SOFIF"/>
|
|
|
|
|
<bitfield caption="Suspend Interrupt Flag" mask="0x40" name="SUSPENDIF"/>
|
|
|
|
|
<bitfield caption="Resume Interrupt Flag" mask="0x20" name="RESUMEIF"/>
|
|
|
|
|
<bitfield caption="Reset Interrupt Flag" mask="0x10" name="RSTIF"/>
|
|
|
|
|
<bitfield caption="Isochronous CRC Error Interrupt Flag" mask="0x08" name="CRCIF"/>
|
|
|
|
|
<bitfield caption="Underflow Interrupt Flag" mask="0x04" name="UNFIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x02" name="OVFIF"/>
|
|
|
|
|
<bitfield caption="STALL Interrupt Flag" mask="0x01" name="STALLIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Clear Interrupt Flag Register B" name="INTFLAGSBCLR" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Transaction Complete Interrupt Flag" mask="0x02" name="TRNIF"/>
|
|
|
|
|
<bitfield caption="SETUP Transaction Complete Interrupt Flag" mask="0x01" name="SETUPIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Set Interrupt Flag Register B" name="INTFLAGSBSET" offset="0x0D" size="1">
|
|
|
|
|
<bitfield caption="Transaction Complete Interrupt Flag" mask="0x02" name="TRNIF"/>
|
|
|
|
|
<bitfield caption="SETUP Transaction Complete Interrupt Flag" mask="0x01" name="SETUPIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Byte 0" name="CAL0" offset="0x3A" size="1"/>
|
|
|
|
|
<register caption="Calibration Byte 1" name="CAL1" offset="0x3B" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="USB Endpoint Table" name="USB_EP_TABLE" size="274">
|
|
|
|
|
<register caption="Frame Number Low Byte" name="FRAMENUML" offset="0x110" size="1"/>
|
|
|
|
|
<register caption="Frame Number High Byte" name="FRAMENUMH" offset="0x111" size="1"/>
|
|
|
|
|
<register-group caption="Endpoint 0" name="EP0OUT" offset="0x00" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 0" name="EP0IN" offset="0x08" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 1" name="EP1OUT" offset="0x10" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 1" name="EP1IN" offset="0x18" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 2" name="EP2OUT" offset="0x20" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 2" name="EP2IN" offset="0x28" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 3" name="EP3OUT" offset="0x30" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 3" name="EP3IN" offset="0x38" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 4" name="EP4OUT" offset="0x40" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 4" name="EP4IN" offset="0x48" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 5" name="EP5OUT" offset="0x50" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 5" name="EP5IN" offset="0x58" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 6" name="EP6OUT" offset="0x60" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 6" name="EP6IN" offset="0x68" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 7" name="EP7OUT" offset="0x70" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 7" name="EP7IN" offset="0x78" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 8" name="EP8OUT" offset="0x80" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 8" name="EP8IN" offset="0x88" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 9" name="EP9OUT" offset="0x90" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 9" name="EP9IN" offset="0x98" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 10" name="EP10OUT" offset="0xA0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 10" name="EP10IN" offset="0xA8" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 11" name="EP11OUT" offset="0xB0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 11" name="EP11IN" offset="0xB8" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 12" name="EP12OUT" offset="0xC0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 12" name="EP12IN" offset="0xC8" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 13" name="EP13OUT" offset="0xD0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 13" name="EP13IN" offset="0xD8" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 14" name="EP14OUT" offset="0xE0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 14" name="EP14IN" offset="0xE8" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 15" name="EP15OUT" offset="0xF0" name-in-module="USB_EP"/>
|
|
|
|
|
<register-group caption="Endpoint 15" name="EP15IN" offset="0xF8" name-in-module="USB_EP"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="USB_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="USB Endpoint Type" name="USB_EP_TYPE">
|
|
|
|
|
<value caption="Endpoint Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Control" name="CONTROL" value="0x01"/>
|
|
|
|
|
<value caption="Bulk/Interrupt" name="BULK" value="0x02"/>
|
|
|
|
|
<value caption="Isochronous" name="ISOCHRONOUS" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="USB Endpoint Buffersize" name="USB_EP_BUFSIZE">
|
|
|
|
|
<value caption="8 bytes buffer size" name="8" value="0x00"/>
|
|
|
|
|
<value caption="16 bytes buffer size" name="16" value="0x01"/>
|
|
|
|
|
<value caption="32 bytes buffer size" name="32" value="0x02"/>
|
|
|
|
|
<value caption="64 bytes buffer size" name="64" value="0x03"/>
|
|
|
|
|
<value caption="128 bytes buffer size" name="128" value="0x04"/>
|
|
|
|
|
<value caption="256 bytes buffer size" name="256" value="0x05"/>
|
|
|
|
|
<value caption="512 bytes buffer size" name="512" value="0x06"/>
|
|
|
|
|
<value caption="1023 bytes buffer size" name="1023" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="USB">
|
2023-12-13 20:40:14 +00:00
|
|
|
<interrupt index="0" name="BUSEVENT" caption="SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<interrupt index="1" name="TRNCOMPL" caption="Transaction complete interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PORT" id="I6075" version="XMEGAAU" caption="I/O Port Configuration">
|
|
|
|
|
<register-group caption="I/O Ports" name="PORT" size="24">
|
|
|
|
|
<register caption="I/O Port Data Direction" name="DIR" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Set" name="DIRSET" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Clear" name="DIRCLR" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Toggle" name="DIRTGL" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output" name="OUT" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Set" name="OUTSET" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Clear" name="OUTCLR" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Toggle" name="OUTTGL" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="I/O port Input" name="IN" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Port Interrupt 1 Level" mask="0x0C" name="INT1LVL" values="PORT_INT1LVL"/>
|
|
|
|
|
<bitfield caption="Port Interrupt 0 Level" mask="0x03" name="INT0LVL" values="PORT_INT0LVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Port Interrupt 0 Mask" name="INT0MASK" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Port Interrupt 1 Mask" name="INT1MASK" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Port Interrupt 1 Flag" mask="0x02" name="INT1IF"/>
|
|
|
|
|
<bitfield caption="Port Interrupt 0 Flag" mask="0x01" name="INT0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="I/O Port Pin Remap Register" name="REMAP" offset="0x0E" size="1">
|
|
|
|
|
<bitfield caption="SPI" mask="0x20" name="SPI"/>
|
|
|
|
|
<bitfield caption="USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 0 Output Compare D" mask="0x08" name="TC0D"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 0 Output Compare C" mask="0x04" name="TC0C"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 0 Output Compare B" mask="0x02" name="TC0B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 0 Output Compare A" mask="0x01" name="TC0A"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 0 Control Register" name="PIN0CTRL" offset="0x10" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 1 Control Register" name="PIN1CTRL" offset="0x11" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 2 Control Register" name="PIN2CTRL" offset="0x12" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 3 Control Register" name="PIN3CTRL" offset="0x13" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 4 Control Register" name="PIN4CTRL" offset="0x14" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 5 Control Register" name="PIN5CTRL" offset="0x15" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 6 Control Register" name="PIN6CTRL" offset="0x16" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 7 Control Register" name="PIN7CTRL" offset="0x17" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Enable" mask="0x80" name="SRLEN"/>
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Port Interrupt 0 Level" name="PORT_INT0LVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Port Interrupt 1 Level" name="PORT_INT1LVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Output/Pull Configuration" name="PORT_OPC">
|
|
|
|
|
<value caption="Totempole" name="TOTEM" value="0x00"/>
|
|
|
|
|
<value caption="Totempole w/ Bus keeper on Input and Output" name="BUSKEEPER" value="0x01"/>
|
|
|
|
|
<value caption="Totempole w/ Pull-down on Input" name="PULLDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Totempole w/ Pull-up on Input" name="PULLUP" value="0x03"/>
|
|
|
|
|
<value caption="Wired OR" name="WIREDOR" value="0x04"/>
|
|
|
|
|
<value caption="Wired AND" name="WIREDAND" value="0x05"/>
|
|
|
|
|
<value caption="Wired OR w/ Pull-down" name="WIREDORPULL" value="0x06"/>
|
|
|
|
|
<value caption="Wired AND w/ Pull-up" name="WIREDANDPULL" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input/Sense Configuration" name="PORT_ISC">
|
|
|
|
|
<value caption="Sense Both Edges" name="BOTHEDGES" value="0x00"/>
|
|
|
|
|
<value caption="Sense Rising Edge" name="RISING" value="0x01"/>
|
|
|
|
|
<value caption="Sense Falling Edge" name="FALLING" value="0x02"/>
|
|
|
|
|
<value caption="Sense Level (Transparent For Events)" name="LEVEL" value="0x03"/>
|
|
|
|
|
<value caption="Disable Digital Input Buffer" name="INPUT_DISABLE" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="PORT">
|
|
|
|
|
<interrupt index="0" name="INT0" caption="External Interrupt 0"/>
|
|
|
|
|
<interrupt index="1" name="INT1" caption="External Interrupt 1"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter With PWM">
|
|
|
|
|
<register-group caption="16-bit Timer/Counter 0" name="TC0" size="64">
|
2021-09-17 22:44:36 +01:00
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture D Enable" mask="0x80" name="CCDEN"/>
|
|
|
|
|
<bitfield caption="Compare or Capture C Enable" mask="0x40" name="CCCEN"/>
|
|
|
|
|
<bitfield caption="Compare or Capture B Enable" mask="0x20" name="CCBEN"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Enable" mask="0x10" name="CCAEN"/>
|
|
|
|
|
<bitfield caption="Waveform generation mode" mask="0x07" name="WGMODE" values="TC_WGMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Compare D Output Value" mask="0x08" name="CMPD"/>
|
|
|
|
|
<bitfield caption="Compare C Output Value" mask="0x04" name="CMPC"/>
|
|
|
|
|
<bitfield caption="Compare B Output Value" mask="0x02" name="CMPB"/>
|
|
|
|
|
<bitfield caption="Compare A Output Value" mask="0x01" name="CMPA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Action" mask="0xE0" name="EVACT" values="TC_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Delay" mask="0x10" name="EVDLY"/>
|
|
|
|
|
<bitfield caption="Event Source Select" mask="0x0F" name="EVSEL" values="TC_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Byte Mode" mask="0x03" name="BYTEM" values="TC_BYTEM"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Error Interrupt Level" mask="0x0C" name="ERRINTLVL" values="TC_ERRINTLVL"/>
|
|
|
|
|
<bitfield caption="Overflow interrupt level" mask="0x03" name="OVFINTLVL" values="TC_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x07" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Compare or Capture D Interrupt Level" mask="0xC0" name="CCDINTLVL" values="TC_CCDINTLVL"/>
|
|
|
|
|
<bitfield caption="Compare or Capture C Interrupt Level" mask="0x30" name="CCCINTLVL" values="TC_CCCINTLVL"/>
|
|
|
|
|
<bitfield caption="Compare or Capture B Interrupt Level" mask="0x0C" name="CCBINTLVL" values="TC_CCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Interrupt Level" mask="0x03" name="CCAINTLVL" values="TC_CCAINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F Clear" name="CTRLFCLR" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F Set" name="CTRLFSET" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Clear" name="CTRLGCLR" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture D Buffer Valid" mask="0x10" name="CCDBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture C Buffer Valid" mask="0x08" name="CCCBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture B Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Set" name="CTRLGSET" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture D Buffer Valid" mask="0x10" name="CCDBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture C Buffer Valid" mask="0x08" name="CCCBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture B Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture D Interrupt Flag" mask="0x80" name="CCDIF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture C Interrupt Flag" mask="0x40" name="CCCIF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture B Interrupt Flag" mask="0x20" name="CCBIF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Interrupt Flag" mask="0x10" name="CCAIF"/>
|
|
|
|
|
<bitfield caption="Error Interrupt Flag" mask="0x02" name="ERRIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register For 16-bit Access" name="TEMP" offset="0x0F" size="1"/>
|
|
|
|
|
<register caption="Count" name="CNT" offset="0x20" size="2"/>
|
|
|
|
|
<register caption="Period" name="PER" offset="0x26" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture A" name="CCA" offset="0x28" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture B" name="CCB" offset="0x2A" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture C" name="CCC" offset="0x2C" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture D" name="CCD" offset="0x2E" size="2"/>
|
|
|
|
|
<register caption="Period Buffer" name="PERBUF" offset="0x36" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture A Buffer" name="CCABUF" offset="0x38" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture B Buffer" name="CCBBUF" offset="0x3A" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture C Buffer" name="CCCBUF" offset="0x3C" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="16-bit Timer/Counter 1" name="TC1" size="60">
|
2021-09-17 22:44:36 +01:00
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture B Enable" mask="0x20" name="CCBEN"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Enable" mask="0x10" name="CCAEN"/>
|
|
|
|
|
<bitfield caption="Waveform generation mode" mask="0x07" name="WGMODE" values="TC_WGMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Compare B Output Value" mask="0x02" name="CMPB"/>
|
|
|
|
|
<bitfield caption="Compare A Output Value" mask="0x01" name="CMPA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Action" mask="0xE0" name="EVACT" values="TC_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Delay" mask="0x10" name="EVDLY"/>
|
|
|
|
|
<bitfield caption="Event Source Select" mask="0x0F" name="EVSEL" values="TC_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Byte Mode" mask="0x01" name="BYTEM"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Error Interrupt Level" mask="0x0C" name="ERRINTLVL" values="TC_ERRINTLVL"/>
|
|
|
|
|
<bitfield caption="Overflow interrupt level" mask="0x03" name="OVFINTLVL" values="TC_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x07" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Compare or Capture B Interrupt Level" mask="0x0C" name="CCBINTLVL" values="TC_CCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Interrupt Level" mask="0x03" name="CCAINTLVL" values="TC_CCAINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F Clear" name="CTRLFCLR" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F Set" name="CTRLFSET" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Clear" name="CTRLGCLR" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture B Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Set" name="CTRLGSET" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture B Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Compare or Capture B Interrupt Flag" mask="0x20" name="CCBIF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture A Interrupt Flag" mask="0x10" name="CCAIF"/>
|
|
|
|
|
<bitfield caption="Error Interrupt Flag" mask="0x02" name="ERRIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register For 16-bit Access" name="TEMP" offset="0x0F" size="1"/>
|
|
|
|
|
<register caption="Count" name="CNT" offset="0x20" size="2"/>
|
|
|
|
|
<register caption="Period" name="PER" offset="0x26" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture A" name="CCA" offset="0x28" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture B" name="CCB" offset="0x2A" size="2"/>
|
|
|
|
|
<register caption="Period Buffer" name="PERBUF" offset="0x36" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture A Buffer" name="CCABUF" offset="0x38" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture B Buffer" name="CCBBUF" offset="0x3A" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Clock Selection" name="TC_CLKSEL">
|
|
|
|
|
<value caption="Timer Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="System Clock / 2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="System Clock / 4" name="DIV4" value="0x03"/>
|
|
|
|
|
<value caption="System Clock / 8" name="DIV8" value="0x04"/>
|
|
|
|
|
<value caption="System Clock / 64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="System Clock / 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="System Clock / 1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
<value caption="Event Channel 0" name="EVCH0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="EVCH1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="EVCH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="EVCH3" value="0x0B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Waveform Generation Mode" name="TC_WGMODE">
|
|
|
|
|
<value caption="Normal Mode" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
|
|
|
|
|
<value caption="Single Slope" name="SINGLESLOPE" value="0x03"/>
|
|
|
|
|
<value caption="Single Slope" name="SS" value="0x03"/>
|
|
|
|
|
<value caption="Dual Slope, Update on TOP" name="DSTOP" value="0x05"/>
|
|
|
|
|
<value caption="Dual Slope, Update on TOP" name="DS_T" value="0x05"/>
|
|
|
|
|
<value caption="Dual Slope, Update on both TOP and BOTTOM" name="DSBOTH" value="0x06"/>
|
|
|
|
|
<value caption="Dual Slope, Update on both TOP and BOTTOM" name="DS_TB" value="0x06"/>
|
|
|
|
|
<value caption="Dual Slope, Update on BOTTOM" name="DSBOTTOM" value="0x07"/>
|
|
|
|
|
<value caption="Dual Slope, Update on BOTTOM" name="DS_B" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Byte Mode" name="TC_BYTEM">
|
|
|
|
|
<value caption="16-bit mode" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Timer/Counter operating in byte mode only" name="BYTEMODE" value="0x01"/>
|
|
|
|
|
<value caption="Timer/Counter split into two 8-bit Counters (TC2)" name="SPLITMODE" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Action" name="TC_EVACT">
|
|
|
|
|
<value caption="No Event Action" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Input Capture" name="CAPT" value="0x01"/>
|
|
|
|
|
<value caption="Externally Controlled Up/Down Count" name="UPDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Quadrature Decode" name="QDEC" value="0x03"/>
|
|
|
|
|
<value caption="Restart" name="RESTART" value="0x04"/>
|
|
|
|
|
<value caption="Frequency Capture" name="FRQ" value="0x05"/>
|
|
|
|
|
<value caption="Pulse-width Capture" name="PW" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Selection" name="TC_EVSEL">
|
|
|
|
|
<value caption="No Event Source" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 0" name="CH0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="CH1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="CH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="CH3" value="0x0B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Error Interrupt Level" name="TC_ERRINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Overflow Interrupt Level" name="TC_OVFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture D Interrupt Level" name="TC_CCDINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture C Interrupt Level" name="TC_CCCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture B Interrupt Level" name="TC_CCBINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture A Interrupt Level" name="TC_CCAINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Command" name="TC_CMD">
|
|
|
|
|
<value caption="No Command" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Force Update" name="UPDATE" value="0x01"/>
|
|
|
|
|
<value caption="Force Restart" name="RESTART" value="0x02"/>
|
|
|
|
|
<value caption="Force Hard Reset" name="RESET" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="TC0">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="ERR" caption="Error Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="CCA" caption="Compare or Capture A Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="CCB" caption="Compare or Capture B Interrupt"/>
|
|
|
|
|
<interrupt index="4" name="CCC" caption="Compare or Capture C Interrupt"/>
|
|
|
|
|
<interrupt index="5" name="CCD" caption="Compare or Capture D Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
<interrupt-group name="TC1">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="ERR" caption="Error Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="CCA" caption="Compare or Capture A Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="CCB" caption="Compare or Capture B Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC2" id="I6090" version="XMEGAD" caption="16-bit Timer/Counter type 2">
|
|
|
|
|
<register-group caption="16-bit Timer/Counter type 2" name="TC2" size="48">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="TC2_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="High Byte Compare D Enable" mask="0x80" name="HCMPDEN"/>
|
|
|
|
|
<bitfield caption="High Byte Compare C Enable" mask="0x40" name="HCMPCEN"/>
|
|
|
|
|
<bitfield caption="High Byte Compare B Enable" mask="0x20" name="HCMPBEN"/>
|
|
|
|
|
<bitfield caption="High Byte Compare A Enable" mask="0x10" name="HCMPAEN"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare D Enable" mask="0x08" name="LCMPDEN"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare C Enable" mask="0x04" name="LCMPCEN"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare B Enable" mask="0x02" name="LCMPBEN"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare A Enable" mask="0x01" name="LCMPAEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="High Byte Compare D Output Value" mask="0x80" name="HCMPD"/>
|
|
|
|
|
<bitfield caption="High Byte Compare C Output Value" mask="0x40" name="HCMPC"/>
|
|
|
|
|
<bitfield caption="High Byte Compare B Output Value" mask="0x20" name="HCMPB"/>
|
|
|
|
|
<bitfield caption="High Byte Compare A Output Value" mask="0x10" name="HCMPA"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare D Output Value" mask="0x08" name="LCMPD"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare C Output Value" mask="0x04" name="LCMPC"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare B Output Value" mask="0x02" name="LCMPB"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare A Output Value" mask="0x01" name="LCMPA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Byte Mode" mask="0x03" name="BYTEM" values="TC2_BYTEM"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x06" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="High Byte Underflow Interrupt Level" mask="0x0C" name="HUNFINTLVL" values="TC2_HUNFINTLVL"/>
|
|
|
|
|
<bitfield caption="Low Byte Underflow interrupt level" mask="0x03" name="LUNFINTLVL" values="TC2_LUNFINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x07" size="1">
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Low Byte Compare D Interrupt Level" mask="0xC0" name="LCMPDINTLVL" values="TC2_LCMPDINTLVL"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare C Interrupt Level" mask="0x30" name="LCMPCINTLVL" values="TC2_LCMPCINTLVL"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare B Interrupt Level" mask="0x0C" name="LCMPBINTLVL" values="TC2_LCMPBINTLVL"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare A Interrupt Level" mask="0x03" name="LCMPAINTLVL" values="TC2_LCMPAINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F" name="CTRLF" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC2_CMD"/>
|
|
|
|
|
<bitfield caption="Command Enable" mask="0x03" name="CMDEN" values="TC2_CMDEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Low Byte Compare D Interrupt Flag" mask="0x80" name="LCMPDIF"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare C Interrupt Flag" mask="0x40" name="LCMPCIF"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare B Interrupt Flag" mask="0x20" name="LCMPBIF"/>
|
|
|
|
|
<bitfield caption="Low Byte Compare A Interrupt Flag" mask="0x10" name="LCMPAIF"/>
|
|
|
|
|
<bitfield caption="High Byte Underflow Interrupt Flag" mask="0x02" name="HUNFIF"/>
|
|
|
|
|
<bitfield caption="Low Byte Underflow Interrupt Flag" mask="0x01" name="LUNFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Low Byte Count" name="LCNT" offset="0x20" size="1"/>
|
|
|
|
|
<register caption="High Byte Count" name="HCNT" offset="0x21" size="1"/>
|
|
|
|
|
<register caption="Low Byte Period" name="LPER" offset="0x26" size="1"/>
|
|
|
|
|
<register caption="High Byte Period" name="HPER" offset="0x27" size="1"/>
|
|
|
|
|
<register caption="Low Byte Compare A" name="LCMPA" offset="0x28" size="1"/>
|
|
|
|
|
<register caption="High Byte Compare A" name="HCMPA" offset="0x29" size="1"/>
|
|
|
|
|
<register caption="Low Byte Compare B" name="LCMPB" offset="0x2A" size="1"/>
|
|
|
|
|
<register caption="High Byte Compare B" name="HCMPB" offset="0x2B" size="1"/>
|
|
|
|
|
<register caption="Low Byte Compare C" name="LCMPC" offset="0x2C" size="1"/>
|
|
|
|
|
<register caption="High Byte Compare C" name="HCMPC" offset="0x2D" size="1"/>
|
|
|
|
|
<register caption="Low Byte Compare D" name="LCMPD" offset="0x2E" size="1"/>
|
|
|
|
|
<register caption="High Byte Compare D" name="HCMPD" offset="0x2F" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Clock Selection" name="TC2_CLKSEL">
|
|
|
|
|
<value caption="Timer Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="System Clock / 2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="System Clock / 4" name="DIV4" value="0x03"/>
|
|
|
|
|
<value caption="System Clock / 8" name="DIV8" value="0x04"/>
|
|
|
|
|
<value caption="System Clock / 64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="System Clock / 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="System Clock / 1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
<value caption="Event Channel 0" name="EVCH0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="EVCH1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="EVCH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="EVCH3" value="0x0B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Byte Mode" name="TC2_BYTEM">
|
|
|
|
|
<value caption="16-bit mode" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Timer/Counter operating in byte mode only (TC2)" name="BYTEMODE" value="0x01"/>
|
|
|
|
|
<value caption="Timer/Counter split into two 8-bit Counters" name="SPLITMODE" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="High Byte Underflow Interrupt Level" name="TC2_HUNFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Low Byte Underflow Interrupt Level" name="TC2_LUNFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Low Byte Compare D Interrupt Level" name="TC2_LCMPDINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Low Byte Compare C Interrupt Level" name="TC2_LCMPCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Low Byte Compare B Interrupt Level" name="TC2_LCMPBINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Low Byte Compare A Interrupt Level" name="TC2_LCMPAINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Command" name="TC2_CMD">
|
|
|
|
|
<value caption="No Command" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Force Restart" name="RESTART" value="0x02"/>
|
|
|
|
|
<value caption="Force Hard Reset" name="RESET" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Command" name="TC2_CMDEN">
|
|
|
|
|
<value caption="Low Byte Timer/Counter" name="LOW" value="0x01"/>
|
|
|
|
|
<value caption="High Byte Timer/Counter" name="HIGH" value="0x02"/>
|
|
|
|
|
<value caption="Both Low Byte and High Byte Timer/Counters" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="TC2">
|
|
|
|
|
<interrupt index="0" name="LUNF" caption="Low Byte Underflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="HUNF" caption="High Byte Underflow Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="LCMPA" caption="Low Byte Compare A Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="LCMPB" caption="Low Byte Compare B Interrupt"/>
|
|
|
|
|
<interrupt index="4" name="LCMPC" caption="Low Byte Compare C Interrupt"/>
|
|
|
|
|
<interrupt index="5" name="LCMPD" caption="Low Byte Compare D Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="AWEX" id="I6090" version="XMEGAAU" caption="Timer/Counter Advanced Waveform Extension">
|
|
|
|
|
<register-group caption="Advanced Waveform Extension" name="AWEX" size="13">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Pattern Generation Mode" mask="0x20" name="PGM"/>
|
|
|
|
|
<bitfield caption="Common Waveform Channel Mode" mask="0x10" name="CWCM"/>
|
|
|
|
|
<bitfield caption="Dead Time Insertion Compare Channel D Enable" mask="0x08" name="DTICCDEN"/>
|
|
|
|
|
<bitfield caption="Dead Time Insertion Compare Channel C Enable" mask="0x04" name="DTICCCEN"/>
|
|
|
|
|
<bitfield caption="Dead Time Insertion Compare Channel B Enable" mask="0x02" name="DTICCBEN"/>
|
|
|
|
|
<bitfield caption="Dead Time Insertion Compare Channel A Enable" mask="0x01" name="DTICCAEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Fault Detection Event Mask" name="FDEMASK" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Fault Detection Control Register" name="FDCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Fault Detect on Disable Break Disable" mask="0x10" name="FDDBD"/>
|
|
|
|
|
<bitfield caption="Fault Detect Mode" mask="0x04" name="FDMODE"/>
|
|
|
|
|
<bitfield caption="Fault Detect Action" mask="0x03" name="FDACT" values="AWEX_FDACT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Fault Detect Flag" mask="0x04" name="FDF"/>
|
|
|
|
|
<bitfield caption="Dead Time High Side Buffer Valid" mask="0x02" name="DTHSBUFV"/>
|
|
|
|
|
<bitfield caption="Dead Time Low Side Buffer Valid" mask="0x01" name="DTLSBUFV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Set Register" name="STATUSSET" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Fault Detect Flag" mask="0x04" name="FDF"/>
|
|
|
|
|
<bitfield caption="Dead Time High Side Buffer Valid" mask="0x02" name="DTHSBUFV"/>
|
|
|
|
|
<bitfield caption="Dead Time Low Side Buffer Valid" mask="0x01" name="DTLSBUFV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Dead Time Both Sides" name="DTBOTH" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="Dead Time Both Sides Buffer" name="DTBOTHBUF" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="Dead Time Low Side" name="DTLS" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Dead Time High Side" name="DTHS" offset="0x09" size="1"/>
|
|
|
|
|
<register caption="Dead Time Low Side Buffer" name="DTLSBUF" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Dead Time High Side Buffer" name="DTHSBUF" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Output Override Enable" name="OUTOVEN" offset="0x0C" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Fault Detect Action" name="AWEX_FDACT">
|
|
|
|
|
<value caption="No Fault Protection" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Clear Output Enable Bits" name="CLEAROE" value="0x01"/>
|
|
|
|
|
<value caption="Clear I/O Port Direction Bits" name="CLEARDIR" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="HIRES" id="I6090" version="XMEGAAU" caption="Timer/Counter High-Resolution Extension">
|
|
|
|
|
<register-group caption="High-Resolution Extension" name="HIRES" size="1">
|
|
|
|
|
<register caption="Control Register" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="High Resolution Plus" mask="0x04" name="HRPLUS"/>
|
|
|
|
|
<bitfield caption="High Resolution Enable" mask="0x03" name="HREN" values="HIRES_HREN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="High Resolution Enable" name="HIRES_HREN">
|
|
|
|
|
<value caption="No Fault Protection" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Enable High Resolution on Timer/Counter 0" name="TC0" value="0x01"/>
|
|
|
|
|
<value caption="Enable High Resolution on Timer/Counter 1" name="TC1" value="0x02"/>
|
|
|
|
|
<value caption="Enable High Resolution both Timer/Counters" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="USART" id="I6090" version="XMEGAAU" caption="Universal Asynchronous Receiver-Transmitter">
|
|
|
|
|
<register-group caption="Universal Synchronous/Asynchronous Receiver/Transmitter" name="USART" size="8">
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Receive Interrupt Flag" mask="0x80" name="RXCIF"/>
|
|
|
|
|
<bitfield caption="Transmit Interrupt Flag" mask="0x40" name="TXCIF"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Flag" mask="0x20" name="DREIF"/>
|
|
|
|
|
<bitfield caption="Frame Error" mask="0x10" name="FERR"/>
|
|
|
|
|
<bitfield caption="Buffer Overflow" mask="0x08" name="BUFOVF"/>
|
|
|
|
|
<bitfield caption="Parity Error" mask="0x04" name="PERR"/>
|
|
|
|
|
<bitfield caption="Receive Bit 8" mask="0x01" name="RXB8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Receive Interrupt Level" mask="0x30" name="RXCINTLVL" values="USART_RXCINTLVL"/>
|
|
|
|
|
<bitfield caption="Transmit Interrupt Level" mask="0x0C" name="TXCINTLVL" values="USART_TXCINTLVL"/>
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Data Register Empty Interrupt Level" mask="0x03" name="DREINTLVL" values="USART_DREINTLVL"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Receiver Enable" mask="0x10" name="RXEN"/>
|
|
|
|
|
<bitfield caption="Transmitter Enable" mask="0x08" name="TXEN"/>
|
|
|
|
|
<bitfield caption="Double transmission speed" mask="0x04" name="CLK2X"/>
|
|
|
|
|
<bitfield caption="Multi-processor Communication Mode" mask="0x02" name="MPCM"/>
|
|
|
|
|
<bitfield caption="Transmit bit 8" mask="0x01" name="TXB8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Communication Mode" mask="0xC0" name="CMODE" values="USART_CMODE"/>
|
|
|
|
|
<bitfield caption="Parity Mode" mask="0x30" name="PMODE" values="USART_PMODE"/>
|
|
|
|
|
<bitfield caption="Stop Bit Mode" mask="0x08" name="SBMODE"/>
|
|
|
|
|
<bitfield caption="Character Size" mask="0x07" name="CHSIZE" values="USART_CHSIZE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register A" name="BAUDCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Baud Rate Selection Bits [7:0]" mask="0xFF" name="BSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register B" name="BAUDCTRLB" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Baud Rate Scale" mask="0xF0" name="BSCALE"/>
|
|
|
|
|
<bitfield caption="Baud Rate Selection bits[11:8]" mask="0x0F" name="BSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Receive Complete Interrupt level" name="USART_RXCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Transmit Complete Interrupt level" name="USART_TXCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Data Register Empty Interrupt level" name="USART_DREINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Character Size" name="USART_CHSIZE">
|
|
|
|
|
<value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
|
|
|
|
|
<value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
|
|
|
|
|
<value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
|
|
|
|
|
<value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
|
|
|
|
|
<value caption="Character size: 9 bit" name="9BIT" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Communication Mode" name="USART_CMODE">
|
|
|
|
|
<value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
|
|
|
|
|
<value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
|
|
|
|
|
<value caption="IrDA Mode" name="IRDA" value="0x02"/>
|
|
|
|
|
<value caption="Master SPI Mode" name="MSPI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Parity Mode" name="USART_PMODE">
|
|
|
|
|
<value caption="No Parity" name="DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="Even Parity" name="EVEN" value="0x02"/>
|
|
|
|
|
<value caption="Odd Parity" name="ODD" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="USART">
|
|
|
|
|
<interrupt index="0" name="RXC" caption="Reception Complete Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="DRE" caption="Data Register Empty Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="TXC" caption="Transmission Complete Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SPI" id="I6090" version="XMEGAAU" caption="Serial Peripheral Interface">
|
|
|
|
|
<register-group caption="Serial Peripheral Interface" name="SPI" size="4">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Enable Double Speed" mask="0x80" name="CLK2X"/>
|
|
|
|
|
<bitfield caption="Enable Module" mask="0x40" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Data Order Setting" mask="0x20" name="DORD"/>
|
|
|
|
|
<bitfield caption="Master Operation Enable" mask="0x10" name="MASTER"/>
|
|
|
|
|
<bitfield caption="SPI Mode" mask="0x0C" name="MODE" values="SPI_MODE"/>
|
|
|
|
|
<bitfield caption="Prescaler" mask="0x03" name="PRESCALER" values="SPI_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Interrupt level" mask="0x03" name="INTLVL" values="SPI_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Flag" mask="0x80" name="IF"/>
|
|
|
|
|
<bitfield caption="Write Collision" mask="0x40" name="WRCOL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x03" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="SPI Mode" name="SPI_MODE">
|
|
|
|
|
<value caption="SPI Mode 0" name="0" value="0x00"/>
|
|
|
|
|
<value caption="SPI Mode 1" name="1" value="0x01"/>
|
|
|
|
|
<value caption="SPI Mode 2" name="2" value="0x02"/>
|
|
|
|
|
<value caption="SPI Mode 3" name="3" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler setting" name="SPI_PRESCALER">
|
|
|
|
|
<value caption="System Clock / 4" name="DIV4" value="0x00"/>
|
|
|
|
|
<value caption="System Clock / 16" name="DIV16" value="0x01"/>
|
|
|
|
|
<value caption="System Clock / 64" name="DIV64" value="0x02"/>
|
|
|
|
|
<value caption="System Clock / 128" name="DIV128" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="SPI_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="SPI">
|
|
|
|
|
<interrupt index="0" name="INT" caption="SPI Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="IRCOM" id="I6090" version="XMEGAD" caption="IR Communication Module">
|
|
|
|
|
<register-group caption="IR Communication Module" name="IRCOM" size="3">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Event Channel Select" mask="0x0F" name="EVSEL" values="IRDA_EVSEL"/>
|
|
|
|
|
</register>
|
2023-12-13 20:40:14 +00:00
|
|
|
<register caption="IrDA Transmitter Pulse Length Control Register" name="TXPLCTRL" offset="0x01" size="1"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<register caption="IrDA Receiver Pulse Length Control Register" name="RXPLCTRL" offset="0x02" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Event channel selection" name="IRDA_EVSEL">
|
|
|
|
|
<value caption="No Event Source" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 0" name="0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="3" value="0x0B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FUSE" id="I6570" version="XMEGAD" caption="Fuses and Lockbits">
|
|
|
|
|
<register-group caption="Fuses" name="NVM_FUSES" size="6">
|
|
|
|
|
<register caption="Watchdog Configuration" name="FUSEBYTE1" offset="0x01" size="1" initval="0x00">
|
|
|
|
|
<bitfield caption="Watchdog Window Timeout Period" mask="0xF0" name="WDWPER" values="WDWPER"/>
|
|
|
|
|
<bitfield caption="Watchdog Timeout Period" mask="0x0F" name="WDPER" values="WDPER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Reset Configuration" name="FUSEBYTE2" offset="0x02" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Boot Loader Section Reset Vector" mask="0x40" name="BOOTRST" values="BOOTRST"/>
|
|
|
|
|
<bitfield caption="Timer Oscillator pin location" mask="0x20" name="TOSCSEL" values="TOSCSEL"/>
|
|
|
|
|
<bitfield caption="BOD Operation in Power-Down Mode" mask="0x03" name="BODPD" values="BODPD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Start-up Configuration" name="FUSEBYTE4" offset="0x04" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="External Reset Disable" mask="0x10" name="RSTDISBL"/>
|
|
|
|
|
<bitfield caption="Start-up Time" mask="0x0C" name="STARTUPTIME" values="SUT"/>
|
|
|
|
|
<bitfield caption="Watchdog Timer Lock" mask="0x02" name="WDLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EESAVE and BOD Level" name="FUSEBYTE5" offset="0x05" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="BOD Operation in Active Mode" mask="0x30" name="BODACT" values="BODACT"/>
|
|
|
|
|
<bitfield caption="Preserve EEPROM Through Chip Erase" mask="0x08" name="EESAVE"/>
|
|
|
|
|
<bitfield caption="Brownout Detection Voltage Level" mask="0x07" name="BODLEVEL" values="BODLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Boot Loader Section Reset Vector" name="BOOTRST">
|
|
|
|
|
<value caption="Boot Loader Reset" name="BOOTLDR" value="0x00"/>
|
|
|
|
|
<value caption="Application Reset" name="APPLICATION" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer Oscillator pin location" name="TOSCSEL">
|
|
|
|
|
<value caption="TOSC1 / TOSC2 on separate pins" name="ALTERNATE" value="0x00"/>
|
|
|
|
|
<value caption="TOSC1 / TOSC2 shared with XTAL1 / XTAL2" name="XTAL" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="BOD operation" name="BODPD">
|
|
|
|
|
<value caption="BOD enabled in sampled mode" name="SAMPLED" value="0x01"/>
|
|
|
|
|
<value caption="BOD enabled continuously" name="CONTINUOUS" value="0x02"/>
|
|
|
|
|
<value caption="BOD Disabled" name="DISABLED" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="BOD operation" name="BODACT">
|
|
|
|
|
<value caption="BOD enabled in sampled mode" name="SAMPLED" value="0x01"/>
|
|
|
|
|
<value caption="BOD enabled continuously" name="CONTINUOUS" value="0x02"/>
|
|
|
|
|
<value caption="BOD Disabled" name="DISABLED" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Watchdog (Window) Timeout Period" name="WDWPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.125s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.25s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.5s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Watchdog (Window) Timeout Period" name="WDPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.125s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.25s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.5s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Start-up Time" name="SUT">
|
|
|
|
|
<value caption="0 ms" name="0MS" value="0x03"/>
|
|
|
|
|
<value caption="4 ms" name="4MS" value="0x01"/>
|
|
|
|
|
<value caption="64 ms" name="64MS" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Brownout Detection Voltage Level" name="BODLVL">
|
|
|
|
|
<value caption="1.6 V" name="1V6" value="0x07"/>
|
|
|
|
|
<value caption="1.8 V" name="1V8" value="0x06"/>
|
|
|
|
|
<value caption="2.0 V" name="2V0" value="0x05"/>
|
|
|
|
|
<value caption="2.2 V" name="2V2" value="0x04"/>
|
|
|
|
|
<value caption="2.4 V" name="2V4" value="0x03"/>
|
|
|
|
|
<value caption="2.6 V" name="2V6" value="0x02"/>
|
|
|
|
|
<value caption="2.8 V" name="2V8" value="0x01"/>
|
|
|
|
|
<value caption="3.0 V" name="3V0" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="LOCKBIT" id="I6570" version="XMEGAD" caption="Fuses and Lockbits">
|
|
|
|
|
<register-group caption="Lock Bits" name="NVM_LOCKBITS">
|
|
|
|
|
<register caption="Lock Bits" name="LOCKBITS" offset="0x00" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Boot Section" mask="0xC0" name="BLBB" values="FUSE_BLBB"/>
|
2023-12-13 20:40:14 +00:00
|
|
|
<bitfield caption="Boot Lock Bits - Application Section" mask="0x30" name="BLBA" values="FUSE_BLBA"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Table" mask="0x0C" name="BLBAT" values="FUSE_BLBAT"/>
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Lock Bits" mask="0x03" name="LB" values="FUSE_LB"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Boot lock bits - boot section" name="FUSE_BLBB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application section" name="FUSE_BLBA">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application table section" name="FUSE_BLBAT">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Lock bits" name="FUSE_LB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SIGROW" id="I3610" version="XMEGAC" caption="Signature Row">
|
|
|
|
|
<register-group caption="Production Signatures" name="NVM_PROD_SIGNATURES" size="64">
|
|
|
|
|
<register caption="RCOSC 2 MHz Calibration Value B" name="RCOSC2M" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="RCOSC 2 MHz Calibration Value A" name="RCOSC2MA" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32.768 kHz Calibration Value" name="RCOSC32K" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32 MHz Calibration Value B" name="RCOSC32M" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32 MHz Calibration Value A" name="RCOSC32MA" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 0, ASCII" name="LOTNUM0" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 1, ASCII" name="LOTNUM1" offset="0x09" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 2, ASCII" name="LOTNUM2" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 3, ASCII" name="LOTNUM3" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 4, ASCII" name="LOTNUM4" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 5, ASCII" name="LOTNUM5" offset="0x0D" size="1"/>
|
|
|
|
|
<register caption="Wafer Number" name="WAFNUM" offset="0x10" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate X Byte 0" name="COORDX0" offset="0x12" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate X Byte 1" name="COORDX1" offset="0x13" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate Y Byte 0" name="COORDY0" offset="0x14" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate Y Byte 1" name="COORDY1" offset="0x15" size="1"/>
|
|
|
|
|
<register caption="USB Calibration Byte 0" name="USBCAL0" offset="0x1A" size="1"/>
|
|
|
|
|
<register caption="USB Calibration Byte 1" name="USBCAL1" offset="0x1B" size="1"/>
|
|
|
|
|
<register caption="USB RCOSC Calibration Value B" name="USBRCOSC" offset="0x1C" size="1"/>
|
|
|
|
|
<register caption="USB RCOSC Calibration Value A" name="USBRCOSCA" offset="0x1D" size="1"/>
|
|
|
|
|
<register caption="ADCA Calibration Byte 0" name="ADCACAL0" offset="0x20" size="1"/>
|
|
|
|
|
<register caption="ADCA Calibration Byte 1" name="ADCACAL1" offset="0x21" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 0" name="TEMPSENSE0" offset="0x2E" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 1" name="TEMPSENSE1" offset="0x2F" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
</modules>
|
2021-06-12 01:43:30 +01:00
|
|
|
<pinouts>
|
|
|
|
|
<pinout name="QFP_QFN_64">
|
|
|
|
|
<pin pad="PA3" position="1"/>
|
|
|
|
|
<pin pad="PA4" position="2"/>
|
|
|
|
|
<pin pad="PA5" position="3"/>
|
|
|
|
|
<pin pad="PA6" position="4"/>
|
|
|
|
|
<pin pad="PA7" position="5"/>
|
|
|
|
|
<pin pad="PB0" position="6"/>
|
|
|
|
|
<pin pad="PB1" position="7"/>
|
|
|
|
|
<pin pad="PB2" position="8"/>
|
|
|
|
|
<pin pad="PB3" position="9"/>
|
|
|
|
|
<pin pad="PB4" position="10"/>
|
|
|
|
|
<pin pad="PB5" position="11"/>
|
|
|
|
|
<pin pad="PB6" position="12"/>
|
|
|
|
|
<pin pad="PB7" position="13"/>
|
|
|
|
|
<pin pad="GND" position="14"/>
|
|
|
|
|
<pin pad="VCC" position="15"/>
|
|
|
|
|
<pin pad="PC0" position="16"/>
|
|
|
|
|
<pin pad="PC1" position="17"/>
|
|
|
|
|
<pin pad="PC2" position="18"/>
|
|
|
|
|
<pin pad="PC3" position="19"/>
|
|
|
|
|
<pin pad="PC4" position="20"/>
|
|
|
|
|
<pin pad="PC5" position="21"/>
|
|
|
|
|
<pin pad="PC6" position="22"/>
|
|
|
|
|
<pin pad="PC7" position="23"/>
|
|
|
|
|
<pin pad="GND" position="24"/>
|
|
|
|
|
<pin pad="VCC" position="25"/>
|
|
|
|
|
<pin pad="PD0" position="26"/>
|
|
|
|
|
<pin pad="PD1" position="27"/>
|
|
|
|
|
<pin pad="PD2" position="28"/>
|
|
|
|
|
<pin pad="PD3" position="29"/>
|
|
|
|
|
<pin pad="PD4" position="30"/>
|
|
|
|
|
<pin pad="PD5" position="31"/>
|
|
|
|
|
<pin pad="PD6" position="32"/>
|
|
|
|
|
<pin pad="PD7" position="33"/>
|
|
|
|
|
<pin pad="GND" position="34"/>
|
|
|
|
|
<pin pad="VCC" position="35"/>
|
|
|
|
|
<pin pad="PE0" position="36"/>
|
|
|
|
|
<pin pad="PE1" position="37"/>
|
|
|
|
|
<pin pad="PE2" position="38"/>
|
|
|
|
|
<pin pad="PE3" position="39"/>
|
|
|
|
|
<pin pad="PE4" position="40"/>
|
|
|
|
|
<pin pad="PE5" position="41"/>
|
|
|
|
|
<pin pad="PE6" position="42"/>
|
|
|
|
|
<pin pad="PE7" position="43"/>
|
|
|
|
|
<pin pad="GND" position="44"/>
|
|
|
|
|
<pin pad="VCC" position="45"/>
|
|
|
|
|
<pin pad="PF0" position="46"/>
|
|
|
|
|
<pin pad="PF1" position="47"/>
|
|
|
|
|
<pin pad="PF2" position="48"/>
|
|
|
|
|
<pin pad="PF3" position="49"/>
|
|
|
|
|
<pin pad="PF4" position="50"/>
|
|
|
|
|
<pin pad="PF5" position="51"/>
|
|
|
|
|
<pin pad="GND" position="52"/>
|
|
|
|
|
<pin pad="VCC" position="53"/>
|
|
|
|
|
<pin pad="PF6" position="54"/>
|
|
|
|
|
<pin pad="PF7" position="55"/>
|
|
|
|
|
<pin pad="PDI" position="56"/>
|
|
|
|
|
<pin pad="RESET" position="57"/>
|
|
|
|
|
<pin pad="PR0" position="58"/>
|
|
|
|
|
<pin pad="PR1" position="59"/>
|
|
|
|
|
<pin pad="GND" position="60"/>
|
|
|
|
|
<pin pad="AVCC" position="61"/>
|
|
|
|
|
<pin pad="PA0" position="62"/>
|
|
|
|
|
<pin pad="PA1" position="63"/>
|
|
|
|
|
<pin pad="PA2" position="64"/>
|
|
|
|
|
</pinout>
|
|
|
|
|
</pinouts>
|
2021-05-31 01:01:14 +01:00
|
|
|
</target-description-file>
|
