2021-04-04 21:04:12 +01:00
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<?xml version="1.0" encoding="UTF-8"?>
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2021-05-31 01:01:14 +01:00
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<target-description-file>
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2021-04-04 21:04:12 +01:00
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<variants>
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<variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="2.7" vccmax="5.5"/>
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</variants>
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<devices>
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<device name="AT90PWM2B" architecture="AVR8" family="megaAVR">
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<address-spaces>
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<address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x2000">
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<memory-segment start="0x0000" size="0x2000" type="flash" rw="RW" exec="1" name="FLASH"
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pagesize="0x40"/>
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<memory-segment start="0x1f00" size="0x0100" type="flash" rw="RW" exec="1" name="BOOT_SECTION_1"
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pagesize="0x40"/>
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<memory-segment start="0x1e00" size="0x0200" type="flash" rw="RW" exec="1" name="BOOT_SECTION_2"
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pagesize="0x40"/>
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<memory-segment start="0x1c00" size="0x0400" type="flash" rw="RW" exec="1" name="BOOT_SECTION_3"
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pagesize="0x40"/>
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<memory-segment start="0x1800" size="0x0800" type="flash" rw="RW" exec="1" name="BOOT_SECTION_4"
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pagesize="0x40"/>
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</address-space>
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<address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
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<memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
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</address-space>
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<address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0003">
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<memory-segment start="0" size="0x0003" type="fuses" rw="RW" exec="0" name="FUSES"/>
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</address-space>
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<address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
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<memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
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</address-space>
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<address-space endianness="little" name="data" id="data" start="0x0000" size="0x0300">
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<memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
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<memory-segment name="MAPPED_IO" start="0x0020" size="0x00e0" type="io" external="false"/>
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<memory-segment name="IRAM" start="0x0100" size="0x0200" type="ram" external="false"/>
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</address-space>
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<address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0200">
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<memory-segment start="0x0000" size="0x0200" type="eeprom" rw="RW" exec="0" name="EEPROM"
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pagesize="0x04"/>
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</address-space>
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<address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
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<address-space endianness="little" name="osccal" id="osccal" start="0" size="1">
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<memory-segment start="0" size="1" type="osccal" rw="R" exec="0" name="OSCCAL"/>
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</address-space>
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</address-spaces>
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<peripherals>
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<module name="PORT">
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<instance name="PORTB" caption="I/O Port">
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<register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"
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caption="I/O Port"/>
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</instance>
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<instance name="PORTD" caption="I/O Port">
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<register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"
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caption="I/O Port"/>
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</instance>
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<instance name="PORTE" caption="I/O Port">
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<register-group name="PORTE" name-in-module="PORTE" offset="0x00" address-space="data"
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caption="I/O Port"/>
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</instance>
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</module>
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<module name="BOOT_LOAD">
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<instance name="BOOT_LOAD" caption="Bootloader">
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<register-group name="BOOT_LOAD" name-in-module="BOOT_LOAD" offset="0x00" address-space="data"
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caption="Bootloader"/>
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</instance>
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</module>
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<module name="EUSART">
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<instance name="EUSART" caption="Extended USART">
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<register-group name="EUSART" name-in-module="EUSART" offset="0x00" address-space="data"
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caption="Extended USART"/>
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</instance>
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</module>
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<module name="AC">
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<instance name="AC" caption="Analog Comparator">
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<register-group name="AC" name-in-module="AC" offset="0x00" address-space="data"
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caption="Analog Comparator"/>
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</instance>
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</module>
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<module name="DAC">
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<instance name="DAC" caption="Digital-to-Analog Converter">
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<register-group name="DAC" name-in-module="DAC" offset="0x00" address-space="data"
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caption="Digital-to-Analog Converter"/>
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</instance>
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</module>
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<module name="CPU">
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<instance name="CPU" caption="CPU Registers">
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<register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data"
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caption="CPU Registers"/>
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<parameters>
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<param name="CORE_VERSION" value="V2E"/>
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</parameters>
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</instance>
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</module>
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<module name="TC8">
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<instance name="TC0" caption="Timer/Counter, 8-bit">
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<register-group name="TC0" name-in-module="TC0" offset="0x00" address-space="data"
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caption="Timer/Counter, 8-bit"/>
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</instance>
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</module>
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<module name="TC16">
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<instance name="TC1" caption="Timer/Counter, 16-bit">
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<register-group name="TC1" name-in-module="TC1" offset="0x00" address-space="data"
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caption="Timer/Counter, 16-bit"/>
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</instance>
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</module>
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<module name="ADC">
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<instance name="ADC" caption="Analog-to-Digital Converter">
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<register-group name="ADC" name-in-module="ADC" offset="0x00" address-space="data"
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caption="Analog-to-Digital Converter"/>
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</instance>
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</module>
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<module name="USART">
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<instance name="USART" caption="USART">
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<register-group name="USART" name-in-module="USART" offset="0x00" address-space="data"
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caption="USART"/>
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</instance>
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</module>
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<module name="SPI">
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<instance name="SPI" caption="Serial Peripheral Interface">
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<register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data"
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caption="Serial Peripheral Interface"/>
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</instance>
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</module>
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<module name="WDT">
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<instance name="WDT" caption="Watchdog Timer">
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<register-group name="WDT" name-in-module="WDT" offset="0x00" address-space="data"
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caption="Watchdog Timer"/>
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</instance>
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</module>
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<module name="EXINT">
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<instance name="EXINT" caption="External Interrupts">
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<register-group name="EXINT" name-in-module="EXINT" offset="0x00" address-space="data"
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caption="External Interrupts"/>
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</instance>
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</module>
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<module name="EEPROM">
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<instance name="EEPROM" caption="EEPROM">
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<register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data"
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caption="EEPROM"/>
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</instance>
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</module>
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<module name="PSC">
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<instance name="PSC0" caption="Power Stage Controller">
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<register-group name="PSC0" name-in-module="PSC0" offset="0x00" address-space="data"
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caption="Power Stage Controller"/>
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</instance>
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<instance name="PSC2" caption="Power Stage Controller">
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<register-group name="PSC2" name-in-module="PSC2" offset="0x00" address-space="data"
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caption="Power Stage Controller"/>
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</instance>
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</module>
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<module name="FUSE">
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<instance name="FUSE" caption="Fuses">
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<register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses"
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caption="Fuses"/>
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</instance>
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</module>
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<module name="LOCKBIT">
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<instance name="LOCKBIT" caption="Lockbits">
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<register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits"
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caption="Lockbits"/>
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</instance>
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</module>
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</peripherals>
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<interrupts>
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<interrupt index="0" name="RESET"
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caption="External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset"/>
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<interrupt index="1" name="PSC2_CAPT" caption="PSC2 Capture Event"/>
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<interrupt index="2" name="PSC2_EC" caption="PSC2 End Cycle"/>
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<interrupt index="3" name="PSC1_CAPT" caption="PSC1 Capture Event"/>
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<interrupt index="4" name="PSC1_EC" caption="PSC1 End Cycle"/>
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<interrupt index="5" name="PSC0_CAPT" caption="PSC0 Capture Event"/>
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<interrupt index="6" name="PSC0_EC" caption="PSC0 End Cycle"/>
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<interrupt index="7" name="ANALOG_COMP_0" caption="Analog Comparator 0"/>
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<interrupt index="8" name="ANALOG_COMP_1" caption="Analog Comparator 1"/>
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<interrupt index="9" name="ANALOG_COMP_2" caption="Analog Comparator 2"/>
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<interrupt index="10" name="INT0" caption="External Interrupt Request 0"/>
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<interrupt index="11" name="TIMER1_CAPT" caption="Timer/Counter1 Capture Event"/>
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<interrupt index="12" name="TIMER1_COMPA" caption="Timer/Counter1 Compare Match A"/>
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<interrupt index="13" name="TIMER1_COMPB" caption="Timer/Counter Compare Match B"/>
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<interrupt index="14" name="RESERVED15" caption=""/>
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<interrupt index="15" name="TIMER1_OVF" caption="Timer/Counter1 Overflow"/>
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<interrupt index="16" name="TIMER0_COMPA" caption="Timer/Counter0 Compare Match A"/>
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<interrupt index="17" name="TIMER0_OVF" caption="Timer/Counter0 Overflow"/>
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<interrupt index="18" name="ADC" caption="ADC Conversion Complete"/>
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<interrupt index="19" name="INT1" caption="External Interrupt Request 1"/>
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<interrupt index="20" name="SPI_STC" caption="SPI Serial Transfer Complete"/>
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<interrupt index="21" name="USART_RX" caption="USART, Rx Complete"/>
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<interrupt index="22" name="USART_UDRE" caption="USART Data Register Empty"/>
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<interrupt index="23" name="USART_TX" caption="USART, Tx Complete"/>
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<interrupt index="24" name="INT2" caption="External Interrupt Request 2"/>
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<interrupt index="25" name="WDT" caption="Watchdog Timeout Interrupt"/>
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<interrupt index="26" name="EE_READY" caption="EEPROM Ready"/>
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<interrupt index="27" name="TIMER0_COMPB" caption="Timer Counter 0 Compare Match B"/>
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<interrupt index="28" name="INT3" caption="External Interrupt Request 3"/>
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<interrupt index="29" name="RESERVED30" caption=""/>
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<interrupt index="30" name="RESERVED31" caption=""/>
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<interrupt index="31" name="SPM_READY" caption="Store Program Memory Read"/>
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</interrupts>
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<interfaces>
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<interface name="ISP" type="isp"/>
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<interface name="HVPP" type="hvpp"/>
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<interface name="debugWIRE" type="dw"/>
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</interfaces>
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<property-groups>
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<property-group name="SIGNATURES">
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<property name="JTAGID" value="0x9383"/>
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<property name="SIGNATURE0" value="0x1e"/>
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<property name="SIGNATURE1" value="0x93"/>
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<property name="SIGNATURE2" value="0x83"/>
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</property-group>
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<property-group name="OCD">
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<property name="OCD_REVISION" value="1"/>
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<property name="OCD_DATAREG" value="0x31"/>
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<property name="PROGBASE" value="0x0000"/>
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</property-group>
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<property-group name="JTAG_INTERFACE">
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<property name="ALLOWFULLPAGESTREAM" value="0x00"/>
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</property-group>
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<property-group name="ISP_INTERFACE">
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<property name="IspEnterProgMode_timeout" value="200"/>
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<property name="IspEnterProgMode_stabDelay" value="100"/>
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<property name="IspEnterProgMode_cmdexeDelay" value="25"/>
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<property name="IspEnterProgMode_synchLoops" value="32"/>
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<property name="IspEnterProgMode_byteDelay" value="0"/>
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<property name="IspEnterProgMode_pollIndex" value="3"/>
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<property name="IspEnterProgMode_pollValue" value="0x53"/>
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<property name="IspLeaveProgMode_preDelay" value="1"/>
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<property name="IspLeaveProgMode_postDelay" value="1"/>
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<property name="IspChipErase_eraseDelay" value="45"/>
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<property name="IspChipErase_pollMethod" value="1"/>
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<property name="IspProgramFlash_mode" value="0x41"/>
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<property name="IspProgramFlash_blockSize" value="64"/>
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<property name="IspProgramFlash_delay" value="10"/>
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<property name="IspProgramFlash_cmd1" value="0x40"/>
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<property name="IspProgramFlash_cmd2" value="0x4C"/>
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<property name="IspProgramFlash_cmd3" value="0x00"/>
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<property name="IspProgramFlash_pollVal1" value="0x00"/>
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<property name="IspProgramFlash_pollVal2" value="0x00"/>
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<property name="IspProgramEeprom_mode" value="0x41"/>
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<property name="IspProgramEeprom_blockSize" value="4"/>
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<property name="IspProgramEeprom_delay" value="5"/>
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<property name="IspProgramEeprom_cmd1" value="0xC1"/>
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<property name="IspProgramEeprom_cmd2" value="0xC2"/>
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<property name="IspProgramEeprom_cmd3" value="0x00"/>
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<property name="IspProgramEeprom_pollVal1" value="0x00"/>
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<property name="IspProgramEeprom_pollVal2" value="0x00"/>
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<property name="IspReadFlash_blockSize" value="256"/>
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<property name="IspReadEeprom_blockSize" value="256"/>
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<property name="IspReadFuse_pollIndex" value="4"/>
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<property name="IspReadLock_pollIndex" value="4"/>
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<property name="IspReadSign_pollIndex" value="4"/>
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<property name="IspReadOsccal_pollIndex" value="4"/>
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</property-group>
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<property-group name="PP_INTERFACE">
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<property name="PpControlStack"
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value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
|
|
|
|
|
<property name="PpEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="PpEnterProgMode_progModeDelay" value="0"/>
|
|
|
|
|
<property name="PpEnterProgMode_latchCycles" value="5"/>
|
|
|
|
|
<property name="PpEnterProgMode_toggleVtg" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_powerOffDelay" value="15"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayMs" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayUs" value="0"/>
|
|
|
|
|
<property name="PpLeaveProgMode_stabDelay" value="15"/>
|
|
|
|
|
<property name="PpLeaveProgMode_resetDelay" value="15"/>
|
|
|
|
|
<property name="PpChipErase_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpChipErase_pollTimeout" value="10"/>
|
|
|
|
|
<property name="PpProgramFlash_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramFlash_mode" value="0x0D"/>
|
|
|
|
|
<property name="PpProgramFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramEeprom_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramEeprom_mode" value="0x05"/>
|
|
|
|
|
<property name="PpProgramEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramFuse_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramFuse_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramLock_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramLock_pollTimeout" value="5"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="ISP_INTERFACE_STK600">
|
|
|
|
|
<property name="IspEnterProgMode_timeout" value="200"/>
|
|
|
|
|
<property name="IspEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="IspEnterProgMode_cmdexeDelay" value="25"/>
|
|
|
|
|
<property name="IspEnterProgMode_synchLoops" value="32"/>
|
|
|
|
|
<property name="IspEnterProgMode_byteDelay" value="0"/>
|
|
|
|
|
<property name="IspEnterProgMode_pollIndex" value="3"/>
|
|
|
|
|
<property name="IspEnterProgMode_pollValue" value="0x53"/>
|
|
|
|
|
<property name="IspLeaveProgMode_preDelay" value="1"/>
|
|
|
|
|
<property name="IspLeaveProgMode_postDelay" value="1"/>
|
|
|
|
|
<property name="IspChipErase_eraseDelay" value="45"/>
|
|
|
|
|
<property name="IspChipErase_pollMethod" value="1"/>
|
|
|
|
|
<property name="IspProgramFlash_mode" value="0x41"/>
|
|
|
|
|
<property name="IspProgramFlash_blockSize" value="64"/>
|
|
|
|
|
<property name="IspProgramFlash_delay" value="6"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd1" value="0x40"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd2" value="0x4C"/>
|
|
|
|
|
<property name="IspProgramFlash_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramFlash_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_mode" value="0x41"/>
|
|
|
|
|
<property name="IspProgramEeprom_blockSize" value="4"/>
|
|
|
|
|
<property name="IspProgramEeprom_delay" value="5"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd1" value="0xC1"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd2" value="0xC2"/>
|
|
|
|
|
<property name="IspProgramEeprom_cmd3" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal1" value="0x00"/>
|
|
|
|
|
<property name="IspProgramEeprom_pollVal2" value="0x00"/>
|
|
|
|
|
<property name="IspReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="IspReadFuse_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadLock_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadSign_pollIndex" value="4"/>
|
|
|
|
|
<property name="IspReadOsccal_pollIndex" value="4"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="PP_INTERFACE_STK600">
|
|
|
|
|
<property name="PpControlStack"
|
|
|
|
|
value="0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00"/>
|
|
|
|
|
<property name="PpEnterProgMode_stabDelay" value="100"/>
|
|
|
|
|
<property name="PpEnterProgMode_progModeDelay" value="0"/>
|
|
|
|
|
<property name="PpEnterProgMode_latchCycles" value="5"/>
|
|
|
|
|
<property name="PpEnterProgMode_toggleVtg" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_powerOffDelay" value="15"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayMs" value="1"/>
|
|
|
|
|
<property name="PpEnterProgMode_resetDelayUs" value="0"/>
|
|
|
|
|
<property name="PpLeaveProgMode_stabDelay" value="15"/>
|
|
|
|
|
<property name="PpLeaveProgMode_resetDelay" value="15"/>
|
|
|
|
|
<property name="PpChipErase_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpChipErase_pollTimeout" value="10"/>
|
|
|
|
|
<property name="PpProgramFlash_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramFlash_mode" value="0x0D"/>
|
|
|
|
|
<property name="PpProgramFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadFlash_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramEeprom_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramEeprom_mode" value="0x05"/>
|
|
|
|
|
<property name="PpProgramEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpReadEeprom_blockSize" value="256"/>
|
|
|
|
|
<property name="PpProgramFuse_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramFuse_pollTimeout" value="5"/>
|
|
|
|
|
<property name="PpProgramLock_pulseWidth" value="0"/>
|
|
|
|
|
<property name="PpProgramLock_pollTimeout" value="5"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
</property-groups>
|
|
|
|
|
</device>
|
|
|
|
|
</devices>
|
|
|
|
|
<modules>
|
|
|
|
|
<module caption="Fuses" name="FUSE">
|
|
|
|
|
<register-group caption="Fuses" name="FUSE">
|
|
|
|
|
<register caption="" name="EXTENDED" offset="0x02" size="1" initval="0xF9">
|
|
|
|
|
<bitfield caption="PSC2 Reset Behavior" mask="0x80" name="PSC2RB"/>
|
|
|
|
|
<bitfield caption="PSC1 Reset Behavior" mask="0x40" name="PSC1RB"/>
|
|
|
|
|
<bitfield caption="PSC0 Reset Behavior" mask="0x20" name="PSC0RB"/>
|
|
|
|
|
<bitfield caption="PSCOUT Reset Value" mask="0x10" name="PSCRV"/>
|
|
|
|
|
<bitfield caption="Select Boot Size" mask="0x06" name="BOOTSZ" values="ENUM_BOOTSZ"/>
|
|
|
|
|
<bitfield caption="Select Reset Vector" mask="0x01" name="BOOTRST"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="HIGH" offset="0x01" size="1" initval="0xDF">
|
|
|
|
|
<bitfield caption="Reset Disabled (Enable PC6 as i/o pin)" mask="0x80" name="RSTDISBL"/>
|
|
|
|
|
<bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
|
|
|
|
|
<bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
|
|
|
|
|
<bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
|
|
|
|
|
<bitfield caption="Preserve EEPROM through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
|
|
|
|
|
<bitfield caption="Brown-out Detector Trigger Level" mask="0x07" name="BODLEVEL"
|
|
|
|
|
values="ENUM_BODLEVEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="LOW" offset="0x00" size="1" initval="0x62">
|
|
|
|
|
<bitfield caption="Divide clock by 8 internally" mask="0x80" name="CKDIV8"/>
|
|
|
|
|
<bitfield caption="Clock output on PORTB0" mask="0x40" name="CKOUT"/>
|
|
|
|
|
<bitfield caption="Select Clock Source" mask="0x3F" name="SUT_CKSEL" values="ENUM_SUT_CKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ENUM_SUT_CKSEL">
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms" name="EXTCLK_6CK_14CK_0MS"
|
|
|
|
|
value="0x00"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms" name="EXTCLK_6CK_14CK_4MS1"
|
|
|
|
|
value="0x10"/>
|
|
|
|
|
<value caption="Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms" name="EXTCLK_6CK_14CK_65MS"
|
|
|
|
|
value="0x20"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_0MS" value="0x02"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_4MS1" value="0x12"/>
|
|
|
|
|
<value caption="Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms"
|
|
|
|
|
name="INTRCOSC_8MHZ_6CK_14CK_65MS" value="0x22"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1" value="0x08"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS" value="0x18"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS" value="0x28"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1" value="0x38"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS" value="0x09"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS" value="0x19"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1" value="0x29"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS" value="0x39"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1" value="0x0A"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS" value="0x1A"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS" value="0x2A"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1" value="0x3A"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS" value="0x0B"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS" value="0x1B"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1" value="0x2B"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS" value="0x3B"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1" value="0x0C"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS" value="0x1C"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS" value="0x2C"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1" value="0x3C"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS" value="0x0D"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS" value="0x1D"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1" value="0x2D"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS" value="0x3D"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_258CK_14CK_4MS1" value="0x0E"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_258CK_14CK_65MS" value="0x1E"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_1KCK_14CK_0MS" value="0x2E"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1" value="0x3E"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_1KCK_14CK_65MS" value="0x0F"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_16KCK_14CK_0MS" value="0x1F"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1" value="0x2F"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"
|
|
|
|
|
name="EXTXOSC_8MHZ_XX_16KCK_14CK_65MS" value="0x3F"/>
|
|
|
|
|
<value caption="PLL clock 16 MHz; Rc. Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"
|
|
|
|
|
name="PLLCLK_16MHZ_1KCK_14CK_0MS" value="0x03"/>
|
|
|
|
|
<value caption="PLL clock 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms"
|
|
|
|
|
name="PLLCLK_16MHZ_1KCK_14CK_4MS1" value="0x13"/>
|
|
|
|
|
<value caption="PLL clock 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms"
|
|
|
|
|
name="PLLCLK_16MHZ_1KCK_14CK_65MS" value="0x23"/>
|
|
|
|
|
<value caption="PLL clock 16 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"
|
|
|
|
|
name="PLLCLK_16MHZ_16KCK_14CK_0MS" value="0x33"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 0 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTCLK_6KCK_14CK_0MS" value="0x01"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 4 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTCLK_6KCK_14CK_4MS" value="0x11"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 64 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTCLK_6KCK_14CK_64MS" value="0x21"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTXOSC_1KCK_14CK_0MS" value="0x05"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTXOSC_1KCK_14CK_4MS" value="0x15"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTXOSC_16KCK_14CK_4MS" value="0x25"/>
|
|
|
|
|
<value caption="PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"
|
|
|
|
|
name="PLLCLK_PLLIN_EXTXOSC_16KCK_14CK_64MS" value="0x35"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"
|
|
|
|
|
name="EXTXOSC_PLLIN_EXTXOSC_1KCK_14CK_0MS" value="0x04"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"
|
|
|
|
|
name="EXTXOSC_PLLIN_EXTXOSC_1KCK_14CK_4MS" value="0x14"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"
|
|
|
|
|
name="EXTXOSC_PLLIN_EXTXOSC_16KCK_14CK_4MS" value="0x24"/>
|
|
|
|
|
<value caption="Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"
|
|
|
|
|
name="EXTXOSC_PLLIN_EXTXOSC_16KCK_14CK_64MS" value="0x34"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BODLEVEL">
|
|
|
|
|
<value caption="Brown-out detection disabled" name="DISABLED" value="0x07"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=4.5 V" name="4V5" value="0x06"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=2.7 V" name="2V7" value="0x05"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=4.3 V" name="4V3" value="0x04"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=4.4 V" name="4V4" value="0x03"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=4.2 V" name="4V2" value="0x02"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=2.8 V" name="2V8" value="0x01"/>
|
|
|
|
|
<value caption="Brown-out detection at VCC=2.6 V" name="2V6" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BOOTSZ">
|
|
|
|
|
<value caption="Boot Flash size=128 words Boot address=$0F80" name="128W_0F80" value="0x03"/>
|
|
|
|
|
<value caption="Boot Flash size=256 words Boot address=$0F00" name="256W_0F00" value="0x02"/>
|
|
|
|
|
<value caption="Boot Flash size=512 words Boot address=$0E00" name="512W_0E00" value="0x01"/>
|
|
|
|
|
<value caption="Boot Flash size=1024 words Boot address=$0C00" name="1024W_0C00" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Lockbits" name="LOCKBIT">
|
|
|
|
|
<register-group caption="Lockbits" name="LOCKBIT">
|
|
|
|
|
<register caption="" name="LOCKBIT" offset="0x00" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
|
|
|
|
|
<bitfield caption="Boot Loader Protection Mode" mask="0x0C" name="BLB0" values="ENUM_BLB"/>
|
|
|
|
|
<bitfield caption="Boot Loader Protection Mode" mask="0x30" name="BLB1" values="ENUM_BLB2"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ENUM_LB">
|
|
|
|
|
<value caption="Further programming and verification disabled" name="PROG_VER_DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="Further programming disabled" name="PROG_DISABLED" value="0x02"/>
|
|
|
|
|
<value caption="No memory lock features enabled" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BLB">
|
|
|
|
|
<value caption="LPM and SPM prohibited in Application Section" name="LPM_SPM_DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="LPM prohibited in Application Section" name="LPM_DISABLE" value="0x01"/>
|
|
|
|
|
<value caption="SPM prohibited in Application Section" name="SPM_DISABLE" value="0x02"/>
|
|
|
|
|
<value caption="No lock on SPM and LPM in Application Section" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="ENUM_BLB2">
|
|
|
|
|
<value caption="LPM and SPM prohibited in Boot Section" name="LPM_SPM_DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="LPM prohibited in Boot Section" name="LPM_DISABLE" value="0x01"/>
|
|
|
|
|
<value caption="SPM prohibited in Boot Section" name="SPM_DISABLE" value="0x02"/>
|
|
|
|
|
<value caption="No lock on SPM and LPM in Boot Section" name="NO_LOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="I/O Port" name="PORT">
|
|
|
|
|
<register-group caption="I/O Port" name="PORTB">
|
|
|
|
|
<register caption="Port B Data Register" name="PORTB" offset="0x25" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port B Data Direction Register" name="DDRB" offset="0x24" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port B Input Pins" name="PINB" offset="0x23" size="1" mask="0xFF" ocd-rw="R"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="I/O Port" name="PORTD">
|
|
|
|
|
<register caption="Port D Data Register" name="PORTD" offset="0x2B" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port D Data Direction Register" name="DDRD" offset="0x2A" size="1" mask="0xFF"/>
|
|
|
|
|
<register caption="Port D Input Pins" name="PIND" offset="0x29" size="1" mask="0xFF" ocd-rw="R"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="I/O Port" name="PORTE">
|
|
|
|
|
<register caption="Port E Data Register" name="PORTE" offset="0x2E" size="1" mask="0x07"/>
|
|
|
|
|
<register caption="Port E Data Direction Register" name="DDRE" offset="0x2D" size="1" mask="0x07"/>
|
|
|
|
|
<register caption="Port E Input Pins" name="PINE" offset="0x2C" size="1" mask="0x07" ocd-rw="R"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Bootloader" name="BOOT_LOAD">
|
|
|
|
|
<register-group caption="Bootloader" name="BOOT_LOAD">
|
|
|
|
|
<register caption="Store Program Memory Control Register" name="SPMCSR" offset="0x57" size="1">
|
|
|
|
|
<bitfield caption="SPM Interrupt Enable" mask="0x80" name="SPMIE"/>
|
|
|
|
|
<bitfield caption="Read While Write Section Busy" mask="0x40" name="RWWSB"/>
|
|
|
|
|
<bitfield caption="Read While Write section read enable" mask="0x10" name="RWWSRE"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bit Set" mask="0x08" name="BLBSET"/>
|
|
|
|
|
<bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
|
|
|
|
|
<bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
|
|
|
|
|
<bitfield caption="Store Program Memory Enable" mask="0x01" name="SPMEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Extended USART" name="EUSART">
|
|
|
|
|
<register-group caption="Extended USART" name="EUSART">
|
|
|
|
|
<register caption="EUSART I/O Data Register" name="EUDR" offset="0xCE" size="1" mask="0xFF" ocd-rw="">
|
|
|
|
|
<bitfield caption="EUSART Extended data bits" mask="0xFF" name="EUDR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EUSART Control and Status Register A" name="EUCSRA" offset="0xC8" size="1">
|
|
|
|
|
<bitfield caption="EUSART Control and Status Register A Bits" mask="0xF0" name="UTxS"
|
|
|
|
|
values="COMM_TRANS_CHAR_SIZE"/>
|
|
|
|
|
<bitfield caption="EUSART Control and Status Register A Bits" mask="0x0F" name="URxS"
|
|
|
|
|
values="COMM_TRANS_CHAR_SIZE2"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EUSART Control Register B" name="EUCSRB" offset="0xC9" size="1">
|
|
|
|
|
<bitfield caption="EUSART Enable Bit" mask="0x10" name="EUSART"/>
|
|
|
|
|
<bitfield caption="EUSBS Enable Bit" mask="0x08" name="EUSBS"/>
|
|
|
|
|
<bitfield caption="Manchester Mode Bit" mask="0x02" name="EMCH"/>
|
|
|
|
|
<bitfield caption="Order Bit" mask="0x01" name="BODR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EUSART Status Register C" name="EUCSRC" offset="0xCA" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="Frame Error Manchester Bit" mask="0x08" name="FEM"/>
|
|
|
|
|
<bitfield caption="F1617 Bit" mask="0x04" name="F1617"/>
|
|
|
|
|
<bitfield caption="Stop Bits" mask="0x03" name="STP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Manchester Receiver Baud Rate Register" name="MUBRR" offset="0xCC" size="2">
|
|
|
|
|
<bitfield caption="Manchester Receiver Baud Rate Register Bits" mask="0xFFFF" name="MUBRR"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="COMM_TRANS_CHAR_SIZE">
|
|
|
|
|
<value caption="5-bit" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="6-bit" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="7-bit" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="8-bit" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="9-bit" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="13-bit" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
<value caption="14-bit" name="VAL_0x09" value="0x09"/>
|
|
|
|
|
<value caption="15-bit" name="VAL_0x0A" value="0x0A"/>
|
|
|
|
|
<value caption="16-bit" name="VAL_0x0B" value="0x0B"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x0C" value="0x0C"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x0D" value="0x0D"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x0E" value="0x0E"/>
|
|
|
|
|
<value caption="17-bit" name="VAL_0x0F" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="COMM_TRANS_CHAR_SIZE2">
|
|
|
|
|
<value caption="5-bit" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="6-bit" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="7-bit" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="8-bit" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="9-bit" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="13-bit" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
<value caption="14-bit" name="VAL_0x09" value="0x09"/>
|
|
|
|
|
<value caption="15-bit" name="VAL_0x0A" value="0x0A"/>
|
|
|
|
|
<value caption="16-bit" name="VAL_0x0B" value="0x0B"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x0C" value="0x0C"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x0D" value="0x0D"/>
|
|
|
|
|
<value caption="16 or 17" name="VAL_0x0E" value="0x0E"/>
|
|
|
|
|
<value caption="17-bit" name="VAL_0x0F" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Analog Comparator" name="AC">
|
|
|
|
|
<register-group caption="Analog Comparator" name="AC">
|
|
|
|
|
<register caption="Analog Comparator 0 Control Register" name="AC0CON" offset="0xAD" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Enable Bit" mask="0x80" name="AC0EN"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Interrupt Enable Bit" mask="0x40" name="AC0IE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Interrupt Select Bit" mask="0x30" name="AC0IS"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Multiplexer Register" mask="0x07" name="AC0M"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 1 Control Register" name="AC1CON" offset="0xAE" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Enable Bit" mask="0x80" name="AC1EN"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Enable Bit" mask="0x40" name="AC1IE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Select Bit" mask="0x30" name="AC1IS"
|
|
|
|
|
values="ANALOG_COMP_INTERRUPT"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Capture Enable Bit" mask="0x08" name="AC1ICE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Multiplexer Register" mask="0x07" name="AC1M"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 2 Control Register" name="AC2CON" offset="0xAF" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Enable Bit" mask="0x80" name="AC2EN"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Interrupt Enable Bit" mask="0x40" name="AC2IE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Interrupt Select Bit" mask="0x30" name="AC2IS"
|
|
|
|
|
values="ANALOG_COMP_INTERRUPT"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Multiplexer Register" mask="0x07" name="AC2M"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator Status Register" name="ACSR" offset="0x50" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="Analog Comparator Clock Divider" mask="0x80" name="ACCKDIV"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Interrupt Flag Bit" mask="0x40" name="AC2IF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Flag Bit" mask="0x20" name="AC1IF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Interrupt Flag Bit" mask="0x10" name="AC0IF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 2 Output Bit" mask="0x04" name="AC2O"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Output Bit" mask="0x02" name="AC1O"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Output Bit" mask="0x01" name="AC0O"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_COMP_INTERRUPT">
|
|
|
|
|
<value caption="Interrupt on Toggle" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on Falling Edge" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on Rising Edge" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Digital-to-Analog Converter" name="DAC">
|
|
|
|
|
<register-group caption="Digital-to-Analog Converter" name="DAC">
|
|
|
|
|
<register caption="DAC Data Register" name="DAC" offset="0xAB" size="2" ocd-rw="">
|
|
|
|
|
<bitfield caption="DAC Data Register Bits" mask="0xFFFF" name="DAC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="DAC Control Register" name="DACON" offset="0xAA" size="1">
|
|
|
|
|
<bitfield caption="DAC Auto Trigger Enable Bit" mask="0x80" name="DAATE"/>
|
|
|
|
|
<bitfield caption="DAC Trigger Selection Bits" mask="0x70" name="DATS"
|
|
|
|
|
values="ANALOG_DAC_AUTO_TRIGGER"/>
|
|
|
|
|
<bitfield caption="DAC Left Adjust" mask="0x04" name="DALA"/>
|
|
|
|
|
<bitfield caption="DAC Output Enable" mask="0x02" name="DAOE"/>
|
|
|
|
|
<bitfield caption="DAC Enable Bit" mask="0x01" name="DAEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_DAC_AUTO_TRIGGER">
|
|
|
|
|
<value caption="Analog Comparator 0" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Analog Comparator 1" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="External Interrupt Request 0" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Timer/Counter0 Compare Match A" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Timer/Counter0 Overflow" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Timer/Counter1 Compare Match B" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Timer/Counter1 Overflow" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Timer/Counter1 Capture Event" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="CPU Registers" name="CPU">
|
|
|
|
|
<register-group caption="CPU Registers" name="CPU">
|
|
|
|
|
<register caption="Status Register" name="SREG" offset="0x5F" size="1">
|
|
|
|
|
<bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
|
|
|
|
|
<bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
|
|
|
|
|
<bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
|
|
|
|
|
<bitfield caption="Sign Bit" mask="0x10" name="S"/>
|
|
|
|
|
<bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
|
|
|
|
|
<bitfield caption="Negative Flag" mask="0x04" name="N"/>
|
|
|
|
|
<bitfield caption="Zero Flag" mask="0x02" name="Z"/>
|
|
|
|
|
<bitfield caption="Carry Flag" mask="0x01" name="C"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Stack Pointer " name="SP" offset="0x5D" size="2" mask="0xFFFF"/>
|
|
|
|
|
<register caption="MCU Control Register" name="MCUCR" offset="0x55" size="1">
|
|
|
|
|
<bitfield caption="SPI Pin Select" mask="0x80" name="SPIPS"/>
|
|
|
|
|
<bitfield caption="Pull-up disable" mask="0x10" name="PUD"/>
|
|
|
|
|
<bitfield caption="Interrupt Vector Select" mask="0x02" name="IVSEL"/>
|
|
|
|
|
<bitfield caption="Interrupt Vector Change Enable" mask="0x01" name="IVCE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="MCU Status Register" name="MCUSR" offset="0x54" size="1">
|
|
|
|
|
<bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
|
|
|
|
|
<bitfield caption="Brown-out Reset Flag" mask="0x04" name="BORF"/>
|
|
|
|
|
<bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
|
|
|
|
|
<bitfield caption="Power-on reset flag" mask="0x01" name="PORF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Calibration Value" name="OSCCAL" offset="0x66" size="1" mask="0x7F"
|
|
|
|
|
ocd-rw="R">
|
|
|
|
|
<bitfield caption="Oscillator Calibration " mask="0xFF" name="OSCCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="CLKPR" offset="0x61" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="CLKPCE"/>
|
|
|
|
|
<bitfield caption="" mask="0x0F" name="CLKPS" values="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Sleep Mode Control Register" name="SMCR" offset="0x53" size="1">
|
|
|
|
|
<bitfield caption="Sleep Mode Select bits" mask="0x0E" name="SM" values="CPU_SLEEP_MODE_3BITS4"/>
|
|
|
|
|
<bitfield caption="Sleep Enable" mask="0x01" name="SE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Purpose IO Register 3" name="GPIOR3" offset="0x3B" size="1">
|
|
|
|
|
<bitfield caption="General Purpose IO Register 3 bis" mask="0xFF" name="GPIOR" lsb="30"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Purpose IO Register 2" name="GPIOR2" offset="0x3A" size="1">
|
|
|
|
|
<bitfield caption="General Purpose IO Register 2 bis" mask="0xFF" name="GPIOR" lsb="20"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Purpose IO Register 1" name="GPIOR1" offset="0x39" size="1">
|
|
|
|
|
<bitfield caption="General Purpose IO Register 1 bis" mask="0xFF" name="GPIOR" lsb="10"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Purpose IO Register 0" name="GPIOR0" offset="0x3E" size="1">
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 7" mask="0x80" name="GPIOR07"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 6" mask="0x40" name="GPIOR06"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 5" mask="0x20" name="GPIOR05"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 4" mask="0x10" name="GPIOR04"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 3" mask="0x08" name="GPIOR03"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 2" mask="0x04" name="GPIOR02"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 1" mask="0x02" name="GPIOR01"/>
|
|
|
|
|
<bitfield caption="General Purpose IO Register 0 bit 0" mask="0x01" name="GPIOR00"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PLL Control And Status Register" name="PLLCSR" offset="0x49" size="1">
|
|
|
|
|
<bitfield caption="PLL Factor" mask="0x04" name="PLLF"/>
|
|
|
|
|
<bitfield caption="PLL Enable" mask="0x02" name="PLLE"/>
|
|
|
|
|
<bitfield caption="PLL Lock Detector" mask="0x01" name="PLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Register" name="PRR" offset="0x64" size="1">
|
|
|
|
|
<bitfield caption="Power Reduction PSC2" mask="0x80" name="PRPSC2"/>
|
|
|
|
|
<bitfield caption="Power Reduction PSC1" mask="0x40" name="PRPSC1"/>
|
|
|
|
|
<bitfield caption="Power Reduction PSC0" mask="0x20" name="PRPSC0"/>
|
|
|
|
|
<bitfield caption="Power Reduction Timer/Counter1" mask="0x10" name="PRTIM1"/>
|
|
|
|
|
<bitfield caption="Power Reduction Timer/Counter0" mask="0x08" name="PRTIM0"/>
|
|
|
|
|
<bitfield caption="Power Reduction Serial Peripheral Interface" mask="0x04" name="PRSPI"/>
|
|
|
|
|
<bitfield caption="Power Reduction USART" mask="0x02" name="PRUSART0"/>
|
|
|
|
|
<bitfield caption="Power Reduction ADC" mask="0x01" name="PRADC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="CPU_CLK_PRESCALE_4_BITS_SMALL">
|
|
|
|
|
<value caption="1" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="2" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="4" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="8" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="16" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="32" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="64" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="128" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="256" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="CPU_SLEEP_MODE_3BITS4">
|
|
|
|
|
<value caption="Idle" name="IDLE" value="0x00"/>
|
|
|
|
|
<value caption="ADC Noise Reduction (If Available)" name="ADC" value="0x01"/>
|
|
|
|
|
<value caption="Power Down" name="PDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Standby" name="STDBY" value="0x06"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Oscillator Calibration Values" name="OSCCAL_VALUE_ADDRESSES">
|
|
|
|
|
<value value="0x00" caption="8.0 MHz" name="8_0_MHz"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Timer/Counter, 8-bit" name="TC8">
|
|
|
|
|
<register-group caption="Timer/Counter, 8-bit" name="TC0">
|
|
|
|
|
<register caption="Timer/Counter0 Interrupt Mask Register" name="TIMSK0" offset="0x6E" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Match B Interrupt Enable" mask="0x04"
|
|
|
|
|
name="OCIE0B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Match A Interrupt Enable" mask="0x02"
|
|
|
|
|
name="OCIE0A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Overflow Interrupt Enable" mask="0x01" name="TOIE0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0 Interrupt Flag register" name="TIFR0" offset="0x35" size="1"
|
|
|
|
|
ocd-rw="R">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Flag 0B" mask="0x04" name="OCF0B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare Flag 0A" mask="0x02" name="OCF0A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter0 Overflow Flag" mask="0x01" name="TOV0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter Control Register A" name="TCCR0A" offset="0x44" size="1">
|
|
|
|
|
<bitfield caption="Compare Output Mode, Phase Correct PWM Mode" mask="0xC0" name="COM0A"/>
|
|
|
|
|
<bitfield caption="Compare Output Mode, Fast PWm" mask="0x30" name="COM0B"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter Control Register B" name="TCCR0B" offset="0x45" size="1">
|
|
|
|
|
<bitfield caption="Force Output Compare A" mask="0x80" name="FOC0A"/>
|
|
|
|
|
<bitfield caption="Force Output Compare B" mask="0x40" name="FOC0B"/>
|
|
|
|
|
<bitfield caption="" mask="0x08" name="WGM02"/>
|
|
|
|
|
<bitfield caption="Clock Select" mask="0x07" name="CS0" values="CLK_SEL_3BIT_EXT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0" name="TCNT0" offset="0x46" size="1">
|
|
|
|
|
<bitfield caption="Timer Counter 0 value" mask="0xFF" name="TCNT0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0 Output Compare Register" name="OCR0A" offset="0x47" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare A" mask="0xFF" name="OCR0A"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter0 Output Compare Register" name="OCR0B" offset="0x48" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter0 Output Compare B" mask="0xFF" name="OCR0B"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
|
|
|
|
<bitfield caption="Timer1 Input Capture Selection Bit" mask="0x40" name="ICPSEL1"/>
|
|
|
|
|
<bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSR10"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
|
|
|
|
<value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Timer/Counter, 16-bit" name="TC16">
|
|
|
|
|
<register-group caption="Timer/Counter, 16-bit" name="TC1">
|
|
|
|
|
<register caption="Timer/Counter Interrupt Mask Register" name="TIMSK1" offset="0x6F" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter1 Input Capture Interrupt Enable" mask="0x20" name="ICIE1"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Output CompareB Match Interrupt Enable" mask="0x04"
|
|
|
|
|
name="OCIE1B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Output CompareA Match Interrupt Enable" mask="0x02"
|
|
|
|
|
name="OCIE1A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Overflow Interrupt Enable" mask="0x01" name="TOIE1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter Interrupt Flag register" name="TIFR1" offset="0x36" size="1"
|
|
|
|
|
ocd-rw="R">
|
|
|
|
|
<bitfield caption="Input Capture Flag 1" mask="0x20" name="ICF1"/>
|
|
|
|
|
<bitfield caption="Output Compare Flag 1B" mask="0x04" name="OCF1B"/>
|
|
|
|
|
<bitfield caption="Output Compare Flag 1A" mask="0x02" name="OCF1A"/>
|
|
|
|
|
<bitfield caption="Timer/Counter1 Overflow Flag" mask="0x01" name="TOV1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register A" name="TCCR1A" offset="0x80" size="1">
|
|
|
|
|
<bitfield caption="Compare Output Mode 1A, bits" mask="0xC0" name="COM1A"/>
|
|
|
|
|
<bitfield caption="Compare Output Mode 1B, bits" mask="0x30" name="COM1B"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x03" name="WGM1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register B" name="TCCR1B" offset="0x81" size="1">
|
|
|
|
|
<bitfield caption="Input Capture 1 Noise Canceler" mask="0x80" name="ICNC1"/>
|
|
|
|
|
<bitfield caption="Input Capture 1 Edge Select" mask="0x40" name="ICES1"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x18" name="WGM1" lsb="2"/>
|
|
|
|
|
<bitfield caption="Prescaler source of Timer/Counter 1" mask="0x07" name="CS1"
|
|
|
|
|
values="CLK_SEL_3BIT_EXT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Control Register C" name="TCCR1C" offset="0x82" size="1" ocd-rw="">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="FOC1A"/>
|
|
|
|
|
<bitfield caption="" mask="0x40" name="FOC1B"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Bytes" name="TCNT1" offset="0x84" size="2" mask="0xFFFF">
|
|
|
|
|
<bitfield caption="Timer/Counter1" mask="0xFFFF" name="TCNT1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1A" offset="0x88" size="2"
|
|
|
|
|
mask="0xFFFF"/>
|
|
|
|
|
<register caption="Timer/Counter1 Output Compare Register Bytes" name="OCR1B" offset="0x8A" size="2"
|
|
|
|
|
mask="0xFFFF"/>
|
|
|
|
|
<register caption="Timer/Counter1 Input Capture Register Bytes" name="ICR1" offset="0x86" size="2"
|
|
|
|
|
mask="0xFFFF">
|
|
|
|
|
<bitfield caption="Timer/Counter1 Input Capture" mask="0xFFFF" name="ICR1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x43" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
|
|
|
|
|
<bitfield caption="Prescaler Reset Timer/Counter1 and Timer/Counter0" mask="0x01" name="PSRSYNC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="CLK_SEL_3BIT_EXT">
|
|
|
|
|
<value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Running, CLK/64" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Running, CLK/256" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Running, CLK/1024" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Falling Edge" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Running, ExtClk Tn Rising Edge" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Analog-to-Digital Converter" name="ADC">
|
|
|
|
|
<register-group caption="Analog-to-Digital Converter" name="ADC">
|
|
|
|
|
<register caption="The ADC multiplexer Selection Register" name="ADMUX" offset="0x7C" size="1">
|
|
|
|
|
<bitfield caption="Reference Selection Bits" mask="0xC0" name="REFS" values="ANALOG_ADC_V_REF2"/>
|
|
|
|
|
<bitfield caption="Left Adjust Result" mask="0x20" name="ADLAR"/>
|
|
|
|
|
<bitfield caption="Analog Channel and Gain Selection Bits" mask="0x0F" name="MUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="The ADC Control and Status register" name="ADCSRA" offset="0x7A" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="ADC Enable" mask="0x80" name="ADEN"/>
|
|
|
|
|
<bitfield caption="ADC Start Conversion" mask="0x40" name="ADSC"/>
|
|
|
|
|
<bitfield caption="ADC Auto Trigger Enable" mask="0x20" name="ADATE"/>
|
|
|
|
|
<bitfield caption="ADC Interrupt Flag" mask="0x10" name="ADIF"/>
|
|
|
|
|
<bitfield caption="ADC Interrupt Enable" mask="0x08" name="ADIE"/>
|
|
|
|
|
<bitfield caption="ADC Prescaler Select Bits" mask="0x07" name="ADPS"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="ADC Data Register Bytes" name="ADC" offset="0x78" size="2" mask="0xFFFF">
|
|
|
|
|
<bitfield caption="ADC Data Register" mask="0xFFFF" name="ADC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="ADC Control and Status Register B" name="ADCSRB" offset="0x7B" size="1">
|
|
|
|
|
<bitfield caption="ADC High Speed Mode" mask="0x80" name="ADHSM"/>
|
|
|
|
|
<bitfield caption="ADC Auto Trigger Source" mask="0x0F" name="ADTS"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 0" name="DIDR0" offset="0x7E" size="1" mask="0xFF">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="ADC7D"/>
|
|
|
|
|
<bitfield caption="" mask="0x40" name="ADC6D"/>
|
|
|
|
|
<bitfield caption="" mask="0x20" name="ADC5D"/>
|
|
|
|
|
<bitfield caption="" mask="0x10" name="ADC4D"/>
|
|
|
|
|
<bitfield caption="" mask="0x08" name="ADC3D"/>
|
|
|
|
|
<bitfield caption="" mask="0x04" name="ADC2D"/>
|
|
|
|
|
<bitfield caption="" mask="0x02" name="ADC1D"/>
|
|
|
|
|
<bitfield caption="" mask="0x01" name="ADC0D"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Digital Input Disable Register 1" name="DIDR1" offset="0x7F" size="1">
|
|
|
|
|
<bitfield caption="" mask="0x20" name="ACMP0D"/>
|
|
|
|
|
<bitfield caption="" mask="0x10" name="AMP0PD"/>
|
|
|
|
|
<bitfield caption="" mask="0x08" name="AMP0ND"/>
|
|
|
|
|
<bitfield caption="" mask="0x04" name="ADC10D"/>
|
|
|
|
|
<bitfield caption="" mask="0x02" name="ADC9D"/>
|
|
|
|
|
<bitfield caption="" mask="0x01" name="ADC8D"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="AMP0CSR" offset="0x76" size="1">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="AMP0EN"/>
|
|
|
|
|
<bitfield caption="" mask="0x40" name="AMP0IS"/>
|
|
|
|
|
<bitfield caption="" mask="0x30" name="AMP0G"/>
|
|
|
|
|
<bitfield caption="" mask="0x03" name="AMP0TS"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="" name="AMP1CSR" offset="0x77" size="1">
|
|
|
|
|
<bitfield caption="" mask="0x80" name="AMP1EN"/>
|
|
|
|
|
<bitfield caption="" mask="0x40" name="AMP1IS"/>
|
|
|
|
|
<bitfield caption="" mask="0x30" name="AMP1G"/>
|
|
|
|
|
<bitfield caption="" mask="0x03" name="AMP1TS"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="ANALOG_ADC_V_REF2">
|
|
|
|
|
<value caption="AREF, Internal Vref turned off" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="AVCC with external capacitor at AREF pin" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Internal 2.56V Voltage Reference with external capacitor at AREF pin" name="VAL_0x03"
|
|
|
|
|
value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="USART" name="USART">
|
|
|
|
|
<register-group caption="USART" name="USART">
|
|
|
|
|
<register caption="USART I/O Data Register" name="UDR" offset="0xC6" size="1" ocd-rw="">
|
|
|
|
|
<bitfield caption="USART I/O Data" mask="0xFF" name="UDR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control and Status register A" name="UCSRA" offset="0xC0" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="USART Receive Complete" mask="0x80" name="RXC"/>
|
|
|
|
|
<bitfield caption="USART Transmitt Complete" mask="0x40" name="TXC"/>
|
|
|
|
|
<bitfield caption="USART Data Register Empty" mask="0x20" name="UDRE"/>
|
|
|
|
|
<bitfield caption="Framing Error" mask="0x10" name="FE"/>
|
|
|
|
|
<bitfield caption="Data Overrun" mask="0x08" name="DOR"/>
|
|
|
|
|
<bitfield caption="USART Parity Error" mask="0x04" name="UPE"/>
|
|
|
|
|
<bitfield caption="Double USART Transmission Bit" mask="0x02" name="U2X"/>
|
|
|
|
|
<bitfield caption="Multi-processor Communication Mode" mask="0x01" name="MPCM"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control an Status register B" name="UCSRB" offset="0xC1" size="1">
|
|
|
|
|
<bitfield caption="RX Complete Interrupt Enable" mask="0x80" name="RXCIE"/>
|
|
|
|
|
<bitfield caption="TX Complete Interrupt Enable" mask="0x40" name="TXCIE"/>
|
|
|
|
|
<bitfield caption="USART Data Register Empty Interrupt Enable" mask="0x20" name="UDRIE"/>
|
|
|
|
|
<bitfield caption="Receiver Enable" mask="0x10" name="RXEN"/>
|
|
|
|
|
<bitfield caption="Transmitter Enable" mask="0x08" name="TXEN"/>
|
|
|
|
|
<bitfield caption="Character Size" mask="0x04" name="UCSZ2"/>
|
|
|
|
|
<bitfield caption="Receive Data Bit 8" mask="0x02" name="RXB8"/>
|
|
|
|
|
<bitfield caption="Transmit Data Bit 8" mask="0x01" name="TXB8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Control an Status register C" name="UCSRC" offset="0xC2" size="1">
|
|
|
|
|
<bitfield caption="USART Mode Select" mask="0x40" name="UMSEL0"/>
|
|
|
|
|
<bitfield caption="Parity Mode Bits" mask="0x30" name="UPM" values="COMM_UPM_PARITY_MODE"/>
|
|
|
|
|
<bitfield caption="Stop Bit Select" mask="0x08" name="USBS" values="COMM_STOP_BIT_SEL"/>
|
|
|
|
|
<bitfield caption="Character Size Bits" mask="0x06" name="UCSZ"/>
|
|
|
|
|
<bitfield caption="Clock Polarity" mask="0x01" name="UCPOL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="USART Baud Rate Register" name="UBRR" offset="0xC4" size="2">
|
|
|
|
|
<bitfield caption="USART Baud Rate Register Bits" mask="0x0FFF" name="UBRR"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="COMM_UPM_PARITY_MODE">
|
|
|
|
|
<value caption="Disabled" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Reserved" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Enabled, Even Parity" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Enabled, Odd Parity" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="" name="COMM_STOP_BIT_SEL">
|
|
|
|
|
<value caption="1-bit" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="2-bit" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Serial Peripheral Interface" name="SPI">
|
|
|
|
|
<register-group caption="Serial Peripheral Interface" name="SPI">
|
|
|
|
|
<register caption="SPI Control Register" name="SPCR" offset="0x4C" size="1">
|
|
|
|
|
<bitfield caption="SPI Interrupt Enable" mask="0x80" name="SPIE"/>
|
|
|
|
|
<bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
|
|
|
|
|
<bitfield caption="Data Order" mask="0x20" name="DORD"/>
|
|
|
|
|
<bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
|
|
|
|
|
<bitfield caption="Clock polarity" mask="0x08" name="CPOL"/>
|
|
|
|
|
<bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
|
|
|
|
|
<bitfield caption="SPI Clock Rate Selects" mask="0x03" name="SPR" values="COMM_SCK_RATE_3BIT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="SPI Status Register" name="SPSR" offset="0x4D" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
|
|
|
|
|
<bitfield caption="Write Collision Flag" mask="0x40" name="WCOL"/>
|
|
|
|
|
<bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="SPI Data Register" name="SPDR" offset="0x4E" size="1" ocd-rw="">
|
|
|
|
|
<bitfield caption="SPI Data bits" mask="0xFF" name="SPD"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="COMM_SCK_RATE_3BIT">
|
|
|
|
|
<value caption="fosc/4" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="fosc/16" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="fosc/64" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="fosc/128" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="fosc/2" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="fosc/8" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="fosc/32" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="fosc/64" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Watchdog Timer" name="WDT">
|
|
|
|
|
<register-group caption="Watchdog Timer" name="WDT">
|
|
|
|
|
<register caption="Watchdog Timer Control Register" name="WDTCSR" offset="0x60" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="Watchdog Timeout Interrupt Flag" mask="0x80" name="WDIF"/>
|
|
|
|
|
<bitfield caption="Watchdog Timeout Interrupt Enable" mask="0x40" name="WDIE"/>
|
|
|
|
|
<bitfield caption="Watchdog Timer Prescaler Bits" mask="0x27" name="WDP"
|
|
|
|
|
values="WDOG_TIMER_PRESCALE_4BITS"/>
|
|
|
|
|
<bitfield caption="Watchdog Change Enable" mask="0x10" name="WDCE"/>
|
|
|
|
|
<bitfield caption="Watch Dog Enable" mask="0x08" name="WDE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="" name="WDOG_TIMER_PRESCALE_4BITS">
|
|
|
|
|
<value caption="Oscillator Cycles 2K" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Oscillator Cycles 4K" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Oscillator Cycles 8K" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Oscillator Cycles 16K" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
<value caption="Oscillator Cycles 32K" name="VAL_0x04" value="0x04"/>
|
|
|
|
|
<value caption="Oscillator Cycles 64K" name="VAL_0x05" value="0x05"/>
|
|
|
|
|
<value caption="Oscillator Cycles 128K" name="VAL_0x06" value="0x06"/>
|
|
|
|
|
<value caption="Oscillator Cycles 256K" name="VAL_0x07" value="0x07"/>
|
|
|
|
|
<value caption="Oscillator Cycles 512K" name="VAL_0x08" value="0x08"/>
|
|
|
|
|
<value caption="Oscillator Cycles 1024K" name="VAL_0x09" value="0x09"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="External Interrupts" name="EXINT">
|
|
|
|
|
<register-group caption="External Interrupts" name="EXINT">
|
|
|
|
|
<register caption="External Interrupt Control Register A" name="EICRA" offset="0x69" size="1">
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control Bit" mask="0xC0" name="ISC3"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control Bit" mask="0x30" name="ISC2"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control Bit" mask="0x0C" name="ISC1"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
<bitfield caption="External Interrupt Sense Control Bit" mask="0x03" name="ISC0"
|
|
|
|
|
values="INTERRUPT_SENSE_CONTROL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Interrupt Mask Register" name="EIMSK" offset="0x3D" size="1">
|
|
|
|
|
<bitfield caption="External Interrupt Request Enable" mask="0x07" name="INT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Interrupt Flag Register" name="EIFR" offset="0x3C" size="1" ocd-rw="R">
|
|
|
|
|
<bitfield caption="External Interrupt Flags" mask="0x07" name="INTF"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Interrupt Sense Control" name="INTERRUPT_SENSE_CONTROL">
|
|
|
|
|
<value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
|
|
|
|
|
<value caption="Any Logical Change of INTX" name="VAL_0x01" value="0x01"/>
|
|
|
|
|
<value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
|
|
|
|
|
<value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="EEPROM" name="EEPROM">
|
|
|
|
|
<register-group caption="EEPROM" name="EEPROM">
|
|
|
|
|
<register caption="EEPROM Read/Write Access Bytes" name="EEAR" offset="0x41" size="2" mask="0x0FFF">
|
|
|
|
|
<bitfield caption="EEPROM Address bytes" mask="0x0FFF" name="EEAR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EEPROM Data Register" name="EEDR" offset="0x40" size="1">
|
|
|
|
|
<bitfield caption="EEPROM Data Bits" mask="0xFF" name="EEDR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EEPROM Control Register" name="EECR" offset="0x3F" size="1">
|
|
|
|
|
<bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM"/>
|
|
|
|
|
<bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
|
|
|
|
|
<bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMWE"/>
|
|
|
|
|
<bitfield caption="EEPROM Write Enable" mask="0x02" name="EEWE"/>
|
|
|
|
|
<bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module caption="Power Stage Controller" name="PSC">
|
|
|
|
|
<register-group caption="Power Stage Controller" name="PSC0">
|
|
|
|
|
<register caption="PSC 0 Input Capture Register " name="PICR0" offset="0xDE" size="2" mask="0x8FFF">
|
|
|
|
|
<bitfield caption="PSC 0 Input Capture Software Trig" mask="0x8000" name="PCST0"/>
|
|
|
|
|
<bitfield caption="PSC 0 Input Capture Bytes" mask="0x0FFF" name="PICR0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PSC 0 Input B Control" name="PFRC0B" offset="0xDD" size="1">
|
|
|
|
|
<bitfield caption="PSC 0 Capture Enable Input Part B" mask="0x80" name="PCAE0B"/>
|
|
|
|
|
<bitfield caption="PSC 0 Input Select for Part B" mask="0x40" name="PISEL0B"/>
|
|
|
|
|
<bitfield caption="PSC 0 Edge Level Selector on Input Part B" mask="0x20" name="PELEV0B"/>
|
|
|
|
|
<bitfield caption="PSC 0 Filter Enable on Input Part B" mask="0x10" name="PFLTE0B"/>
|
|
|
|
|
<bitfield caption="PSC 0 Retrigger and Fault Mode for Part B" mask="0x0F" name="PRFM0B"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PSC 0 Input A Control" name="PFRC0A" offset="0xDC" size="1">
|
|
|
|
|
<bitfield caption="PSC 0 Capture Enable Input Part A" mask="0x80" name="PCAE0A"/>
|
|
|
|
|
<bitfield caption="PSC 0 Input Select for Part A" mask="0x40" name="PISEL0A"/>
|
|
|
|
|
<bitfield caption="PSC 0 Edge Level Selector on Input Part A" mask="0x20" name="PELEV0A"/>
|
|
|
|
|
<bitfield caption="PSC 0 Filter Enable on Input Part A" mask="0x10" name="PFLTE0A"/>
|
|
|
|
|
<bitfield caption="PSC 0 Retrigger and Fault Mode for Part A" mask="0x0F" name="PRFM0A"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PSC 0 Control Register" name="PCTL0" offset="0xDB" size="1">
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<bitfield caption="PSC 0 Prescaler Selects" mask="0xC0" name="PPRE0"/>
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<bitfield caption="PSC 0 Balance Flank Width Modulation" mask="0x20" name="PBFM0"/>
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<bitfield caption="PSC 0 Asynchronous Output Control B" mask="0x10" name="PAOC0B"/>
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<bitfield caption="PSC 0 Asynchronous Output Control A" mask="0x08" name="PAOC0A"/>
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<bitfield caption="PSC0 Auto Run" mask="0x04" name="PARUN0"/>
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<bitfield caption="PSC0 Complete Cycle" mask="0x02" name="PCCYC0"/>
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<bitfield caption="PSC 0 Run" mask="0x01" name="PRUN0"/>
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</register>
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<register caption="PSC 0 Configuration Register" name="PCNF0" offset="0xDA" size="1">
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<bitfield caption="PSC 0 Fifty" mask="0x80" name="PFIFTY0"/>
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<bitfield caption="PSC 0 Autolock" mask="0x40" name="PALOCK0"/>
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<bitfield caption="PSC 0 Lock" mask="0x20" name="PLOCK0"/>
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<bitfield caption="PSC 0 Mode" mask="0x18" name="PMODE0"/>
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<bitfield caption="PSC 0 Output Polarity" mask="0x04" name="POP0"/>
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<bitfield caption="PSC 0 Input Clock Select" mask="0x02" name="PCLKSEL0"/>
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</register>
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<register caption="Output Compare 0 RB Register" name="OCR0RB" offset="0xD8" size="2">
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<bitfield caption="Output Compare RB" mask="0xFFFF" name="OCR0RB"/>
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</register>
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<register caption="Output Compare 0 SB Register" name="OCR0SB" offset="0xD6" size="2">
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<bitfield caption="Output Compare SB" mask="0x0FFF" name="OCR0SB"/>
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</register>
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<register caption="Output Compare 0 RA Register" name="OCR0RA" offset="0xD4" size="2">
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<bitfield caption="Output Compare RA" mask="0x0FFF" name="OCR0RA"/>
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</register>
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<register caption="Output Compare 0 SA Register" name="OCR0SA" offset="0xD2" size="2">
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<bitfield caption="Output Compare SA" mask="0x0FFF" name="OCR0SA"/>
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</register>
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<register caption="PSC0 Synchro and Output Configuration" name="PSOC0" offset="0xD0" size="1">
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<bitfield caption="Synchronization Out for ADC Selection" mask="0x30" name="PSYNC0"/>
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<bitfield caption="PSCOUT01 Output Enable" mask="0x04" name="POEN0B"/>
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<bitfield caption="PSCOUT00 Output Enable" mask="0x01" name="POEN0A"/>
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</register>
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<register caption="PSC0 Interrupt Mask Register" name="PIM0" offset="0xA1" size="1">
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<bitfield caption="PSC 0 Synchro Error Interrupt Enable" mask="0x20" name="PSEIE0"/>
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<bitfield caption="External Event B Interrupt Enable" mask="0x10" name="PEVE0B"/>
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<bitfield caption="External Event A Interrupt Enable" mask="0x08" name="PEVE0A"/>
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<bitfield caption="End of Cycle Interrupt Enable" mask="0x01" name="PEOPE0"/>
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</register>
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<register caption="PSC0 Interrupt Flag Register" name="PIFR0" offset="0xA0" size="1">
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<bitfield caption="PSC 0 Output A Activity" mask="0x80" name="POAC0B"/>
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<bitfield caption="PSC 0 Output A Activity" mask="0x40" name="POAC0A"/>
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<bitfield caption="PSC 0 Synchro Error Interrupt" mask="0x20" name="PSEI0"/>
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<bitfield caption="External Event B Interrupt" mask="0x10" name="PEV0B"/>
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<bitfield caption="External Event A Interrupt" mask="0x08" name="PEV0A"/>
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<bitfield caption="Ramp Number" mask="0x06" name="PRN0"/>
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<bitfield caption="End of PSC0 Interrupt" mask="0x01" name="PEOP0"/>
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</register>
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</register-group>
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<register-group caption="Power Stage Controller" name="PSC2">
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<register caption="PSC 2 Input Capture Register " name="PICR2" offset="0xFE" size="2">
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<bitfield caption="PSC 2 Input Capture Software Trig" mask="0x8000" name="PCST2"/>
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<bitfield caption="PSC 2 Input Capture Bytes" mask="0x0FFF" name="PICR2"/>
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</register>
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<register caption="PSC 2 Input B Control" name="PFRC2B" offset="0xFD" size="1">
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<bitfield caption="PSC 2 Capture Enable Input Part B" mask="0x80" name="PCAE2B"/>
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<bitfield caption="PSC 2 Input Select for Part B" mask="0x40" name="PISEL2B"/>
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<bitfield caption="PSC 2 Edge Level Selector on Input Part B" mask="0x20" name="PELEV2B"/>
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<bitfield caption="PSC 2 Filter Enable on Input Part B" mask="0x10" name="PFLTE2B"/>
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<bitfield caption="PSC 2 Retrigger and Fault Mode for Part B" mask="0x0F" name="PRFM2B"/>
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</register>
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<register caption="PSC 2 Input B Control" name="PFRC2A" offset="0xFC" size="1">
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<bitfield caption="PSC 2 Capture Enable Input Part A" mask="0x80" name="PCAE2A"/>
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<bitfield caption="PSC 2 Input Select for Part A" mask="0x40" name="PISEL2A"/>
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<bitfield caption="PSC 2 Edge Level Selector on Input Part A" mask="0x20" name="PELEV2A"/>
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<bitfield caption="PSC 2 Filter Enable on Input Part A" mask="0x10" name="PFLTE2A"/>
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<bitfield caption="PSC 2 Retrigger and Fault Mode for Part A" mask="0x0F" name="PRFM2A"/>
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</register>
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<register caption="PSC 2 Control Register" name="PCTL2" offset="0xFB" size="1">
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<bitfield caption="PSC 2 Prescaler Selects" mask="0xC0" name="PPRE2"/>
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<bitfield caption="Balance Flank Width Modulation" mask="0x20" name="PBFM2"/>
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<bitfield caption="PSC 2 Asynchronous Output Control B" mask="0x10" name="PAOC2B"/>
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<bitfield caption="PSC 2 Asynchronous Output Control A" mask="0x08" name="PAOC2A"/>
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<bitfield caption="PSC2 Auto Run" mask="0x04" name="PARUN2"/>
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<bitfield caption="PSC2 Complete Cycle" mask="0x02" name="PCCYC2"/>
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<bitfield caption="PSC 2 Run" mask="0x01" name="PRUN2"/>
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</register>
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<register caption="PSC 2 Configuration Register" name="PCNF2" offset="0xFA" size="1">
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<bitfield caption="PSC 2 Fifty" mask="0x80" name="PFIFTY2"/>
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<bitfield caption="PSC 2 Autolock" mask="0x40" name="PALOCK2"/>
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<bitfield caption="PSC 2 Lock" mask="0x20" name="PLOCK2"/>
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<bitfield caption="PSC 2 Mode" mask="0x18" name="PMODE2"/>
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<bitfield caption="PSC 2 Output Polarity" mask="0x04" name="POP2"/>
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<bitfield caption="PSC 2 Input Clock Select" mask="0x02" name="PCLKSEL2"/>
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<bitfield caption="PSC 2 Output Matrix Enable" mask="0x01" name="POME2"/>
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|
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</register>
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|
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|
|
<register caption="Output Compare 2 RB Register" name="OCR2RB" offset="0xF8" size="2">
|
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|
|
<bitfield caption="Output Compare RB" mask="0xFFFF" name="OCR2RB"/>
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|
|
</register>
|
|
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|
|
<register caption="Output Compare 2 SB Register" name="OCR2SB" offset="0xF6" size="2">
|
|
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|
|
<bitfield caption="Output Compare SB" mask="0x0FFF" name="OCR2SB"/>
|
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|
|
</register>
|
|
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|
|
<register caption="Output Compare 2 RA Register" name="OCR2RA" offset="0xF4" size="2">
|
|
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|
|
<bitfield caption="Output Compare RA" mask="0x0FFF" name="OCR2RA"/>
|
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|
|
</register>
|
|
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|
|
<register caption="Output Compare 2 SA Register" name="OCR2SA" offset="0xF2" size="2">
|
|
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|
|
<bitfield caption="Output Compare SA" mask="0x0FFF" name="OCR2SA"/>
|
|
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|
|
</register>
|
|
|
|
|
<register caption="PSC 2 Output Matrix" name="POM2" offset="0xF1" size="1">
|
|
|
|
|
<bitfield caption="Output Matrix Output B Ramps" mask="0xF0" name="POMV2B"/>
|
|
|
|
|
<bitfield caption="Output Matrix Output A Ramps" mask="0x0F" name="POMV2A"/>
|
|
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|
|
</register>
|
|
|
|
|
<register caption="PSC2 Synchro and Output Configuration" name="PSOC2" offset="0xF0" size="1">
|
|
|
|
|
<bitfield caption="PSC 2 Output 23 Select" mask="0xC0" name="POS2" lsb="2"/>
|
|
|
|
|
<bitfield caption="Synchronization Out for ADC Selection" mask="0x30" name="PSYNC2_"/>
|
|
|
|
|
<bitfield caption="PSCOUT23 Output Enable" mask="0x08" name="POEN2D"/>
|
|
|
|
|
<bitfield caption="PSCOUT21 Output Enable" mask="0x04" name="POEN2B"/>
|
|
|
|
|
<bitfield caption="PSCOUT22 Output Enable" mask="0x02" name="POEN2C"/>
|
|
|
|
|
<bitfield caption="PSCOUT20 Output Enable" mask="0x01" name="POEN2A"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PSC2 Interrupt Mask Register" name="PIM2" offset="0xA5" size="1">
|
|
|
|
|
<bitfield caption="PSC 2 Synchro Error Interrupt Enable" mask="0x20" name="PSEIE2"/>
|
|
|
|
|
<bitfield caption="External Event B Interrupt Enable" mask="0x10" name="PEVE2B"/>
|
|
|
|
|
<bitfield caption="External Event A Interrupt Enable" mask="0x08" name="PEVE2A"/>
|
|
|
|
|
<bitfield caption="End of Cycle Interrupt Enable" mask="0x01" name="PEOPE2"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="PSC2 Interrupt Flag Register" name="PIFR2" offset="0xA4" size="1">
|
|
|
|
|
<bitfield caption="PSC 2 Output A Activity" mask="0x80" name="POAC2B"/>
|
|
|
|
|
<bitfield caption="PSC 2 Output A Activity" mask="0x40" name="POAC2A"/>
|
|
|
|
|
<bitfield caption="PSC 2 Synchro Error Interrupt" mask="0x20" name="PSEI2"/>
|
|
|
|
|
<bitfield caption="External Event B Interrupt" mask="0x10" name="PEV2B"/>
|
|
|
|
|
<bitfield caption="External Event A Interrupt" mask="0x08" name="PEV2A"/>
|
|
|
|
|
<bitfield caption="Ramp Number" mask="0x06" name="PRN2"/>
|
|
|
|
|
<bitfield caption="End of PSC2 Interrupt" mask="0x01" name="PEOP2"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
</modules>
|
2021-05-31 01:01:14 +01:00
|
|
|
</target-description-file>
|
