2021-04-04 21:04:12 +01:00
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<?xml version="1.0" encoding="UTF-8"?>
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2021-05-31 01:01:14 +01:00
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<target-description-file>
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2021-04-04 21:04:12 +01:00
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<variants>
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<variant ordercode="ATxmega16E5-AU" package="TQFP32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="85"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATxmega16E5-MU" package="VQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="85"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATxmega16E5-M4U" package="UQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="85"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATxmega16E5-AN" package="TQFP32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATxmega16E5-MN" package="VQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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<variant ordercode="ATxmega16E5-M4N" package="UQFN32" pinout="QFP_QFN_32" speedmax="32000000" tempmax="105"
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tempmin="-40" vccmax="3.6" vccmin="1.6"/>
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</variants>
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2023-12-13 20:33:41 +00:00
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<device name="ATxmega16E5" family="AVR8" architecture="AVR8_XMEGA" avr-family="AVR XMEGA">
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2021-06-02 23:24:05 +01:00
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<address-spaces>
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<address-space name="prog" id="prog" start="0x00000" size="0x5000" endianness="little">
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<memory-segment start="0x00000" size="0x4000" type="flash" rw="RW" exec="1" name="APP_SECTION"
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pagesize="128"/>
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<memory-segment start="0x03000" size="0x1000" type="flash" rw="RW" exec="1" name="APPTABLE_SECTION"
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pagesize="128"/>
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<memory-segment start="0x04000" size="0x1000" type="flash" rw="RW" exec="1" name="BOOT_SECTION"
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pagesize="128"/>
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</address-space>
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<address-space name="data" id="data" start="0x0000" size="0x2800" endianness="little">
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<memory-segment start="0x0000" size="0x1000" type="io" rw="RW" exec="0" name="IO"/>
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<memory-segment start="0x1000" size="0x0200" type="eeprom" rw="RW" exec="0" name="MAPPED_EEPROM"/>
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<memory-segment start="0x2000" size="0x0800" type="ram" rw="RW" exec="0" name="INTERNAL_SRAM"/>
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</address-space>
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<address-space name="eeprom" id="eeprom" start="0x00000" size="0x0200">
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<memory-segment start="0x00000" size="0x0200" type="eeprom" rw="RW" exec="0" name="EEPROM"
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pagesize="32"/>
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</address-space>
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<address-space name="signatures" id="signatures" start="0x0000" size="0x0003">
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<memory-segment start="0x0000" size="0x0003" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
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</address-space>
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<address-space name="fuses" id="fuses" start="0x0000" size="0x0007">
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<memory-segment start="0x0000" size="0x0007" type="fuses" rw="RW" exec="0" name="FUSES"/>
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</address-space>
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<address-space name="lockbits" id="lockbits" start="0x0000" size="0x0001">
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<memory-segment start="0x0000" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
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</address-space>
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<address-space name="user_signatures" id="user_signatures" start="0x0000" size="0x0080">
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<memory-segment start="0x0000" size="0x0080" type="user_signatures" rw="RW" exec="0"
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name="USER_SIGNATURES" pagesize="128"/>
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</address-space>
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<address-space name="prod_signatures" id="prod_signatures" start="0x0000" size="0x0036">
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<memory-segment start="0x0000" size="0x0036" type="other" rw="R" exec="0" name="PROD_SIGNATURES"
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pagesize="128"/>
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</address-space>
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</address-spaces>
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<peripherals>
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<module name="GPIO" id="I6085" version="XMEGAD">
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<instance name="GPIO">
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<register-group address-space="data" offset="0x0000" name-in-module="GPIO" name="GPIO"/>
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</instance>
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</module>
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<module name="VPORT" id="I6075" version="XMEGAE">
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<instance name="VPORT0">
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<register-group address-space="data" offset="0x0010" name-in-module="VPORT" name="VPORT0"/>
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</instance>
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<instance name="VPORT1">
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<register-group address-space="data" offset="0x0014" name-in-module="VPORT" name="VPORT1"/>
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</instance>
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<instance name="VPORT2">
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<register-group address-space="data" offset="0x0018" name-in-module="VPORT" name="VPORT2"/>
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</instance>
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<instance name="VPORT3">
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<register-group address-space="data" offset="0x001C" name-in-module="VPORT" name="VPORT3"/>
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</instance>
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</module>
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<module name="XOCD" id="I6043">
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<instance name="OCD">
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<register-group address-space="data" offset="0x002E" name-in-module="OCD" name="OCD"/>
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</instance>
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</module>
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<module name="CPU" id="I6000">
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<instance name="CPU">
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<register-group address-space="data" offset="0x0030" name-in-module="CPU" name="CPU"/>
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<parameters>
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<param name="CORE_VERSION" value="V3XJ"/>
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</parameters>
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</instance>
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</module>
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<module name="CLK" id="I6073" version="XMEGAE">
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<instance name="CLK">
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<register-group address-space="data" offset="0x0040" name-in-module="CLK" name="CLK"/>
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<signals>
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<signal function="EXTERNAL_CLOCK" group="EXTCLK" pad="PC4"/>
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</signals>
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</instance>
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</module>
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<module name="PR" id="I6073" version="XMEGAE">
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<instance name="PR">
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<register-group address-space="data" offset="0x0070" name-in-module="PR" name="PR"/>
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</instance>
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</module>
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<module name="SLEEP" id="I6081" version="XMEGAAU">
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<instance name="SLEEP">
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<register-group address-space="data" offset="0x0048" name-in-module="SLEEP" name="SLEEP"/>
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</instance>
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</module>
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<module name="OSC" id="I6079" version="XMEGAE">
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<instance name="OSC">
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<register-group address-space="data" offset="0x0050" name-in-module="OSC" name="OSC"/>
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<signals>
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<signal function="XTAL" group="XTAL2" pad="PR0"/>
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<signal function="XTAL" group="XTAL1" pad="PR1"/>
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<signal function="TOSC" group="TOSC2" pad="PR0"/>
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<signal function="TOSC" group="TOSC1" pad="PR1"/>
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</signals>
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</instance>
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</module>
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<module name="DFLL" id="I6055" version="XMEGAAU">
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<instance name="DFLLRC32M">
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<register-group address-space="data" offset="0x0060" name-in-module="DFLL" name="DFLLRC32M"/>
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</instance>
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</module>
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<module name="RST" id="I6083" version="XMEGAAU">
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<instance name="RST">
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<register-group address-space="data" offset="0x0078" name-in-module="RST" name="RST"/>
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</instance>
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</module>
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<module name="WDT" id="I6078">
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<instance name="WDT">
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<register-group address-space="data" offset="0x0080" name-in-module="WDT" name="WDT"/>
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</instance>
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</module>
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<module name="MCU" id="I6091" version="XMEGAE">
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<instance name="MCU">
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<register-group address-space="data" offset="0x0090" name-in-module="MCU" name="MCU"/>
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</instance>
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</module>
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<module name="PMIC" id="I6057">
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<instance name="PMIC">
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<register-group address-space="data" offset="0x00A0" name-in-module="PMIC" name="PMIC"/>
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</instance>
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</module>
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<module name="PORTCFG" id="I6075" version="XMEGAE">
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<instance name="PORTCFG">
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<register-group address-space="data" offset="0x00B0" name-in-module="PORTCFG" name="PORTCFG"/>
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<signals>
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<signal field="CLKOUT" function="CLKOUTD" group="CLKOUT" pad="PD7"/>
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<signal field="CLKEVPIN" function="CLKOUTD_ALT" group="CLKOUT" pad="PD4"/>
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<signal field="CLKOUT" function="CLKOUTR" group="CLKOUT" pad="PR0"/>
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<signal field="EVOUT" function="EVOUTD" group="EVOUT" pad="PD7"/>
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<signal field="CLKEVPIN" function="EVOUTD_ALT" group="EVOUT" pad="PD4"/>
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<signal field="EVOUT" function="EVOUTR" group="EVOUT" pad="PR0"/>
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<signal field="RTCOUT" function="RTCOUTD" group="RTCOUT" pad="PD6"/>
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<signal field="RTCOUT" function="RTCOUTR" group="RTCOUT" pad="PR0"/>
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</signals>
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</instance>
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</module>
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<module name="CRC" id="I6111" version="XMEGAAU">
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<instance name="CRC">
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<register-group address-space="data" offset="0x0D0" name-in-module="CRC" name="CRC"/>
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</instance>
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</module>
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<module name="EDMA" id="I3002" version="XMEGAE">
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<instance name="EDMA">
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<register-group address-space="data" offset="0x0100" name-in-module="EDMA" name="EDMA"/>
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</instance>
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</module>
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<module name="EVSYS" id="I6061" version="XMEGAE">
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<instance name="EVSYS">
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<register-group address-space="data" offset="0x0180" name-in-module="EVSYS" name="EVSYS"/>
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</instance>
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</module>
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<module name="NVM" id="I3620" version="XMEGAE">
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<instance name="NVM">
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<register-group address-space="data" offset="0x01C0" name-in-module="NVM" name="NVM"/>
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</instance>
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</module>
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<module name="ADC" id="I6110" version="XMEGAE">
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<instance name="ADCA">
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<register-group address-space="data" offset="0x0200" name-in-module="ADC" name="ADCA"/>
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<signals>
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<signal function="ADC" group="ADC" index="0" pad="PA0"/>
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<signal function="ADC" group="ADC" index="1" pad="PA1"/>
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<signal function="ADC" group="ADC" index="2" pad="PA2"/>
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<signal function="ADC" group="ADC" index="3" pad="PA3"/>
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<signal function="ADC" group="ADC" index="4" pad="PA4"/>
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<signal function="ADC" group="ADC" index="5" pad="PA5"/>
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<signal function="ADC" group="ADC" index="6" pad="PA6"/>
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<signal function="ADC" group="ADC" index="7" pad="PA7"/>
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<signal function="ADC" group="ADC" index="8" pad="PD0"/>
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<signal function="ADC" group="ADC" index="9" pad="PD1"/>
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<signal function="ADC" group="ADC" index="10" pad="PD2"/>
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<signal function="ADC" group="ADC" index="11" pad="PD3"/>
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<signal function="ADC" group="ADC" index="12" pad="PD4"/>
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<signal function="ADC" group="ADC" index="13" pad="PD5"/>
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<signal function="ADC" group="ADC" index="14" pad="PD6"/>
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<signal function="ADC" group="ADC" index="15" pad="PD7"/>
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<signal function="AREF" group="REFA" index="0" pad="PA0"/>
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<signal function="AREF" group="REFD" index="0" pad="PD0"/>
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</signals>
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</instance>
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</module>
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<module name="DAC" id="I6059" version="XMEGAAU">
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<instance name="DACA">
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<register-group address-space="data" offset="0x0300" name-in-module="DAC" name="DACA"/>
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<signals>
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<signal function="DAC" group="DAC" index="0" pad="PA2"/>
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<signal function="DAC" group="DAC" index="1" pad="PA3"/>
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<signal function="AREF" group="REFA" index="0" pad="PA0"/>
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<signal function="AREF" group="REFD" index="0" pad="PD0"/>
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</signals>
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</instance>
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</module>
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<module name="AC" id="I6077" version="XMEGAE">
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<instance name="ACA">
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<register-group address-space="data" offset="0x0380" name-in-module="AC" name="ACA"/>
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<signals>
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<signal function="AC" group="AC" index="0" pad="PA0"/>
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<signal function="AC" group="AC" index="1" pad="PA1"/>
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<signal function="AC" group="AC" index="2" pad="PA2"/>
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<signal function="AC" group="AC" index="3" pad="PA3"/>
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<signal function="AC" group="AC" index="4" pad="PA4"/>
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<signal function="AC" group="AC" index="5" pad="PA5"/>
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<signal function="AC" group="AC" index="6" pad="PA6"/>
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<signal function="AC" group="AC" index="7" pad="PA7"/>
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<signal field="ACOUT" function="ACOUT_PA" group="ACOUT" index="1" pad="PA6"/>
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<signal field="ACOUT" function="ACOUT_PA" group="ACOUT" index="0" pad="PA7"/>
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<signal field="ACOUT" function="ACOUT_PC" group="ACOUT" index="1" pad="PC6"/>
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<signal field="ACOUT" function="ACOUT_PC" group="ACOUT" index="0" pad="PC7"/>
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<signal field="ACOUT" function="ACOUT_PD" group="ACOUT" index="1" pad="PD6"/>
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<signal field="ACOUT" function="ACOUT_PD" group="ACOUT" index="0" pad="PD7"/>
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<signal field="ACOUT" function="ACOUT_PR" group="ACOUT" index="1" pad="PR0"/>
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<signal field="ACOUT" function="ACOUT_PR" group="ACOUT" index="0" pad="PR1"/>
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</signals>
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</instance>
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</module>
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<module name="RTC" id="I6093" version="XMEGAE">
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<instance name="RTC">
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<register-group address-space="data" offset="0x0400" name-in-module="RTC" name="RTC"/>
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</instance>
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</module>
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<module name="XCL" id="I3008">
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<instance name="XCL">
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<register-group address-space="data" offset="0x0460" name-in-module="XCL" name="XCL"/>
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<signals>
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<signal function="XCLIN_LSB_PC" group="IN" index="1" pad="PC0"/>
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<signal function="XCLIN_LSB_PC" group="IN" index="2" pad="PC1"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PC" group="IN" index="0" pad="PC2"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PC" group="IN" index="3" pad="PC3"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PC" group="IN" index="1" pad="PC4"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PC" group="IN" index="2" pad="PC5"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PC" group="IN" index="0" pad="PC6"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PC" group="IN" index="3" pad="PC7"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PD" group="IN" index="1" pad="PD0"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PD" group="IN" index="2" pad="PD1"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PD" group="IN" index="0" pad="PD2"/>
|
|
|
|
|
<signal function="XCLIN_LSB_PD" group="IN" index="3" pad="PD3"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PD" group="IN" index="1" pad="PD4"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PD" group="IN" index="2" pad="PD5"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PD" group="IN" index="0" pad="PD6"/>
|
|
|
|
|
<signal function="XCLIN_MSB_PD" group="IN" index="3" pad="PD7"/>
|
|
|
|
|
<signal function="XCLOUT_LSB_PC" group="OUT" index="0" pad="PC0"/>
|
|
|
|
|
<signal function="XCLOUT_MSB_PC" group="OUT" index="0" pad="PC4"/>
|
|
|
|
|
<signal function="XCLOUT_LSB_PD" group="OUT" index="0" pad="PD0"/>
|
|
|
|
|
<signal function="XCLOUT_LSB_PD" group="OUT" index="0" pad="PD4"/>
|
|
|
|
|
<signal function="XCL_OCOUT" group="OC" index="0" pad="PD2"/>
|
|
|
|
|
<signal function="XCL_OCOUT" group="OC" index="1" pad="PD3"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TWI" id="I6089" version="XMEGAE">
|
|
|
|
|
<instance name="TWIC">
|
|
|
|
|
<register-group address-space="data" offset="0x480" name-in-module="TWI" name="TWIC"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="TWI" group="SDA" pad="PC0"/>
|
|
|
|
|
<signal function="TWI" group="SCL" pad="PC1"/>
|
|
|
|
|
<signal function="TWI_BRIDGE" group="SDA" pad="PD0"/>
|
|
|
|
|
<signal function="TWI_BRIDGE" group="SCL" pad="PD1"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PORT" id="I6075" version="XMEGAE">
|
|
|
|
|
<instance name="PORTA">
|
|
|
|
|
<register-group address-space="data" offset="0x0600" name-in-module="PORT" name="PORTA"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="PORTA" group="P" index="0" pad="PA0"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="1" pad="PA1"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="2" pad="PA2"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="3" pad="PA3"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="4" pad="PA4"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="5" pad="PA5"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="6" pad="PA6"/>
|
|
|
|
|
<signal function="PORTA" group="P" index="7" pad="PA7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="PORTC">
|
|
|
|
|
<register-group address-space="data" offset="0x0640" name-in-module="PORT" name="PORTC"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="PORTC" group="P" index="0" pad="PC0"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="1" pad="PC1"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="2" pad="PC2"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="3" pad="PC3"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="4" pad="PC4"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="5" pad="PC5"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="6" pad="PC6"/>
|
|
|
|
|
<signal function="PORTC" group="P" index="7" pad="PC7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="PORTD">
|
|
|
|
|
<register-group address-space="data" offset="0x0660" name-in-module="PORT" name="PORTD"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="PORTD" group="P" index="0" pad="PD0"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="1" pad="PD1"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="2" pad="PD2"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="3" pad="PD3"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="4" pad="PD4"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="5" pad="PD5"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="6" pad="PD6"/>
|
|
|
|
|
<signal function="PORTD" group="P" index="7" pad="PD7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="PORTR">
|
|
|
|
|
<register-group address-space="data" offset="0x07E0" name-in-module="PORT" name="PORTR"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="PORTR" group="P" index="0" pad="PR0"/>
|
|
|
|
|
<signal function="PORTR" group="P" index="1" pad="PR1"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC" id="I3007" version="XMEGAE">
|
|
|
|
|
<instance name="TCC4">
|
|
|
|
|
<register-group address-space="data" offset="0x800" name-in-module="TC4" name="TCC4"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal field="TC4A" function="TC4" group="OC4A" pad="PC0"/>
|
|
|
|
|
<signal field="TC4B" function="TC4" group="OC4B" pad="PC1"/>
|
|
|
|
|
<signal field="TC4C" function="TC4" group="OC4C" pad="PC2"/>
|
|
|
|
|
<signal field="TC4D" function="TC4" group="OC4D" pad="PC3"/>
|
|
|
|
|
<signal field="TC4A" function="TC4_ALT" group="OC4A" pad="PC4"/>
|
|
|
|
|
<signal field="TC4B" function="TC4_ALT" group="OC4B" pad="PC5"/>
|
|
|
|
|
<signal field="TC4C" function="TC4_ALT" group="OC4C" pad="PC6"/>
|
|
|
|
|
<signal field="TC4D" function="TC4_ALT" group="OC4D" pad="PC7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCC5">
|
|
|
|
|
<register-group address-space="data" offset="0x840" name-in-module="TC5" name="TCC5"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="TC5" group="OC5A" pad="PC4"/>
|
|
|
|
|
<signal function="TC5" group="OC5B" pad="PC5"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="TCD5">
|
|
|
|
|
<register-group address-space="data" offset="0x940" name-in-module="TC5" name="TCD5"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="TC5" group="OC5A" pad="PD4"/>
|
|
|
|
|
<signal function="TC5" group="OC5B" pad="PD5"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FAULT" id="I3620" version="XMEGAE">
|
|
|
|
|
<instance name="FAULTC4">
|
|
|
|
|
<register-group address-space="data" offset="0x880" name-in-module="FAULT" name="FAULTC4"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="FAULTC5">
|
|
|
|
|
<register-group address-space="data" offset="0x890" name-in-module="FAULT" name="FAULTC5"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="WEX" id="I3007" version="XMEGAE">
|
|
|
|
|
<instance name="WEXC">
|
|
|
|
|
<register-group address-space="data" offset="0x8A0" name-in-module="WEX" name="WEXC"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="WEX" group="OC4ALS" pad="PC0"/>
|
|
|
|
|
<signal function="WEX" group="OC4AHS" pad="PC1"/>
|
|
|
|
|
<signal function="WEX" group="OC4BLS" pad="PC2"/>
|
|
|
|
|
<signal function="WEX" group="OC4BHS" pad="PC3"/>
|
|
|
|
|
<signal function="WEX" group="OC4CLS" pad="PC4"/>
|
|
|
|
|
<signal function="WEX" group="OC4CHS" pad="PC5"/>
|
|
|
|
|
<signal function="WEX" group="OC4DLS" pad="PC6"/>
|
|
|
|
|
<signal function="WEX" group="OC4DHS" pad="PC7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="HIRES" id="I3620" version="XMEGAE">
|
|
|
|
|
<instance name="HIRESC">
|
|
|
|
|
<register-group address-space="data" offset="0x8B0" name-in-module="HIRES" name="HIRESC"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="USART" id="I4000" version="XMEGAE">
|
|
|
|
|
<instance name="USARTC0">
|
|
|
|
|
<register-group address-space="data" offset="0x8C0" name-in-module="USART" name="USARTC0"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal field="USART0" function="USART" group="XCK" pad="PC1"/>
|
|
|
|
|
<signal field="USART0" function="USART" group="RXD" pad="PC2"/>
|
|
|
|
|
<signal field="USART0" function="USART" group="TXD" pad="PC3"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="XCK" pad="PC5"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="RXD" pad="PC6"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="TXD" pad="PC7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="USARTD0">
|
|
|
|
|
<register-group address-space="data" offset="0x9C0" name-in-module="USART" name="USARTD0"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal field="USART0" function="USART" group="XCK" pad="PD1"/>
|
|
|
|
|
<signal field="USART0" function="USART" group="RXD" pad="PD2"/>
|
|
|
|
|
<signal field="USART0" function="USART" group="TXD" pad="PD3"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="XCK" pad="PD5"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="RXD" pad="PD6"/>
|
|
|
|
|
<signal field="USART0" function="USART_ALT" group="TXD" pad="PD7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SPI" id="I6090" version="XMEGAE">
|
|
|
|
|
<instance name="SPIC">
|
|
|
|
|
<register-group address-space="data" offset="0x08E0" name-in-module="SPI" name="SPIC"/>
|
|
|
|
|
<signals>
|
|
|
|
|
<signal function="SPI" group="SS" pad="PC4"/>
|
|
|
|
|
<signal function="SPI" group="SCK" pad="PC5"/>
|
|
|
|
|
<signal function="SPI" group="MISO" pad="PC6"/>
|
|
|
|
|
<signal function="SPI" group="MOSI" pad="PC7"/>
|
|
|
|
|
</signals>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="IRCOM" id="I6090" version="XMEGAAU">
|
|
|
|
|
<instance name="IRCOM">
|
|
|
|
|
<register-group address-space="data" offset="0x8F8" name-in-module="IRCOM" name="IRCOM"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FUSE" id="I3620" version="XMEGAE">
|
|
|
|
|
<instance name="FUSE">
|
|
|
|
|
<register-group address-space="fuses" offset="0x00" name-in-module="NVM_FUSES" name="FUSE"/>
|
|
|
|
|
</instance>
|
|
|
|
|
<instance name="LOCKBIT">
|
|
|
|
|
<register-group address-space="lockbits" offset="0x00" name-in-module="NVM_LOCKBITS"
|
|
|
|
|
name="LOCKBIT"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SIGROW" id="I3620" version="XMEGAE">
|
|
|
|
|
<instance name="PROD_SIGNATURES">
|
|
|
|
|
<register-group address-space="prod_signatures" offset="0x00"
|
|
|
|
|
name-in-module="NVM_PROD_SIGNATURES" name="PROD_SIGNATURES"/>
|
|
|
|
|
</instance>
|
|
|
|
|
</module>
|
|
|
|
|
</peripherals>
|
|
|
|
|
<interrupts>
|
|
|
|
|
<interrupt-group index="1" module-instance="OSC" name-in-module="OSC"/>
|
|
|
|
|
<interrupt-group index="2" module-instance="PORTR" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="3" module-instance="EDMA" name-in-module="EDMA"/>
|
|
|
|
|
<interrupt-group index="7" module-instance="RTC" name-in-module="RTC"/>
|
|
|
|
|
<interrupt-group index="9" module-instance="PORTC" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="10" module-instance="TWIC" name-in-module="TWI"/>
|
|
|
|
|
<interrupt-group index="12" module-instance="TCC4" name-in-module="TC4"/>
|
|
|
|
|
<interrupt-group index="18" module-instance="TCC5" name-in-module="TC5"/>
|
|
|
|
|
<interrupt-group index="22" module-instance="SPIC" name-in-module="SPI"/>
|
|
|
|
|
<interrupt-group index="23" module-instance="USARTC0" name-in-module="USART"/>
|
|
|
|
|
<interrupt-group index="26" module-instance="NVM" name-in-module="NVM"/>
|
|
|
|
|
<interrupt-group index="28" module-instance="XCL" name-in-module="XCL"/>
|
|
|
|
|
<interrupt-group index="30" module-instance="PORTA" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="31" module-instance="ACA" name-in-module="AC"/>
|
|
|
|
|
<interrupt-group index="34" module-instance="ADCA" name-in-module="ADC"/>
|
|
|
|
|
<interrupt-group index="35" module-instance="PORTD" name-in-module="PORT"/>
|
|
|
|
|
<interrupt-group index="36" module-instance="TCD5" name-in-module="TC5"/>
|
|
|
|
|
<interrupt-group index="40" module-instance="USARTD0" name-in-module="USART"/>
|
|
|
|
|
</interrupts>
|
|
|
|
|
<interfaces>
|
|
|
|
|
<interface type="pdi" name="PDI"/>
|
|
|
|
|
</interfaces>
|
|
|
|
|
<property-groups>
|
|
|
|
|
<property-group name="SIGNATURES">
|
|
|
|
|
<property name="SIGNATURE0" value="0x1E"/>
|
|
|
|
|
<property name="SIGNATURE1" value="0x94"/>
|
|
|
|
|
<property name="SIGNATURE2" value="0x45"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
<property-group name="PDI_INTERFACE">
|
|
|
|
|
<property name="APP_SECTION_OFFSET" value="0x00800000"/>
|
|
|
|
|
<property name="APPTABLE_SECTION_OFFSET" value="0x00803000"/>
|
|
|
|
|
<property name="BOOT_SECTION_OFFSET" value="0x00804000"/>
|
|
|
|
|
<property name="DATAMEM_OFFSET" value="0x01000000"/>
|
|
|
|
|
<property name="EEPROM_OFFSET" value="0x008C0000"/>
|
|
|
|
|
<property name="USER_SIGNATURES_OFFSET" value="0x008E0400"/>
|
|
|
|
|
<property name="PROD_SIGNATURES_OFFSET" value="0x008E0200"/>
|
|
|
|
|
<property name="FUSE_REGISTERS_OFFSET" value="0x008F0020"/>
|
|
|
|
|
<property name="LOCK_REGISTERS_OFFSET" value="0x008F0027"/>
|
|
|
|
|
</property-group>
|
|
|
|
|
</property-groups>
|
|
|
|
|
</device>
|
2021-04-04 21:04:12 +01:00
|
|
|
<modules>
|
|
|
|
|
<module name="GPIO" id="I6085" version="XMEGAD" caption="General Purpose IO">
|
|
|
|
|
<register-group caption="General Purpose IO Registers" name="GPIO" size="4">
|
|
|
|
|
<register caption="General Purpose IO Register 0" name="GPIOR0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 1" name="GPIOR1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 2" name="GPIOR2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="General Purpose IO Register 3" name="GPIOR3" offset="0x03" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="VPORT" id="I6075" version="XMEGAE" caption="Virtual Ports">
|
|
|
|
|
<register-group caption="Virtual Port" name="VPORT" size="4">
|
|
|
|
|
<register caption="I/O Port Data Direction" name="DIR" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output" name="OUT" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="I/O Port Input" name="IN" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Pin 7 Flag" mask="0x80" name="INT7IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 6 Flag" mask="0x40" name="INT6IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 5 Flag" mask="0x20" name="INT5IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 4 Flag" mask="0x10" name="INT4IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 3 Flag" mask="0x08" name="INT3IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 2 Flag" mask="0x04" name="INT2IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 1 Flag" mask="0x02" name="INT1IF"/>
|
|
|
|
|
<bitfield caption="Interrupt Pin 0 Flag" mask="0x01" name="INT0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="XOCD" caption="On-Chip Debug System" id="I6043">
|
|
|
|
|
<register-group name="OCD" caption="On-Chip Debug System" size="2">
|
|
|
|
|
<register name="OCDR0" caption="OCD Register 0" size="1" offset="0x00">
|
|
|
|
|
<bitfield name="OCDRD" caption="OCDR Dirty" mask="0xFF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="OCDR1" caption="OCD Register 1" size="1" offset="0x01">
|
|
|
|
|
<bitfield name="OCDRD" caption="OCDR Dirty" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CPU" id="I6000" caption="CPU">
|
|
|
|
|
<register-group caption="CPU registerMap" name="CPU" size="16">
|
|
|
|
|
<register caption="Configuration Change Protection" name="CCP" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="CCP signature" mask="0xFF" name="CCP" values="CCP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Ramp D" name="RAMPD" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Ramp X" name="RAMPX" offset="0x09" size="1"/>
|
|
|
|
|
<register caption="Ramp Y" name="RAMPY" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Ramp Z" name="RAMPZ" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Extended Indirect Jump" name="EIND" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Stack Pointer Low" name="SPL" offset="0x0D" size="1"/>
|
|
|
|
|
<register caption="Stack Pointer High" name="SPH" offset="0x0E" size="1"/>
|
|
|
|
|
<register caption="Status Register" name="SREG" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="Global Interrupt Enable Flag" mask="0x80" name="I"/>
|
|
|
|
|
<bitfield caption="Transfer Bit" mask="0x40" name="T"/>
|
|
|
|
|
<bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
|
|
|
|
|
<bitfield caption="N Exclusive Or V Flag" mask="0x10" name="S"/>
|
|
|
|
|
<bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
|
|
|
|
|
<bitfield caption="Negative Flag" mask="0x04" name="N"/>
|
|
|
|
|
<bitfield caption="Zero Flag" mask="0x02" name="Z"/>
|
|
|
|
|
<bitfield caption="Carry Flag" mask="0x01" name="C"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="CCP signatures" name="CCP">
|
|
|
|
|
<value caption="SPM Instruction Protection" name="SPM" value="0x9D"/>
|
|
|
|
|
<value caption="IO Register Protection" name="IOREG" value="0xD8"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CLK" id="I6073" version="XMEGAE" caption="Clock System">
|
|
|
|
|
<register-group caption="Clock System" name="CLK" size="5">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="System Clock Selection" mask="0x07" name="SCLKSEL" values="CLK_SCLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Prescaler Control Register" name="PSCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Prescaler A Division Factor" mask="0x7C" name="PSADIV" values="CLK_PSADIV"/>
|
|
|
|
|
<bitfield caption="Prescaler B and C Division factor" mask="0x03" name="PSBCDIV"
|
|
|
|
|
values="CLK_PSBCDIV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Lock register" name="LOCK" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Clock System Lock" mask="0x01" name="LOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="RTC Control Register" name="RTCCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Clock Source" mask="0x0E" name="RTCSRC" values="CLK_RTCSRC"/>
|
|
|
|
|
<bitfield caption="Clock Source Enable" mask="0x01" name="RTCEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="System Clock Selection" name="CLK_SCLKSEL">
|
|
|
|
|
<value caption="Internal 2 MHz RC Oscillator" name="RC2M" value="0x00"/>
|
|
|
|
|
<value caption="Internal 32 MHz RC Oscillator" name="RC32M" value="0x01"/>
|
|
|
|
|
<value caption="Internal 32.768 kHz RC Oscillator" name="RC32K" value="0x02"/>
|
|
|
|
|
<value caption="External Crystal Oscillator or Clock" name="XOSC" value="0x03"/>
|
|
|
|
|
<value caption="Phase Locked Loop" name="PLL" value="0x04"/>
|
|
|
|
|
<value caption="Internal 8 MHz RC Oscillator" name="RC8M" value="0x05"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler A Division Factor" name="CLK_PSADIV">
|
|
|
|
|
<value caption="Divide by 1" name="1" value="0x00"/>
|
|
|
|
|
<value caption="Divide by 2" name="2" value="0x01"/>
|
|
|
|
|
<value caption="Divide by 4" name="4" value="0x03"/>
|
|
|
|
|
<value caption="Divide by 8" name="8" value="0x05"/>
|
|
|
|
|
<value caption="Divide by 16" name="16" value="0x07"/>
|
|
|
|
|
<value caption="Divide by 32" name="32" value="0x09"/>
|
|
|
|
|
<value caption="Divide by 64" name="64" value="0x0B"/>
|
|
|
|
|
<value caption="Divide by 128" name="128" value="0x0D"/>
|
|
|
|
|
<value caption="Divide by 256" name="256" value="0x0F"/>
|
|
|
|
|
<value caption="Divide by 512" name="512" value="0x11"/>
|
|
|
|
|
<value caption="Divide by 6" name="6" value="0x13"/>
|
|
|
|
|
<value caption="Divide by 10" name="10" value="0x15"/>
|
|
|
|
|
<value caption="Divide by 12" name="12" value="0x17"/>
|
|
|
|
|
<value caption="Divide by 24" name="24" value="0x19"/>
|
|
|
|
|
<value caption="Divide by 48" name="48" value="0x1B"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler B and C Division Factor" name="CLK_PSBCDIV">
|
|
|
|
|
<value caption="Divide B by 1 and C by 1" name="1_1" value="0x00"/>
|
|
|
|
|
<value caption="Divide B by 1 and C by 2" name="1_2" value="0x01"/>
|
|
|
|
|
<value caption="Divide B by 4 and C by 1" name="4_1" value="0x02"/>
|
|
|
|
|
<value caption="Divide B by 2 and C by 2" name="2_2" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="RTC Clock Source" name="CLK_RTCSRC">
|
|
|
|
|
<value caption="1.024 kHz from internal 32kHz ULP" name="ULP" value="0x00"/>
|
|
|
|
|
<value caption="1.024 kHz from 32.768 kHz crystal oscillator on TOSC" name="TOSC" value="0x01"/>
|
|
|
|
|
<value caption="1.024 kHz from internal 32.768 kHz RC oscillator" name="RCOSC" value="0x02"/>
|
|
|
|
|
<value caption="32.768 kHz from 32.768 kHz crystal oscillator on TOSC" name="TOSC32" value="0x05"/>
|
|
|
|
|
<value caption="32.768 kHz from internal 32.768 kHz RC oscillator" name="RCOSC32" value="0x06"/>
|
|
|
|
|
<value caption="External Clock from TOSC1" name="EXTCLK" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PR" id="I6073" version="XMEGAE" caption="Power Reduction">
|
|
|
|
|
<register-group caption="Power Reduction" name="PR" size="7">
|
|
|
|
|
<register caption="General Power Reduction" name="PRGEN" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="XMEGA Custom Logic" mask="0x80" name="XCL"/>
|
|
|
|
|
<bitfield caption="Real-time Counter" mask="0x04" name="RTC"/>
|
|
|
|
|
<bitfield caption="Event System" mask="0x02" name="EVSYS"/>
|
|
|
|
|
<bitfield caption="Enhanced DMA-Controller" mask="0x01" name="EDMA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port A" name="PRPA" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Port A DAC" mask="0x04" name="DAC"/>
|
|
|
|
|
<bitfield caption="Port A ADC" mask="0x02" name="ADC"/>
|
|
|
|
|
<bitfield caption="Port A Analog Comparator" mask="0x01" name="AC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port C" name="PRPC" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Port C Two-wire Interface" mask="0x40" name="TWI"/>
|
|
|
|
|
<bitfield caption="Port C USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port C SPI" mask="0x08" name="SPI"/>
|
|
|
|
|
<bitfield caption="Port C WEX" mask="0x04" name="HIRES"/>
|
|
|
|
|
<bitfield caption="Port C Timer/Counter5" mask="0x02" name="TC5"/>
|
|
|
|
|
<bitfield caption="Port C Timer/Counter4" mask="0x01" name="TC4"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Power Reduction Port D" name="PRPD" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Port D USART0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Port D Timer/Counter5" mask="0x02" name="TC5"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SLEEP" id="I6081" version="XMEGAAU" caption="Sleep Controller">
|
|
|
|
|
<register-group caption="Sleep Controller" name="SLEEP" size="1">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Sleep Mode" mask="0x0E" name="SMODE" values="SLEEP_SMODE"/>
|
|
|
|
|
<bitfield caption="Sleep Enable" mask="0x01" name="SEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Sleep Mode" name="SLEEP_SMODE">
|
|
|
|
|
<value caption="Idle mode" name="IDLE" value="0x00"/>
|
|
|
|
|
<value caption="Power-down Mode" name="PDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Power-save Mode" name="PSAVE" value="0x03"/>
|
|
|
|
|
<value caption="Standby Mode" name="STDBY" value="0x06"/>
|
|
|
|
|
<value caption="Extended Standby Mode" name="ESTDBY" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="OSC" id="I6079" version="XMEGAE" caption="Oscillator">
|
|
|
|
|
<register-group caption="Oscillator" name="OSC" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Internal 8 MHz RC Low Power Mode Enable" mask="0x40" name="RC8MLPM"/>
|
|
|
|
|
<bitfield caption="Internal 8 MHz RC Oscillator Enable" mask="0x20" name="RC8MEN"/>
|
|
|
|
|
<bitfield caption="PLL Enable" mask="0x10" name="PLLEN"/>
|
|
|
|
|
<bitfield caption="External Oscillator Enable" mask="0x08" name="XOSCEN"/>
|
|
|
|
|
<bitfield caption="Internal 32.768 kHz RC Oscillator Enable" mask="0x04" name="RC32KEN"/>
|
|
|
|
|
<bitfield caption="Internal 32 MHz RC Oscillator Enable" mask="0x02" name="RC32MEN"/>
|
|
|
|
|
<bitfield caption="Internal 2 MHz RC Oscillator Enable" mask="0x01" name="RC2MEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Internal 8 MHz RC Oscillator Ready" mask="0x20" name="RC8MRDY"/>
|
|
|
|
|
<bitfield caption="PLL Ready" mask="0x10" name="PLLRDY"/>
|
|
|
|
|
<bitfield caption="External Oscillator Ready" mask="0x08" name="XOSCRDY"/>
|
|
|
|
|
<bitfield caption="Internal 32.768 kHz RC Oscillator Ready" mask="0x04" name="RC32KRDY"/>
|
|
|
|
|
<bitfield caption="Internal 32 MHz RC Oscillator Ready" mask="0x02" name="RC32MRDY"/>
|
|
|
|
|
<bitfield caption="Internal 2 MHz RC Oscillator Ready" mask="0x01" name="RC2MRDY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="External Oscillator Control Register" name="XOSCCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Frequency Range" mask="0xC0" name="FRQRANGE" values="OSC_FRQRANGE"/>
|
|
|
|
|
<bitfield caption="32.768 kHz XTAL OSC Low-power Mode" mask="0x20" name="X32KLPM"/>
|
|
|
|
|
<bitfield caption="16 MHz Crystal Oscillator High Power mode" mask="0x10" name="XOSCPWR"/>
|
|
|
|
|
<bitfield caption="External Oscillator Selection and Startup Time" mask="0x1F" name="XOSCSEL"
|
|
|
|
|
values="OSC_XOSCSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Failure Detection Register" name="XOSCFAIL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="PLL Failure Detection Interrupt Flag" mask="0x08" name="PLLFDIF"/>
|
|
|
|
|
<bitfield caption="PLL Failure Detection Enable" mask="0x04" name="PLLFDEN"/>
|
|
|
|
|
<bitfield caption="XOSC Failure Detection Interrupt Flag" mask="0x02" name="XOSCFDIF"/>
|
|
|
|
|
<bitfield caption="XOSC Failure Detection Enable" mask="0x01" name="XOSCFDEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="32.768 kHz Internal Oscillator Calibration Register" name="RC32KCAL" offset="0x04"
|
|
|
|
|
size="1"/>
|
|
|
|
|
<register caption="PLL Control Register" name="PLLCTRL" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Clock Source" mask="0xC0" name="PLLSRC" values="OSC_PLLSRC"/>
|
|
|
|
|
<bitfield caption="Divide by 2" mask="0x20" name="PLLDIV"/>
|
|
|
|
|
<bitfield caption="Multiplication Factor" mask="0x1F" name="PLLFAC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="DFLL Control Register" name="DFLLCTRL" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="32 MHz DFLL Calibration Reference" mask="0x06" name="RC32MCREF"
|
|
|
|
|
values="OSC_RC32MCREF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Internal 8 MHz RC Oscillator Calibration Register" name="RC8MCAL" offset="0x07"
|
|
|
|
|
size="1">
|
|
|
|
|
<bitfield caption="Calibration Bits" mask="0xFF" name="RC8MCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Oscillator Frequency Range" name="OSC_FRQRANGE">
|
|
|
|
|
<value caption="0.4 - 2 MHz" name="04TO2" value="0x00"/>
|
|
|
|
|
<value caption="2 - 9 MHz" name="2TO9" value="0x01"/>
|
|
|
|
|
<value caption="9 - 12 MHz" name="9TO12" value="0x02"/>
|
|
|
|
|
<value caption="12 - 16 MHz" name="12TO16" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="External Oscillator Selection and Startup Time" name="OSC_XOSCSEL">
|
|
|
|
|
<value caption="External Clock on port R1 - 6 CLK" name="EXTCLK" value="0x00"/>
|
|
|
|
|
<value caption="32.768 kHz TOSC - 32K CLK" name="32KHz" value="0x02"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 256 CLK" name="XTAL_256CLK" value="0x03"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 1K CLK" name="XTAL_1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="0.4-16 MHz XTAL - 16K CLK" name="XTAL_16KCLK" value="0x0B"/>
|
|
|
|
|
<value caption="External Clock on port C4 - 6 CLK" name="EXTCLK_C4" value="0x14"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="PLL Clock Source" name="OSC_PLLSRC">
|
|
|
|
|
<value caption="Internal 2 MHz RC Oscillator" name="RC2M" value="0x00"/>
|
|
|
|
|
<value caption="Internal 8 MHz RC Oscillator" name="RC8M" value="0x01"/>
|
|
|
|
|
<value caption="Internal 32 MHz RC Oscillator" name="RC32M" value="0x02"/>
|
|
|
|
|
<value caption="External Oscillator" name="XOSC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="32 MHz DFLL Calibration Reference" name="OSC_RC32MCREF">
|
|
|
|
|
<value caption="Internal 32.768 kHz RC Oscillator" name="RC32K" value="0x00"/>
|
|
|
|
|
<value caption="External 32.768 kHz Crystal Oscillator" name="XOSC32K" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="OSC">
|
|
|
|
|
<interrupt index="0" name="OSCF" caption="Oscillator Failure Interrupt (NMI)"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="DFLL" id="I6055" version="XMEGAAU" caption="DFLL">
|
|
|
|
|
<register-group caption="DFLL" name="DFLL" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="DFLL Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Register A" name="CALA" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="DFLL Calibration Value A" mask="0x7F" name="CALL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Register B" name="CALB" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="DFLL Calibration Value B" mask="0x3F" name="CALH"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Oscillator Compare Register 0" name="COMP0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Oscillator Compare Register 1" name="COMP1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Oscillator Compare Register 2" name="COMP2" offset="0x06" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="RST" id="I6083" version="XMEGAAU" caption="Reset">
|
|
|
|
|
<register-group caption="Reset" name="RST" size="2">
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Spike Detection Reset Flag" mask="0x40" name="SDRF"/>
|
|
|
|
|
<bitfield caption="Software Reset Flag" mask="0x20" name="SRF"/>
|
|
|
|
|
<bitfield caption="Programming and Debug Interface Interface Reset Flag" mask="0x10" name="PDIRF"/>
|
|
|
|
|
<bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
|
|
|
|
|
<bitfield caption="Brown-out Reset Flag" mask="0x04" name="BORF"/>
|
|
|
|
|
<bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
|
|
|
|
|
<bitfield caption="Power-on Reset Flag" mask="0x01" name="PORF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Software Reset" mask="0x01" name="SWRST"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="WDT" id="I6078" caption="Watch-Dog Timer">
|
|
|
|
|
<register-group caption="Watch-Dog Timer" name="WDT" size="3">
|
|
|
|
|
<register caption="Control" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Period" mask="0x3C" name="PER" values="WDT_PER"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x02" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Change Enable" mask="0x01" name="CEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Windowed Mode Control" name="WINCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Windowed Mode Period" mask="0x3C" name="WPER" values="WDT_WPER"/>
|
|
|
|
|
<bitfield caption="Windowed Mode Enable" mask="0x02" name="WEN"/>
|
|
|
|
|
<bitfield caption="Windowed Mode Change Enable" mask="0x01" name="WCEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Syncronization busy" mask="0x01" name="SYNCBUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Period setting" name="WDT_PER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.128s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.256s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.512s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Closed window period" name="WDT_WPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.128s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.256s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.512s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="MCU" id="I6091" version="XMEGAE" caption="MCU Control">
|
|
|
|
|
<register-group caption="MCU Control" name="MCU" size="12">
|
|
|
|
|
<register caption="Device ID byte 0" name="DEVID0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Device ID byte 1" name="DEVID1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="Device ID byte 2" name="DEVID2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Revision ID" name="REVID" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Analog Startup Delay" name="ANAINIT" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Analog startup delay Port A" mask="0x03" name="STARTUPDLYA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event System Lock" name="EVSYSLOCK" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 4-7 Lock" mask="0x10" name="EVSYS1LOCK"/>
|
|
|
|
|
<bitfield caption="Event Channel 0-3 Lock" mask="0x01" name="EVSYS0LOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="WEX Lock" name="WEXLOCK" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="WeX on T/C C4 Lock" mask="0x01" name="WEXCLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="FAULT Lock" name="FAULTLOCK" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Fault on T/C C5 Lock" mask="0x02" name="FAULTC5LOCK"/>
|
|
|
|
|
<bitfield caption="Fault on T/C C4 Lock" mask="0x01" name="FAULTC4LOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PMIC" caption="Programmable Multi-level Interrupt Controller" id="I6057">
|
|
|
|
|
<register-group name="PMIC" caption="Programmable Multi-level Interrupt Controller" size="16">
|
|
|
|
|
<register name="STATUS" caption="Status Register" size="1" offset="0x00">
|
|
|
|
|
<bitfield name="NMIEX" caption="Non-maskable Interrupt Executing" mask="0x80"/>
|
|
|
|
|
<bitfield name="HILVLEX" caption="High Level Interrupt Executing" mask="0x04"/>
|
|
|
|
|
<bitfield name="MEDLVLEX" caption="Medium Level Interrupt Executing" mask="0x02"/>
|
|
|
|
|
<bitfield name="LOLVLEX" caption="Low Level Interrupt Executing" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="INTPRI" caption="Interrupt Priority" size="1" offset="0x01">
|
|
|
|
|
<bitfield name="INTPRI" caption="Interrupt Priority" mask="0xFF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register name="CTRL" caption="Control Register" size="1" offset="0x02">
|
|
|
|
|
<bitfield name="RREN" caption="Round-Robin Priority Enable" mask="0x80"/>
|
|
|
|
|
<bitfield name="IVSEL" caption="Interrupt Vector Select" mask="0x40"/>
|
|
|
|
|
<bitfield name="HILVLEN" caption="High Level Enable" mask="0x04"/>
|
|
|
|
|
<bitfield name="MEDLVLEN" caption="Medium Level Enable" mask="0x02"/>
|
|
|
|
|
<bitfield name="LOLVLEN" caption="Low Level Enable" mask="0x01"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PORTCFG" id="I6075" version="XMEGAE" caption="Port Configuration">
|
|
|
|
|
<register-group caption="I/O port Configuration" name="PORTCFG" size="8">
|
|
|
|
|
<register caption="Multi-pin Configuration Mask" name="MPCMASK" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Clock Out Register" name="CLKOUT" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Clock and Event Output Pin Select" mask="0x80" name="CLKEVPIN"
|
|
|
|
|
values="PORTCFG_CLKEVPIN"/>
|
|
|
|
|
<bitfield caption="RTC Clock Output Enable" mask="0x60" name="RTCOUT" values="PORTCFG_RTCCLKOUT"/>
|
|
|
|
|
<bitfield caption="Clock Output Select" mask="0x0C" name="CLKOUTSEL" values="PORTCFG_CLKOUTSEL"/>
|
|
|
|
|
<bitfield caption="Clock Output Port" mask="0x03" name="CLKOUT" values="PORTCFG_CLKOUT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator and Event Out Register" name="ACEVOUT" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator Output Port" mask="0xC0" name="ACOUT" values="PORTCFG_ACOUT"/>
|
|
|
|
|
<bitfield caption="Event Channel Output Port" mask="0x30" name="EVOUT" values="PORTCFG_EVOUT"/>
|
|
|
|
|
<bitfield caption="Asynchronous Event Enabled" mask="0x08" name="EVASYEN"/>
|
|
|
|
|
<bitfield caption="Event Channel Output Selection" mask="0x07" name="EVOUTSEL"
|
|
|
|
|
values="PORTCFG_EVOUTSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Slew Rate Limit Control Register" name="SRLCTRL" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Slew Rate Limit Enable on PORTA" mask="0x01" name="SRLENRA"/>
|
|
|
|
|
<bitfield caption="Slew Rate Limit Enable on PORTC" mask="0x04" name="SRLENRC"/>
|
|
|
|
|
<bitfield caption="Slew Rate Limit Enable on PORTD" mask="0x08" name="SRLENRD"/>
|
|
|
|
|
<bitfield caption="Slew Rate Limit Enable on PORTR" mask="0x80" name="SRLENRR"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Clock and Event Output Port" name="PORTCFG_CLKEVPIN">
|
|
|
|
|
<value caption="Clock and Event Output on PIN 7" name="PIN7" value="0x00"/>
|
|
|
|
|
<value caption="Clock and Event Output on PIN 4" name="PIN4" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="RTC Clock Output Port" name="PORTCFG_RTCCLKOUT">
|
|
|
|
|
<value caption="System Clock Output Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock Output on Port C pin 6" name="PC6" value="0x01"/>
|
|
|
|
|
<value caption="System Clock Output on Port D pin 6" name="PD6" value="0x02"/>
|
|
|
|
|
<value caption="System Clock Output on Port R pin 0" name="PR0" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Peripheral Clock Output Select" name="PORTCFG_CLKOUTSEL">
|
|
|
|
|
<value caption="1x Peripheral Clock Output to pin" name="CLK1X" value="0x00"/>
|
|
|
|
|
<value caption="2x Peripheral Clock Output to pin" name="CLK2X" value="0x01"/>
|
|
|
|
|
<value caption="4x Peripheral Clock Output to pin" name="CLK4X" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="System Clock Output Port" name="PORTCFG_CLKOUT">
|
|
|
|
|
<value caption="System Clock Output Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock Output on Port C pin 7" name="PC7" value="0x01"/>
|
|
|
|
|
<value caption="System Clock Output on Port D pin 7" name="PD7" value="0x02"/>
|
|
|
|
|
<value caption="System Clock Output on Port R pin 0" name="PR0" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Analog Comparator Output Port" name="PORTCFG_ACOUT">
|
|
|
|
|
<value caption="Analog Comparator Outputs on Port A, Pin 6-7" name="PA" value="0x00"/>
|
|
|
|
|
<value caption="Analog Comparator Outputs on Port C, Pin 6-7" name="PC" value="0x01"/>
|
|
|
|
|
<value caption="Analog Comparator Outputs on Port D, Pin 6-7" name="PD" value="0x02"/>
|
|
|
|
|
<value caption="Analog Comparator Outputs on Port R, Pin 0-1" name="PR" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Output Port" name="PORTCFG_EVOUT">
|
|
|
|
|
<value caption="Event Output Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel n Output on Port C pin 7" name="PC7" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel n Output on Port D pin 7" name="PD7" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel n Output on Port R pin 0" name="PR0" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Output Select" name="PORTCFG_EVOUTSEL">
|
|
|
|
|
<value caption="Event Channel 0 output to pin" name="0" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 1 output to pin" name="1" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 2 output to pin" name="2" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 3 output to pin" name="3" value="0x03"/>
|
|
|
|
|
<value caption="Event Channel 4 output to pin" name="4" value="0x04"/>
|
|
|
|
|
<value caption="Event Channel 5 output to pin" name="5" value="0x05"/>
|
|
|
|
|
<value caption="Event Channel 6 output to pin" name="6" value="0x06"/>
|
|
|
|
|
<value caption="Event Channel 7 output to pin" name="7" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="CRC" id="I6111" version="XMEGAAU" caption="Cyclic Redundancy Checker">
|
|
|
|
|
<register-group caption="Cyclic Redundancy Checker" name="CRC" size="8">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Reset" mask="0xC0" name="RESET" values="CRC_RESET"/>
|
|
|
|
|
<bitfield caption="CRC Mode" mask="0x20" name="CRC32"/>
|
|
|
|
|
<bitfield caption="Input Source" mask="0x0F" name="SOURCE" values="CRC_SOURCE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Zero detection" mask="0x02" name="ZERO"/>
|
|
|
|
|
<bitfield caption="Busy" mask="0x01" name="BUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Data Input" name="DATAIN" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 0" name="CHECKSUM0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 1" name="CHECKSUM1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 2" name="CHECKSUM2" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="Checksum byte 3" name="CHECKSUM3" offset="0x07" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Reset" name="CRC_RESET">
|
|
|
|
|
<value caption="No Reset" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Reset CRC with CHECKSUM to all zeros" name="RESET0" value="0x02"/>
|
|
|
|
|
<value caption="Reset CRC with CHECKSUM to all ones" name="RESET1" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input Source" name="CRC_SOURCE">
|
|
|
|
|
<value caption="Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="I/O Interface" name="IO" value="0x01"/>
|
|
|
|
|
<value caption="Flash" name="FLASH" value="0x02"/>
|
|
|
|
|
<value caption="DMAC Channel 0" name="DMAC0" value="0x04"/>
|
|
|
|
|
<value caption="DMAC Channel 1" name="DMAC1" value="0x05"/>
|
|
|
|
|
<value caption="DMAC Channel 2" name="DMAC2" value="0x06"/>
|
|
|
|
|
<value caption="DMAC Channel 3" name="DMAC3" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="EDMA" id="I3002" version="XMEGAE" caption="Enhanced DMA Controller">
|
|
|
|
|
<register-group caption="Enhanced DMA Controller" name="EDMA" size="80">
|
|
|
|
|
<register caption="Control" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Enable" mask="0x80" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Software Reset" mask="0x40" name="RESET"/>
|
|
|
|
|
<bitfield caption="Channel Mode" mask="0x30" name="CHMODE" values="EDMA_CHMODE"/>
|
|
|
|
|
<bitfield caption="Double Buffer Mode" mask="0x0C" name="DBUFMODE" values="EDMA_DBUFMODE"/>
|
|
|
|
|
<bitfield caption="Priority Mode" mask="0x03" name="PRIMODE" values="EDMA_PRIMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Transfer Interrupt Status" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Channel 3 Transaction Error Interrupt Flag" mask="0x80" name="CH3ERRIF"/>
|
|
|
|
|
<bitfield caption="Channel 2 Transaction Error Interrupt Flag" mask="0x40" name="CH2ERRIF"/>
|
|
|
|
|
<bitfield caption="Channel 1 Transaction Error Interrupt Flag" mask="0x20" name="CH1ERRIF"/>
|
|
|
|
|
<bitfield caption="Channel 0 Transaction Error Interrupt Flag" mask="0x10" name="CH0ERRIF"/>
|
|
|
|
|
<bitfield caption="Channel 3 Transaction Complete Interrupt Flag" mask="0x08" name="CH3TRNFIF"/>
|
|
|
|
|
<bitfield caption="Channel 2 Transaction Complete Interrupt Flag" mask="0x04" name="CH2TRNFIF"/>
|
|
|
|
|
<bitfield caption="Channel 1 Transaction Complete Interrupt Flag" mask="0x02" name="CH1TRNFIF"/>
|
|
|
|
|
<bitfield caption="Channel 0 Transaction Complete Interrupt Flag" mask="0x01" name="CH0TRNFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Channel 3 Busy Flag" mask="0x80" name="CH3BUSY"/>
|
|
|
|
|
<bitfield caption="Channel 2 Busy Flag" mask="0x40" name="CH2BUSY"/>
|
|
|
|
|
<bitfield caption="Channel 1 Busy Flag" mask="0x20" name="CH1BUSY"/>
|
|
|
|
|
<bitfield caption="Channel 0 Busy Flag" mask="0x10" name="CH0BUSY"/>
|
|
|
|
|
<bitfield caption="Channel 3 Pending Flag" mask="0x08" name="CH3PEND"/>
|
|
|
|
|
<bitfield caption="Channel 2 Pending Flag" mask="0x04" name="CH2PEND"/>
|
|
|
|
|
<bitfield caption="Channel 1 Pending Flag" mask="0x02" name="CH1PEND"/>
|
|
|
|
|
<bitfield caption="Channel 0 Pending Flag" mask="0x01" name="CH0PEND"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register For 16-bit Access" name="TEMP" offset="0x06" size="1"/>
|
|
|
|
|
<register-group caption="EDMA Channel 0" name="CH0" offset="0x10" name-in-module="EDMA_CH"/>
|
|
|
|
|
<register-group caption="EDMA Channel 1" name="CH1" offset="0x20" name-in-module="EDMA_CH"/>
|
|
|
|
|
<register-group caption="EDMA Channel 2" name="CH2" offset="0x30" name-in-module="EDMA_CH"/>
|
|
|
|
|
<register-group caption="EDMA Channel 3" name="CH3" offset="0x40" name-in-module="EDMA_CH"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="EDMA Channel" name="EDMA_CH" size="16">
|
|
|
|
|
<register caption="Channel Control A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Channel Enable" mask="0x80" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Channel Software Reset" mask="0x40" name="RESET"/>
|
|
|
|
|
<bitfield caption="Channel Repeat Mode" mask="0x20" name="REPEAT"/>
|
|
|
|
|
<bitfield caption="Channel Transfer Request" mask="0x10" name="TRFREQ"/>
|
|
|
|
|
<bitfield caption="Channel Single Shot Data Transfer" mask="0x04" name="SINGLE"/>
|
|
|
|
|
<bitfield caption="Channel 2-bytes Burst Length" mask="0x01" name="BURSTLEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Control" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Channel Block Transfer Busy" mask="0x80" name="CHBUSY"/>
|
|
|
|
|
<bitfield caption="Channel Block Transfer Pending" mask="0x40" name="CHPEND"/>
|
|
|
|
|
<bitfield caption="Channel Transaction Error Interrupt Flag" mask="0x20" name="ERRIF"/>
|
|
|
|
|
<bitfield caption="Channel Transaction Complete Interrupt Flag" mask="0x10" name="TRNIF"/>
|
|
|
|
|
<bitfield caption="Channel Transaction Error Interrupt Level" mask="0x0C" name="ERRINTLVL"
|
|
|
|
|
values="EDMA_CH_INTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Transaction Complete Interrupt Level" mask="0x03" name="TRNINTLVL"
|
|
|
|
|
values="EDMA_CH_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register
|
|
|
|
|
caption="Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch."
|
|
|
|
|
name="ADDRCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield
|
|
|
|
|
caption="Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch."
|
|
|
|
|
mask="0x30" name="RELOAD" values="EDMA_CH_RELOAD"/>
|
|
|
|
|
<bitfield caption="Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch."
|
|
|
|
|
mask="0x07" name="DIR" values="EDMA_CH_DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Destination Address Control for Standard Channels Only." name="DESTADDRCTRL"
|
|
|
|
|
offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Destination Address Reload for Standard Channels Only." mask="0x30"
|
|
|
|
|
name="DESTRELOAD" values="EDMA_CH_RELOAD"/>
|
|
|
|
|
<bitfield caption="Destination Address Mode for Standard Channels Only." mask="0x07" name="DESTDIR"
|
|
|
|
|
values="EDMA_CH_DESTDIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Trigger Source" name="TRIGSRC" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Channel Trigger Source" mask="0xFF" name="TRIGSRC" values="EDMA_CH_TRIGSRC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register
|
|
|
|
|
caption="Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch."
|
|
|
|
|
name="TRFCNT" offset="0x06" size="2"/>
|
|
|
|
|
<register
|
|
|
|
|
caption="Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch."
|
|
|
|
|
name="ADDR" offset="0x08" size="2"/>
|
|
|
|
|
<register caption="Channel Destination Address for Standard Channels Only." name="DESTADDR"
|
|
|
|
|
offset="0x0C" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Channel mode" name="EDMA_CHMODE">
|
|
|
|
|
<value caption="Channels 0, 1, 2 and 3 in peripheal conf." name="PER0123" value="0x00"/>
|
|
|
|
|
<value caption="Channel 0 in standard conf.; channels 2 and 3 in peripheral conf." name="STD0"
|
|
|
|
|
value="0x01"/>
|
|
|
|
|
<value caption="Channel 2 in standard conf.; channels 0 and 1 in peripheral conf." name="STD2"
|
|
|
|
|
value="0x02"/>
|
|
|
|
|
<value caption="Channels 0 and 2 in standard conf." name="STD02" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Double buffer mode" name="EDMA_DBUFMODE">
|
|
|
|
|
<value caption="No double buffer enabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Double buffer enabled on peripheral channels 0/1 (if exist) " name="BUF01"
|
|
|
|
|
value="0x01"/>
|
|
|
|
|
<value caption="Double buffer enabled on peripheral channels 2/3 (if exist)" name="BUF23" value="0x02"/>
|
|
|
|
|
<value caption="Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2"
|
|
|
|
|
name="BUF0123" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Priority mode" name="EDMA_PRIMODE">
|
|
|
|
|
<value caption="Round robin on all channels" name="RR0123" value="0x00"/>
|
|
|
|
|
<value caption="Ch0 > round robin (Ch 1 ch2 Ch3)" name="RR123" value="0x01"/>
|
|
|
|
|
<value caption="Ch0 > Ch 1 > round robin (Ch2 Ch3)" name="RR23" value="0x02"/>
|
|
|
|
|
<value caption="Ch0 > Ch1 > Ch2 > Ch3 " name="CH0123" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch."
|
|
|
|
|
name="EDMA_CH_RELOAD">
|
|
|
|
|
<value caption="No reload" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Reload at end of each block transfer" name="BLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Reload at end of each burst transfer" name="BURST" value="0x02"/>
|
|
|
|
|
<value caption="Reload at end of each transaction" name="TRANSACTION" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch."
|
|
|
|
|
name="EDMA_CH_DIR">
|
|
|
|
|
<value caption="Fixed" name="FIXED" value="0x00"/>
|
|
|
|
|
<value caption="Increment" name="INC" value="0x01"/>
|
|
|
|
|
<value caption="If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. "
|
|
|
|
|
name="MP1" value="0x04"/>
|
|
|
|
|
<value caption="If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. "
|
|
|
|
|
name="MP2" value="0x05"/>
|
|
|
|
|
<value caption="If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. "
|
|
|
|
|
name="MP3" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Destination addressing mode" name="EDMA_CH_DESTDIR">
|
|
|
|
|
<value caption="Fixed" name="FIXED" value="0x00"/>
|
|
|
|
|
<value caption="Increment" name="INC" value="0x01"/>
|
|
|
|
|
<value caption="1-byte 'mask-match' (data: ADDRL, mask: ADDRH)" name="MP1" value="0x04"/>
|
|
|
|
|
<value caption="1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH)" name="MP2" value="0x05"/>
|
|
|
|
|
<value caption="2-byte 'match' (data1: ADDRL followed by data2: ADDRH)" name="MP3" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Transfer trigger source" name="EDMA_CH_TRIGSRC">
|
|
|
|
|
<value caption="Software triggers only" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event CH0 as trigger (Standard Channels Only)" name="EVSYS_CH0" value="0x01"/>
|
|
|
|
|
<value caption="Event CH1 as trigger (Standard Channels Only)" name="EVSYS_CH1" value="0x02"/>
|
|
|
|
|
<value caption="Event CH2 as trigger (Standard Channels Only)" name="EVSYS_CH2" value="0x03"/>
|
|
|
|
|
<value caption="ADCA CH0 as trigger" name="ADCA_CH0" value="0x10"/>
|
|
|
|
|
<value caption="DACA CH0 as trigger" name="DACA_CH0" value="0x15"/>
|
|
|
|
|
<value caption="DACA CH1 as trigger" name="DACA_CH1" value="0x16"/>
|
|
|
|
|
<value caption="TCC4 overflow/underflow as trigger (Standard Channels Only)" name="TCC4_OVF"
|
|
|
|
|
value="0x40"/>
|
|
|
|
|
<value caption="TCC4 error as trigger (Standard Channels Only)" name="TCC4_ERR" value="0x41"/>
|
|
|
|
|
<value caption="TCC4 compare or capture channel A as trigger (Standard Channels Only)" name="TCC4_CCA"
|
|
|
|
|
value="0x42"/>
|
|
|
|
|
<value caption="TCC4 compare or capture channel B as trigger (Standard Channels Only)" name="TCC4_CCB"
|
|
|
|
|
value="0x43"/>
|
|
|
|
|
<value caption="TCC4 compare or capture channel C as trigger (Standard Channels Only)" name="TCC4_CCC"
|
|
|
|
|
value="0x44"/>
|
|
|
|
|
<value caption="TCC4 compare or capture channel D as trigger (Standard Channels Only)" name="TCC4_CCD"
|
|
|
|
|
value="0x45"/>
|
|
|
|
|
<value caption="TCC5 overflow/underflow as trigger (Standard Channels Only)" name="TCC5_OVF"
|
|
|
|
|
value="0x46"/>
|
|
|
|
|
<value caption="TCC5 error as trigger (Standard Channels Only)" name="TCC5_ERR" value="0x47"/>
|
|
|
|
|
<value caption="TCC5 compare or capture channel A as trigger (Standard Channels Only)" name="TCC5_CCA"
|
|
|
|
|
value="0x48"/>
|
|
|
|
|
<value caption="TCC5 compare or capture channel B as trigger (Standard Channels Only)" name="TCC5_CCB"
|
|
|
|
|
value="0x49"/>
|
|
|
|
|
<value caption="SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes)"
|
|
|
|
|
name="SPIC_RXC" value="0x4A"/>
|
|
|
|
|
<value caption="SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes)"
|
|
|
|
|
name="SPIC_DRE" value="0x4B"/>
|
|
|
|
|
<value caption="USART C0 receive complete as trigger" name="USARTC0_RXC" value="0x4C"/>
|
|
|
|
|
<value caption="USART C0 data register empty as trigger" name="USARTC0_DRE" value="0x4D"/>
|
|
|
|
|
<value caption="TCD5 overflow/underflow as trigger (Standard Channels Only)" name="TCD5_OVF"
|
|
|
|
|
value="0x66"/>
|
|
|
|
|
<value caption="TCD5 error as trigger (Standard Channels Only)" name="TCD5_ERR" value="0x67"/>
|
|
|
|
|
<value caption="TCD5 compare or capture channel A as trigger (Standard Channels Only)" name="TCD5_CCA"
|
|
|
|
|
value="0x68"/>
|
|
|
|
|
<value caption="TCD5 compare or capture channel B as trigger (Standard Channels Only)" name="TCD5_CCB"
|
|
|
|
|
value="0x69"/>
|
|
|
|
|
<value caption="USART D0 receive complete as trigger" name="USARTD0_RXC" value="0x6C"/>
|
|
|
|
|
<value caption="USART D0 data register empty as trigger" name="USARTD0_DRE" value="0x6D"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="EDMA_CH_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="EDMA">
|
|
|
|
|
<interrupt index="0" name="CH0" caption="EDMA Channel 0 Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="CH1" caption="EDMA Channel 1 Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="CH2" caption="EDMA Channel 2 Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="CH3" caption="EDMA Channel 3 Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="EVSYS" id="I6061" version="XMEGAE" caption="Event System">
|
|
|
|
|
<register-group caption="Event System" name="EVSYS" size="19">
|
|
|
|
|
<register caption="Event Channel 0 Multiplexer" name="CH0MUX" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 0 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 1 Multiplexer" name="CH1MUX" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 1 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 2 Multiplexer" name="CH2MUX" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 2 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 3 Multiplexer" name="CH3MUX" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 3 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 4 Multiplexer" name="CH4MUX" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 4 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 5 Multiplexer" name="CH5MUX" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 5 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 6 Multiplexer" name="CH6MUX" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 6 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Channel 7 Multiplexer" name="CH7MUX" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Event Channel 7 Multiplexer" mask="0xFF" name="CHMUX" values="EVSYS_CHMUX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 0 Control Register" name="CH0CTRL" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Rotary Decoder Enable" mask="0x80" name="ROTARY"/>
|
|
|
|
|
<bitfield caption="Quadrature Decoder Index Recognition Mode" mask="0x60" name="QDIRM"
|
|
|
|
|
values="EVSYS_QDIRM"/>
|
|
|
|
|
<bitfield caption="Quadrature Decoder Index Enable" mask="0x10" name="QDIEN"/>
|
|
|
|
|
<bitfield caption="Quadrature Decoder Enable" mask="0x08" name="QDEN"/>
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 1 Control Register" name="CH1CTRL" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 2 Control Register" name="CH2CTRL" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 3 Control Register" name="CH3CTRL" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 4 Control Register" name="CH4CTRL" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 5 Control Register" name="CH5CTRL" offset="0x0D" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 6 Control Register" name="CH6CTRL" offset="0x0E" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 7 Control Register" name="CH7CTRL" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="Digital Filter" mask="0x07" name="DIGFILT" values="EVSYS_DIGFILT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Strobe" name="STROBE" offset="0x10" size="1"/>
|
|
|
|
|
<register caption="Event Data" name="DATA" offset="0x11" size="1"/>
|
|
|
|
|
<register caption="Digital Filter Control Register" name="DFCTRL" offset="0x12" size="1">
|
|
|
|
|
<bitfield caption="Prescaler Filter" mask="0xF0" name="PRESCFILT" values="EVSYS_PRESCFILT"/>
|
|
|
|
|
<bitfield caption="Prescaler Filter Select" mask="0x08" name="FILTSEL"/>
|
|
|
|
|
<bitfield caption="Prescaler" mask="0x07" name="PRESC" values="EVSYS_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Event Channel multiplexer input selection" name="EVSYS_CHMUX">
|
|
|
|
|
<value caption="Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="RTC Overflow" name="RTC_OVF" value="0x08"/>
|
|
|
|
|
<value caption="RTC Compare Match" name="RTC_CMP" value="0x09"/>
|
|
|
|
|
<value caption="Analog Comparator A Channel 0" name="ACA_CH0" value="0x10"/>
|
|
|
|
|
<value caption="Analog Comparator A Channel 1" name="ACA_CH1" value="0x11"/>
|
|
|
|
|
<value caption="Analog Comparator A Window" name="ACA_WIN" value="0x12"/>
|
|
|
|
|
<value caption="ADC A Channel 0" name="ADCA_CH0" value="0x20"/>
|
|
|
|
|
<value caption="Port A, Pin0" name="PORTA_PIN0" value="0x50"/>
|
|
|
|
|
<value caption="Port A, Pin1" name="PORTA_PIN1" value="0x51"/>
|
|
|
|
|
<value caption="Port A, Pin2" name="PORTA_PIN2" value="0x52"/>
|
|
|
|
|
<value caption="Port A, Pin3" name="PORTA_PIN3" value="0x53"/>
|
|
|
|
|
<value caption="Port A, Pin4" name="PORTA_PIN4" value="0x54"/>
|
|
|
|
|
<value caption="Port A, Pin5" name="PORTA_PIN5" value="0x55"/>
|
|
|
|
|
<value caption="Port A, Pin6" name="PORTA_PIN6" value="0x56"/>
|
|
|
|
|
<value caption="Port A, Pin7" name="PORTA_PIN7" value="0x57"/>
|
|
|
|
|
<value caption="Port C, Pin0" name="PORTC_PIN0" value="0x60"/>
|
|
|
|
|
<value caption="Port C, Pin1" name="PORTC_PIN1" value="0x61"/>
|
|
|
|
|
<value caption="Port C, Pin2" name="PORTC_PIN2" value="0x62"/>
|
|
|
|
|
<value caption="Port C, Pin3" name="PORTC_PIN3" value="0x63"/>
|
|
|
|
|
<value caption="Port C, Pin4" name="PORTC_PIN4" value="0x64"/>
|
|
|
|
|
<value caption="Port C, Pin5" name="PORTC_PIN5" value="0x65"/>
|
|
|
|
|
<value caption="Port C, Pin6" name="PORTC_PIN6" value="0x66"/>
|
|
|
|
|
<value caption="Port C, Pin7" name="PORTC_PIN7" value="0x67"/>
|
|
|
|
|
<value caption="Port D, Pin0" name="PORTD_PIN0" value="0x68"/>
|
|
|
|
|
<value caption="Port D, Pin1" name="PORTD_PIN1" value="0x69"/>
|
|
|
|
|
<value caption="Port D, Pin2" name="PORTD_PIN2" value="0x6A"/>
|
|
|
|
|
<value caption="Port D, Pin3" name="PORTD_PIN3" value="0x6B"/>
|
|
|
|
|
<value caption="Port D, Pin4" name="PORTD_PIN4" value="0x6C"/>
|
|
|
|
|
<value caption="Port D, Pin5" name="PORTD_PIN5" value="0x6D"/>
|
|
|
|
|
<value caption="Port D, Pin6" name="PORTD_PIN6" value="0x6E"/>
|
|
|
|
|
<value caption="Port D, Pin7" name="PORTD_PIN7" value="0x6F"/>
|
|
|
|
|
<value caption="Prescaler, divide by 1" name="PRESCALER_1" value="0x80"/>
|
|
|
|
|
<value caption="Prescaler, divide by 2" name="PRESCALER_2" value="0x81"/>
|
|
|
|
|
<value caption="Prescaler, divide by 4" name="PRESCALER_4" value="0x82"/>
|
|
|
|
|
<value caption="Prescaler, divide by 8" name="PRESCALER_8" value="0x83"/>
|
|
|
|
|
<value caption="Prescaler, divide by 16" name="PRESCALER_16" value="0x84"/>
|
|
|
|
|
<value caption="Prescaler, divide by 32" name="PRESCALER_32" value="0x85"/>
|
|
|
|
|
<value caption="Prescaler, divide by 64" name="PRESCALER_64" value="0x86"/>
|
|
|
|
|
<value caption="Prescaler, divide by 128" name="PRESCALER_128" value="0x87"/>
|
|
|
|
|
<value caption="Prescaler, divide by 256" name="PRESCALER_256" value="0x88"/>
|
|
|
|
|
<value caption="Prescaler, divide by 512" name="PRESCALER_512" value="0x89"/>
|
|
|
|
|
<value caption="Prescaler, divide by 1024" name="PRESCALER_1024" value="0x8A"/>
|
|
|
|
|
<value caption="Prescaler, divide by 2048" name="PRESCALER_2048" value="0x8B"/>
|
|
|
|
|
<value caption="Prescaler, divide by 4096" name="PRESCALER_4096" value="0x8C"/>
|
|
|
|
|
<value caption="Prescaler, divide by 8192" name="PRESCALER_8192" value="0x8D"/>
|
|
|
|
|
<value caption="Prescaler, divide by 16384" name="PRESCALER_16384" value="0x8E"/>
|
|
|
|
|
<value caption="Prescaler, divide by 32768" name="PRESCALER_32768" value="0x8F"/>
|
|
|
|
|
<value caption="XCL BTC0 underflow" name="XCL_UNF0" value="0xB0"/>
|
|
|
|
|
<value caption="XCL BTC1 underflow" name="XCL_UNF1" value="0xB1"/>
|
|
|
|
|
<value caption="XCL BTC0 capture or compare" name="XCL_CC0" value="0xB2"/>
|
|
|
|
|
<value caption="XCL BTC1 capture or compare" name="XCL_CC1" value="0xB3"/>
|
|
|
|
|
<value caption="XCL PEC0 restart" name="XCL_PEC0" value="0xB4"/>
|
|
|
|
|
<value caption="XCL PEC1 restart" name="XCL_PEC1" value="0xB5"/>
|
|
|
|
|
<value caption="XCL LUT0 output" name="XCL_LUT0" value="0xB6"/>
|
|
|
|
|
<value caption="XCL LUT1 output" name="XCL_LUT1" value="0xB7"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Overflow" name="TCC4_OVF" value="0xC0"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Error" name="TCC4_ERR" value="0xC1"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Compare or Capture A" name="TCC4_CCA" value="0xC4"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Compare or Capture B" name="TCC4_CCB" value="0xC5"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Compare or Capture C" name="TCC4_CCC" value="0xC6"/>
|
|
|
|
|
<value caption="Timer/Counter C4 Compare or Capture D" name="TCC4_CCD" value="0xC7"/>
|
|
|
|
|
<value caption="Timer/Counter C5 Overflow" name="TCC5_OVF" value="0xC8"/>
|
|
|
|
|
<value caption="Timer/Counter C5 Error" name="TCC5_ERR" value="0xC9"/>
|
|
|
|
|
<value caption="Timer/Counter C5 Compare or Capture A" name="TCC5_CCA" value="0xCC"/>
|
|
|
|
|
<value caption="Timer/Counter C5 Compare or Capture B" name="TCC5_CCB" value="0xCD"/>
|
|
|
|
|
<value caption="Timer/Counter D5 Overflow" name="TCD5_OVF" value="0xD8"/>
|
|
|
|
|
<value caption="Timer/Counter D5 Error" name="TCD5_ERR" value="0xD9"/>
|
|
|
|
|
<value caption="Timer/Counter D5 Compare or Capture A" name="TCD5_CCA" value="0xDC"/>
|
|
|
|
|
<value caption="Timer/Counter D5 Compare or Capture B" name="TCD5_CCB" value="0xDD"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Quadrature Decoder Index Recognition Mode" name="EVSYS_QDIRM">
|
|
|
|
|
<value caption="QDPH0 = 0, QDPH90 = 0" name="00" value="0x00"/>
|
|
|
|
|
<value caption="QDPH0 = 0, QDPH90 = 1" name="01" value="0x01"/>
|
|
|
|
|
<value caption="QDPH0 = 1, QDPH90 = 0" name="10" value="0x02"/>
|
|
|
|
|
<value caption="QDPH0 = 1, QDPH90 = 1" name="11" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Digital filter coefficient" name="EVSYS_DIGFILT">
|
|
|
|
|
<value caption="1 SAMPLE" name="1SAMPLE" value="0x00"/>
|
|
|
|
|
<value caption="2 SAMPLES" name="2SAMPLES" value="0x01"/>
|
|
|
|
|
<value caption="3 SAMPLES" name="3SAMPLES" value="0x02"/>
|
|
|
|
|
<value caption="4 SAMPLES" name="4SAMPLES" value="0x03"/>
|
|
|
|
|
<value caption="5 SAMPLES" name="5SAMPLES" value="0x04"/>
|
|
|
|
|
<value caption="6 SAMPLES" name="6SAMPLES" value="0x05"/>
|
|
|
|
|
<value caption="7 SAMPLES" name="7SAMPLES" value="0x06"/>
|
|
|
|
|
<value caption="8 SAMPLES" name="8SAMPLES" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler Filter" name="EVSYS_PRESCFILT">
|
|
|
|
|
<value caption="Enable prescaler filter for either channel 0 or 4" name="CH04" value="0x01"/>
|
|
|
|
|
<value caption="Enable prescaler filter for either channel 1 or 5" name="CH15" value="0x02"/>
|
|
|
|
|
<value caption="Enable prescaler filter for either channel 2 or 6" name="CH26" value="0x04"/>
|
|
|
|
|
<value caption="Enable prescaler filter for either channel 3 or 7" name="CH37" value="0x08"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler" name="EVSYS_PRESCALER">
|
|
|
|
|
<value caption="CLKPER, divide by 8" name="CLKPER_8" value="0x00"/>
|
|
|
|
|
<value caption="CLKPER, divide by 64" name="CLKPER_64" value="0x01"/>
|
|
|
|
|
<value caption="CLKPER, divide by 512" name="CLKPER_512" value="0x02"/>
|
|
|
|
|
<value caption="CLKPER, divide by 4096" name="CLKPER_4096" value="0x03"/>
|
|
|
|
|
<value caption="CLKPER, divide by 32768" name="CLKPER_32768" value="0x04"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="NVM" id="I3620" version="XMEGAE" caption="Non Volatile Memory Controller">
|
|
|
|
|
<register-group caption="Non-volatile Memory Controller" name="NVM" size="17">
|
|
|
|
|
<register caption="Address Register 0" name="ADDR0" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Address Register 1" name="ADDR1" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="Address Register 2" name="ADDR2" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Data Register 0" name="DATA0" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Data Register 1" name="DATA1" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Data Register 2" name="DATA2" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="Command" name="CMD" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Command" mask="0x7F" name="CMD" values="NVM_CMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Command Execute" mask="0x01" name="CMDEX"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="EEPROM Power Reduction Enable" mask="0x02" name="EPRM"/>
|
|
|
|
|
<bitfield caption="SPM Lock" mask="0x01" name="SPMLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control" name="INTCTRL" offset="0x0D" size="1">
|
|
|
|
|
<bitfield caption="SPM Interrupt Level" mask="0x0C" name="SPMLVL" values="NVM_SPMLVL"/>
|
|
|
|
|
<bitfield caption="EEPROM Interrupt Level" mask="0x03" name="EELVL" values="NVM_EELVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="Non-volatile Memory Busy" mask="0x80" name="NVMBUSY"/>
|
|
|
|
|
<bitfield caption="Flash Memory Busy" mask="0x40" name="FBUSY"/>
|
|
|
|
|
<bitfield caption="EEPROM Page Buffer Active Loading" mask="0x02" name="EELOAD"/>
|
|
|
|
|
<bitfield caption="Flash Page Buffer Active Loading" mask="0x01" name="FLOAD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Lock Bits" name="LOCKBITS" offset="0x10" size="1">
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Boot Section" mask="0xC0" name="BLBB" values="NVM_BLBB"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Section" mask="0x30" name="BLBA" values="NVM_BLBA"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Table" mask="0x0C" name="BLBAT" values="NVM_BLBAT"/>
|
|
|
|
|
<bitfield caption="Lock Bits" mask="0x03" name="LB" values="NVM_LB"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="NVM Command" name="NVM_CMD">
|
|
|
|
|
<value caption="Noop/Ordinary LPM" name="NO_OPERATION" value="0x00"/>
|
|
|
|
|
<value caption="Read user signature row" name="READ_USER_SIG_ROW" value="0x01"/>
|
|
|
|
|
<value caption="Read calibration row" name="READ_CALIB_ROW" value="0x02"/>
|
|
|
|
|
<value caption="Read fuse byte" name="READ_FUSES" value="0x07"/>
|
|
|
|
|
<value caption="Write lock bits" name="WRITE_LOCK_BITS" value="0x08"/>
|
|
|
|
|
<value caption="Erase user signature row" name="ERASE_USER_SIG_ROW" value="0x18"/>
|
|
|
|
|
<value caption="Write user signature row" name="WRITE_USER_SIG_ROW" value="0x1A"/>
|
|
|
|
|
<value caption="Erase Application Section" name="ERASE_APP" value="0x20"/>
|
|
|
|
|
<value caption="Erase Application Section page" name="ERASE_APP_PAGE" value="0x22"/>
|
|
|
|
|
<value caption="Load Flash page buffer" name="LOAD_FLASH_BUFFER" value="0x23"/>
|
|
|
|
|
<value caption="Write Application Section page" name="WRITE_APP_PAGE" value="0x24"/>
|
|
|
|
|
<value caption="Erase-and-write Application Section page" name="ERASE_WRITE_APP_PAGE" value="0x25"/>
|
|
|
|
|
<value caption="Erase/flush Flash page buffer" name="ERASE_FLASH_BUFFER" value="0x26"/>
|
|
|
|
|
<value caption="Erase Boot Section page" name="ERASE_BOOT_PAGE" value="0x2A"/>
|
|
|
|
|
<value caption="Erase Flash Page" name="ERASE_FLASH_PAGE" value="0x2B"/>
|
|
|
|
|
<value caption="Write Boot Section page" name="WRITE_BOOT_PAGE" value="0x2C"/>
|
|
|
|
|
<value caption="Erase-and-write Boot Section page" name="ERASE_WRITE_BOOT_PAGE" value="0x2D"/>
|
|
|
|
|
<value caption="Write Flash Page" name="WRITE_FLASH_PAGE" value="0x2E"/>
|
|
|
|
|
<value caption="Erase-and-write Flash Page" name="ERASE_WRITE_FLASH_PAGE" value="0x2F"/>
|
|
|
|
|
<value caption="Erase EEPROM" name="ERASE_EEPROM" value="0x30"/>
|
|
|
|
|
<value caption="Erase EEPROM page" name="ERASE_EEPROM_PAGE" value="0x32"/>
|
|
|
|
|
<value caption="Write EEPROM page" name="WRITE_EEPROM_PAGE" value="0x34"/>
|
|
|
|
|
<value caption="Erase-and-write EEPROM page" name="ERASE_WRITE_EEPROM_PAGE" value="0x35"/>
|
|
|
|
|
<value caption="Erase/flush EEPROM page buffer" name="ERASE_EEPROM_BUFFER" value="0x36"/>
|
|
|
|
|
<value caption="Application section CRC" name="APP_CRC" value="0x38"/>
|
|
|
|
|
<value caption=" Boot Section CRC" name="BOOT_CRC" value="0x39"/>
|
|
|
|
|
<value caption="Flash Range CRC" name="FLASH_RANGE_CRC" value="0x3A"/>
|
|
|
|
|
<value caption="Erase Chip" name="CHIP_ERASE" value="0x40"/>
|
|
|
|
|
<value caption="Read NVM" name="READ_NVM" value="0x43"/>
|
|
|
|
|
<value caption="Write Fuse byte" name="WRITE_FUSE" value="0x4C"/>
|
|
|
|
|
<value caption="Erase Boot Section" name="ERASE_BOOT" value="0x68"/>
|
|
|
|
|
<value caption="Flash CRC" name="FLASH_CRC" value="0x78"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="SPM ready interrupt level" name="NVM_SPMLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="EEPROM ready interrupt level" name="NVM_EELVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - boot section" name="NVM_BLBB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application section" name="NVM_BLBA">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application table section" name="NVM_BLBAT">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Lock bits" name="NVM_LB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="NVM">
|
|
|
|
|
<interrupt index="0" name="EE" caption="EE Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="SPM" caption="SPM Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="ADC" id="I6110" version="XMEGAE" caption="Analog/Digital Converter">
|
|
|
|
|
<register-group caption="ADC Channel" name="ADC_CH" size="16">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Channel Start Conversion" mask="0x80" name="START"/>
|
|
|
|
|
<bitfield caption="Gain Factor" mask="0x1C" name="GAIN" values="ADC_CH_GAIN"/>
|
|
|
|
|
<bitfield caption="Input Mode Select" mask="0x03" name="INPUTMODE" values="ADC_CH_INPUTMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="MUX Control" name="MUXCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="MUX selection on Positive ADC Input" mask="0x78" name="MUXPOS"
|
|
|
|
|
values="ADC_CH_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX selection on Internal ADC Input" mask="0x78" name="MUXINT"
|
|
|
|
|
values="ADC_CH_MUXINT"/>
|
|
|
|
|
<bitfield caption="MUX selection on Negative ADC Input" mask="0x07" name="MUXNEG"
|
|
|
|
|
values="ADC_CH_MUXNEG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Interrupt Control Register" name="INTCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0x0C" name="INTMODE" values="ADC_CH_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x03" name="INTLVL" values="ADC_CH_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Channel Interrupt Flag" mask="0x01" name="IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel Result" name="RES" offset="0x04" size="2"/>
|
|
|
|
|
<register caption="Input Channel Scan" name="SCAN" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Positive MUX Setting Offset" mask="0xF0" name="INPUTOFFSET"/>
|
|
|
|
|
<bitfield caption="Number of Channels Included in Scan" mask="0x0F" name="INPUTSCAN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Correction Control Register" name="CORRCTRL" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Correction Enable" mask="0x01" name="CORREN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Offset Correction Register 0" name="OFFSETCORR0" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Offset Correction Register 1" name="OFFSETCORR1" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Offset Correction Byte 1" mask="0x0F" name="OFFSETCORR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Gain Correction Register 0" name="GAINCORR0" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Gain Correction Register 1" name="GAINCORR1" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Gain Correction Byte 1" mask="0x0F" name="GAINCORR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Average Control Register" name="AVGCTRL" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Right Shift" mask="0x70" name="RIGHTSHIFT"/>
|
|
|
|
|
<bitfield caption="Averaged Number of Samples" mask="0x0F" name="SAMPNUM" values="ADC_SAMPNUM"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="Analog-to-Digital Converter" name="ADC" size="48">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Start Conversion" mask="0x04" name="START"/>
|
|
|
|
|
<bitfield caption="ADC Flush" mask="0x02" name="FLUSH"/>
|
|
|
|
|
<bitfield caption="Enable ADC" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Current Limitation" mask="0x60" name="CURRLIMIT" values="ADC_CURRLIMIT"/>
|
|
|
|
|
<bitfield caption="Conversion Mode" mask="0x10" name="CONMODE"/>
|
|
|
|
|
<bitfield caption="Free Running Mode Enable" mask="0x08" name="FREERUN"/>
|
|
|
|
|
<bitfield caption="Result Resolution" mask="0x06" name="RESOLUTION" values="ADC_RESOLUTION"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Reference Control" name="REFCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Reference Selection" mask="0x70" name="REFSEL" values="ADC_REFSEL"/>
|
|
|
|
|
<bitfield caption="Bandgap enable" mask="0x02" name="BANDGAP"/>
|
|
|
|
|
<bitfield caption="Temperature Reference Enable" mask="0x01" name="TEMPREF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Control" name="EVCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Input Select" mask="0x38" name="EVSEL" values="ADC_EVSEL"/>
|
|
|
|
|
<bitfield caption="Event Action Select" mask="0x07" name="EVACT" values="ADC_EVACT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Clock Prescaler" name="PRESCALER" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Clock Prescaler Selection" mask="0x07" name="PRESCALER" values="ADC_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Channel 0 Interrupt Flag" mask="0x01" name="CH0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register" name="TEMP" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="ADC Sampling Time Control Register" name="SAMPCTRL" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Sampling time control register" mask="0x03F" name="SAMPVAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Calibration Value" name="CAL" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Channel 0 Result" name="CH0RES" offset="0x10" size="2"/>
|
|
|
|
|
<register caption="Compare Value" name="CMP" offset="0x18" size="2"/>
|
|
|
|
|
<register-group caption="ADC Channel 0" name="CH0" offset="0x20" name-in-module="ADC_CH"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Current Limitation" name="ADC_CURRLIMIT">
|
|
|
|
|
<value caption="No current limit, 300ksps max sampling rate" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Low current limit, 250ksps max sampling rate" name="LOW" value="0x01"/>
|
|
|
|
|
<value caption="Medium current limit, 150ksps max sampling rate" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High current limit, 50ksps max sampling rate" name="HIGH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Conversion result resolution" name="ADC_RESOLUTION">
|
|
|
|
|
<value caption="12-bit right-adjusted result" name="12BIT" value="0x00"/>
|
|
|
|
|
<value caption="More than 12-bit (oversapling) right-adjusted result" name="MT12BIT" value="0x01"/>
|
|
|
|
|
<value caption="8-bit right-adjusted result" name="8BIT" value="0x02"/>
|
|
|
|
|
<value caption="12-bit left-adjusted result" name="LEFT12BIT" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Voltage reference selection" name="ADC_REFSEL">
|
|
|
|
|
<value caption="Internal 1V" name="INT1V" value="0x00"/>
|
|
|
|
|
<value caption="Internal VCC / 1.6" name="INTVCC" value="0x01"/>
|
|
|
|
|
<value caption="External reference on PORT A" name="AREFA" value="0x02"/>
|
|
|
|
|
<value caption="External reference on PORT D" name="AREFD" value="0x03"/>
|
|
|
|
|
<value caption="Internal VCC / 2" name="INTVCC2" value="0x04"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event channel input selection" name="ADC_EVSEL">
|
|
|
|
|
<value caption="Event Channel 0" name="0" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 1" name="1" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 2" name="2" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 3" name="3" value="0x03"/>
|
|
|
|
|
<value caption="Event Channel 4" name="4" value="0x04"/>
|
|
|
|
|
<value caption="Event Channel 5" name="5" value="0x05"/>
|
|
|
|
|
<value caption="Event Channel 6" name="6" value="0x06"/>
|
|
|
|
|
<value caption="Event Channel 7" name="7" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event action selection" name="ADC_EVACT">
|
|
|
|
|
<value caption="No event action" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="First event triggers channel conversion" name="CH0" value="0x01"/>
|
|
|
|
|
<value caption="The ADC is flushed and restarted for accurate timing" name="SYNCSWEEP" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Clock prescaler" name="ADC_PRESCALER">
|
|
|
|
|
<value caption="Divide clock by 4" name="DIV4" value="0x00"/>
|
|
|
|
|
<value caption="Divide clock by 8" name="DIV8" value="0x01"/>
|
|
|
|
|
<value caption="Divide clock by 16" name="DIV16" value="0x02"/>
|
|
|
|
|
<value caption="Divide clock by 32" name="DIV32" value="0x03"/>
|
|
|
|
|
<value caption="Divide clock by 64" name="DIV64" value="0x04"/>
|
|
|
|
|
<value caption="Divide clock by 128" name="DIV128" value="0x05"/>
|
|
|
|
|
<value caption="Divide clock by 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="Divide clock by 512" name="DIV512" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Gain factor" name="ADC_CH_GAIN">
|
|
|
|
|
<value caption="1x gain" name="1X" value="0x00"/>
|
|
|
|
|
<value caption="2x gain" name="2X" value="0x01"/>
|
|
|
|
|
<value caption="4x gain" name="4X" value="0x02"/>
|
|
|
|
|
<value caption="8x gain" name="8X" value="0x03"/>
|
|
|
|
|
<value caption="16x gain" name="16X" value="0x04"/>
|
|
|
|
|
<value caption="32x gain" name="32X" value="0x05"/>
|
|
|
|
|
<value caption="64x gain" name="64X" value="0x06"/>
|
|
|
|
|
<value caption="x/2 gain" name="DIV2" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input mode" name="ADC_CH_INPUTMODE">
|
|
|
|
|
<value caption="Internal inputs, no gain" name="INTERNAL" value="0x00"/>
|
|
|
|
|
<value caption="Single-ended input, no gain" name="SINGLEENDED" value="0x01"/>
|
|
|
|
|
<value caption="Differential input, gain with 4 LSB pins selection" name="DIFFWGAINL" value="0x02"/>
|
|
|
|
|
<value caption="Differential input, gain with 4 MSB pins selection" name="DIFFWGAINH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Positive input multiplexer selection" name="ADC_CH_MUXPOS">
|
|
|
|
|
<value caption="Input pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 2" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 3" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Input pin 4" name="PIN4" value="0x04"/>
|
|
|
|
|
<value caption="Input pin 5" name="PIN5" value="0x05"/>
|
|
|
|
|
<value caption="Input pin 6" name="PIN6" value="0x06"/>
|
|
|
|
|
<value caption="Input pin 7" name="PIN7" value="0x07"/>
|
|
|
|
|
<value caption="Input pin 8" name="PIN8" value="0x08"/>
|
|
|
|
|
<value caption="Input pin 9" name="PIN9" value="0x09"/>
|
|
|
|
|
<value caption="Input pin 10" name="PIN10" value="0x0A"/>
|
|
|
|
|
<value caption="Input pin 11" name="PIN11" value="0x0B"/>
|
|
|
|
|
<value caption="Input pin 12" name="PIN12" value="0x0C"/>
|
|
|
|
|
<value caption="Input pin 13" name="PIN13" value="0x0D"/>
|
|
|
|
|
<value caption="Input pin 14" name="PIN14" value="0x0E"/>
|
|
|
|
|
<value caption="Input pin 15" name="PIN15" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Internal input multiplexer selections" name="ADC_CH_MUXINT">
|
|
|
|
|
<value caption="Temperature Reference" name="TEMP" value="0x00"/>
|
|
|
|
|
<value caption="Bandgap Reference" name="BANDGAP" value="0x01"/>
|
|
|
|
|
<value caption="1/10 Scaled VCC" name="SCALEDVCC" value="0x02"/>
|
|
|
|
|
<value caption="DAC Output" name="DAC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Negative input multiplexer selection" name="ADC_CH_MUXNEG">
|
|
|
|
|
<value caption="Input pin 0 (Input Mode = 2)" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 1 (Input Mode = 2)" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 2 (Input Mode = 2)" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 3 (Input Mode = 2)" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Input pin 4 (Input Mode = 3)" name="PIN4" value="0x00"/>
|
|
|
|
|
<value caption="Input pin 5 (Input Mode = 3)" name="PIN5" value="0x01"/>
|
|
|
|
|
<value caption="Input pin 6 (Input Mode = 3)" name="PIN6" value="0x02"/>
|
|
|
|
|
<value caption="Input pin 7 (Input Mode = 3)" name="PIN7" value="0x03"/>
|
|
|
|
|
<value caption="PAD Ground (Input Mode = 2)" name="GND_MODE3" value="0x05"/>
|
|
|
|
|
<value caption="Internal Ground (Input Mode = 2)" name="INTGND_MODE3" value="0x07"/>
|
|
|
|
|
<value caption="Internal Ground (Input Mode = 3)" name="INTGND_MODE4" value="0x04"/>
|
|
|
|
|
<value caption="PAD Ground (Input Mode = 3)" name="GND_MODE4" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt mode" name="ADC_CH_INTMODE">
|
|
|
|
|
<value caption="Interrupt on conversion complete" name="COMPLETE" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on result below compare value" name="BELOW" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on result above compare value" name="ABOVE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="ADC_CH_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Averaged Number of Samples" name="ADC_SAMPNUM">
|
|
|
|
|
<value caption="1 Sample" name="1X" value="0x00"/>
|
|
|
|
|
<value caption="2 Samples" name="2X" value="0x01"/>
|
|
|
|
|
<value caption="4 Samples" name="4X" value="0x02"/>
|
|
|
|
|
<value caption="8 Samples" name="8X" value="0x03"/>
|
|
|
|
|
<value caption="16 Samples" name="16X" value="0x04"/>
|
|
|
|
|
<value caption="32 Samples" name="32X" value="0x05"/>
|
|
|
|
|
<value caption="64 Samples" name="64X" value="0x06"/>
|
|
|
|
|
<value caption="128 Samples" name="128X" value="0x07"/>
|
|
|
|
|
<value caption="256 Samples" name="256X" value="0x08"/>
|
|
|
|
|
<value caption="512 Samples" name="512X" value="0x09"/>
|
|
|
|
|
<value caption="1024 Samples" name="1024X" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="ADC">
|
|
|
|
|
<interrupt index="0" name="CH0" caption="ADC Channel Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="DAC" id="I6059" version="XMEGAAU" caption="Digital/Analog Converter">
|
|
|
|
|
<register-group caption="Digital-to-Analog Converter" name="DAC" size="28">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Internal Output Enable" mask="0x10" name="IDOEN"/>
|
|
|
|
|
<bitfield caption="Channel 1 Output Enable" mask="0x08" name="CH1EN"/>
|
|
|
|
|
<bitfield caption="Channel 0 Output Enable" mask="0x04" name="CH0EN"/>
|
|
|
|
|
<bitfield caption="Low Power Mode" mask="0x02" name="LPMODE"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Channel Select" mask="0x60" name="CHSEL" values="DAC_CHSEL"/>
|
|
|
|
|
<bitfield caption="Channel 1 Event Trig Enable" mask="0x02" name="CH1TRIG"/>
|
|
|
|
|
<bitfield caption="Channel 0 Event Trig Enable" mask="0x01" name="CH0TRIG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Reference Select" mask="0x18" name="REFSEL" values="DAC_REFSEL"/>
|
|
|
|
|
<bitfield caption="Left-adjust Result" mask="0x01" name="LEFTADJ"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Event Input Control" name="EVCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Separate Event Channel Input for Channel 1" mask="0x08" name="EVSPLIT"/>
|
|
|
|
|
<bitfield caption="Event Input Selection" mask="0x07" name="EVSEL" values="DAC_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Channel 1 Data Register Empty" mask="0x02" name="CH1DRE"/>
|
|
|
|
|
<bitfield caption="Channel 0 Data Register Empty" mask="0x01" name="CH0DRE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Gain Calibration" name="CH0GAINCAL" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Gain Calibration" mask="0x7F" name="CH0GAINCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Offset Calibration" name="CH0OFFSETCAL" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Offset Calibration" mask="0x7F" name="CH0OFFSETCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Gain Calibration" name="CH1GAINCAL" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Gain Calibration" mask="0x7F" name="CH1GAINCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Offset Calibration" name="CH1OFFSETCAL" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Offset Calibration" mask="0x7F" name="CH1OFFSETCAL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Channel 0 Data" name="CH0DATA" offset="0x18" size="2"/>
|
|
|
|
|
<register caption="Channel 1 Data" name="CH1DATA" offset="0x1A" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Output channel selection" name="DAC_CHSEL">
|
|
|
|
|
<value caption="Single channel operation (Channel 0 only)" name="SINGLE" value="0x00"/>
|
|
|
|
|
<value caption="Single channel operation (Channel 1 only)" name="SINGLE1" value="0x01"/>
|
|
|
|
|
<value caption="Dual channel operation (Channel 0 and channel 1)" name="DUAL" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Reference voltage selection" name="DAC_REFSEL">
|
|
|
|
|
<value caption="Internal 1V " name="INT1V" value="0x00"/>
|
|
|
|
|
<value caption="Analog supply voltage" name="AVCC" value="0x01"/>
|
|
|
|
|
<value caption="External reference on AREF on PORTA" name="AREFA" value="0x02"/>
|
|
|
|
|
<value caption="External reference on AREF on PORTD" name="AREFD" value="0x03"/>
|
|
|
|
|
<value caption="Define for PortB kept for legacy reasons" name="AREFB" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event channel selection" name="DAC_EVSEL">
|
|
|
|
|
<value caption="Event Channel 0" name="0" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 1" name="1" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel 2" name="2" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel 3" name="3" value="0x03"/>
|
|
|
|
|
<value caption="Event Channel 4" name="4" value="0x04"/>
|
|
|
|
|
<value caption="Event Channel 5" name="5" value="0x05"/>
|
|
|
|
|
<value caption="Event Channel 6" name="6" value="0x06"/>
|
|
|
|
|
<value caption="Event Channel 7" name="7" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="AC" id="I6077" version="XMEGAE" caption="Analog Comparator">
|
|
|
|
|
<register-group caption="Analog Comparator" name="AC" size="10">
|
|
|
|
|
<register caption="Analog Comparator 0 Control" name="AC0CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0xC0" name="INTMODE" values="AC_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x30" name="INTLVL" values="AC_INTLVL"/>
|
|
|
|
|
<bitfield caption="Hysteresis Mode" mask="0x06" name="HYSMODE" values="AC_HYSMODE"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 1 Control" name="AC1CTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Mode" mask="0xC0" name="INTMODE" values="AC_INTMODE"/>
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0x30" name="INTLVL" values="AC_INTLVL"/>
|
|
|
|
|
<bitfield caption="Hysteresis Mode" mask="0x06" name="HYSMODE" values="AC_HYSMODE"/>
|
|
|
|
|
<bitfield caption="Enable" mask="0x01" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 0 MUX Control" name="AC0MUXCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="MUX Positive Input" mask="0x38" name="MUXPOS" values="AC_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX Negative Input" mask="0x07" name="MUXNEG" values="AC_MUXNEG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Analog Comparator 1 MUX Control" name="AC1MUXCTRL" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="MUX Positive Input" mask="0x38" name="MUXPOS" values="AC_MUXPOS"/>
|
|
|
|
|
<bitfield caption="MUX Negative Input" mask="0x07" name="MUXNEG" values="AC_MUXNEG"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Output Invert Enable" mask="0x08" name="AC1INVEN"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Output Invert Enable" mask="0x04" name="AC0INVEN"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Output Enable" mask="0x02" name="AC1OUT"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Output Enable" mask="0x01" name="AC0OUT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="VCC Voltage Scaler Factor" mask="0x3F" name="SCALEFAC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Window Mode Control" name="WINCTRL" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Window Mode Enable" mask="0x10" name="WEN"/>
|
|
|
|
|
<bitfield caption="Window Interrupt Mode" mask="0x0C" name="WINTMODE" values="AC_WINTMODE"/>
|
|
|
|
|
<bitfield caption="Window Interrupt Level" mask="0x03" name="WINTLVL" values="AC_WINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status" name="STATUS" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Window Mode State" mask="0xC0" name="WSTATE" values="AC_WSTATE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 State" mask="0x20" name="AC1STATE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 State" mask="0x10" name="AC0STATE"/>
|
|
|
|
|
<bitfield caption="Window Mode Interrupt Flag" mask="0x04" name="WIF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 Interrupt Flag" mask="0x02" name="AC1IF"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 Interrupt Flag" mask="0x01" name="AC0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Current Source Control Register" name="CURRCTRL" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Current Source Enable" mask="0x80" name="CURREN"/>
|
|
|
|
|
<bitfield caption="Current Mode" mask="0x40" name="CURRMODE"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 1 current source output" mask="0x02" name="AC1CURR"/>
|
|
|
|
|
<bitfield caption="Analog Comparator 0 current source output" mask="0x01" name="AC0CURR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Current Source Calibration Register" name="CURRCALIB" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Current Source Calibration" mask="0x0F" name="CALIB"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Interrupt mode" name="AC_INTMODE">
|
|
|
|
|
<value caption="Interrupt on both edges" name="BOTHEDGES" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on falling edge" name="FALLING" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on rising edge" name="RISING" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="AC_INTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Hysteresis mode selection" name="AC_HYSMODE">
|
|
|
|
|
<value caption="No hysteresis" name="NO" value="0x00"/>
|
|
|
|
|
<value caption="Small hysteresis" name="SMALL" value="0x01"/>
|
|
|
|
|
<value caption="Large hysteresis" name="LARGE" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Positive input multiplexer selection" name="AC_MUXPOS">
|
|
|
|
|
<value caption="Pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Pin 2" name="PIN2" value="0x02"/>
|
|
|
|
|
<value caption="Pin 3" name="PIN3" value="0x03"/>
|
|
|
|
|
<value caption="Pin 4" name="PIN4" value="0x04"/>
|
|
|
|
|
<value caption="Pin 5" name="PIN5" value="0x05"/>
|
|
|
|
|
<value caption="Pin 6" name="PIN6" value="0x06"/>
|
|
|
|
|
<value caption="DAC output" name="DAC" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Negative input multiplexer selection" name="AC_MUXNEG">
|
|
|
|
|
<value caption="Pin 0" name="PIN0" value="0x00"/>
|
|
|
|
|
<value caption="Pin 1" name="PIN1" value="0x01"/>
|
|
|
|
|
<value caption="Pin 3" name="PIN3" value="0x02"/>
|
|
|
|
|
<value caption="Pin 5" name="PIN5" value="0x03"/>
|
|
|
|
|
<value caption="Pin 7" name="PIN7" value="0x04"/>
|
|
|
|
|
<value caption="DAC output" name="DAC" value="0x05"/>
|
|
|
|
|
<value caption="Bandgap Reference" name="BANDGAP" value="0x06"/>
|
|
|
|
|
<value caption="Internal voltage scaler" name="SCALER" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Windows interrupt mode" name="AC_WINTMODE">
|
|
|
|
|
<value caption="Interrupt on above window" name="ABOVE" value="0x00"/>
|
|
|
|
|
<value caption="Interrupt on inside window" name="INSIDE" value="0x01"/>
|
|
|
|
|
<value caption="Interrupt on below window" name="BELOW" value="0x02"/>
|
|
|
|
|
<value caption="Interrupt on outside window" name="OUTSIDE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Window interrupt level" name="AC_WINTLVL">
|
|
|
|
|
<value caption="Interrupt disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low priority" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium priority" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High priority" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Window mode state" name="AC_WSTATE">
|
|
|
|
|
<value caption="Signal above window" name="ABOVE" value="0x00"/>
|
|
|
|
|
<value caption="Signal inside window" name="INSIDE" value="0x01"/>
|
|
|
|
|
<value caption="Signal below window" name="BELOW" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="AC">
|
|
|
|
|
<interrupt index="0" name="AC0" caption="AC0 Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="AC1" caption="AC1 Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="ACW" caption="ACW Window Mode Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="RTC" id="I6093" version="XMEGAE" caption="Real-Time Clounter">
|
|
|
|
|
<register-group caption="Real-Time Counter" name="RTC" size="14">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Correction Enable" mask="0x08" name="CORREN"/>
|
|
|
|
|
<bitfield caption="Prescaling Factor" mask="0x07" name="PRESCALER" values="RTC_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Synchronization Busy Flag" mask="0x01" name="SYNCBUSY"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Compare Match Interrupt Level" mask="0x0C" name="COMPINTLVL"
|
|
|
|
|
values="RTC_COMPINTLVL"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Level" mask="0x03" name="OVFINTLVL" values="RTC_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flags" name="INTFLAGS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Compare Match Interrupt Flag" mask="0x02" name="COMPIF"/>
|
|
|
|
|
<bitfield caption="Overflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary register" name="TEMP" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Calibration Register" name="CALIB" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Correction Sign" mask="0x80" name="SIGN"/>
|
|
|
|
|
<bitfield caption="Error Value" mask="0x7F" name="ERROR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Count Register" name="CNT" offset="0x08" size="2"/>
|
|
|
|
|
<register caption="Period Register" name="PER" offset="0x0A" size="2"/>
|
|
|
|
|
<register caption="Compare Register" name="COMP" offset="0x0C" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Prescaler Factor" name="RTC_PRESCALER">
|
|
|
|
|
<value caption="RTC Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="RTC Clock" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="RTC Clock / 2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="RTC Clock / 8" name="DIV8" value="0x03"/>
|
|
|
|
|
<value caption="RTC Clock / 16" name="DIV16" value="0x04"/>
|
|
|
|
|
<value caption="RTC Clock / 64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="RTC Clock / 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="RTC Clock / 1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare Interrupt level" name="RTC_COMPINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Overflow Interrupt level" name="RTC_OVFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="RTC">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="COMP" caption="Compare Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="XCL" id="I3008" caption="XMEGA Custom Logic">
|
|
|
|
|
<register-group caption="XMEGA Custom Logic" name="XCL" size="16">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="LUT0 Output Enable" mask="0xC0" name="LUT0OUTEN" values="XCL_LUT0OUTEN"/>
|
|
|
|
|
<bitfield caption="Port Selection" mask="0x30" name="PORTSEL" values="XCL_PORTSEL"/>
|
|
|
|
|
<bitfield caption="LUT Configuration" mask="0x07" name="LUTCONF" values="XCL_LUTCONF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Input Selection 3" mask="0xC0" name="IN3SEL" values="XCL_INSEL"/>
|
|
|
|
|
<bitfield caption="Input Selection 2" mask="0x30" name="IN2SEL" values="XCL_INSEL"/>
|
|
|
|
|
<bitfield caption="Input Selection 1" mask="0x0C" name="IN1SEL" values="XCL_INSEL"/>
|
|
|
|
|
<bitfield caption="Input Selection 0" mask="0x03" name="IN0SEL" values="XCL_INSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Asynchronous Event Line Selection for LUT1" mask="0x80" name="EVASYSEL1"/>
|
|
|
|
|
<bitfield caption="Asynchronous Event Line Selection for LUT0" mask="0x40" name="EVASYSEL0"/>
|
|
|
|
|
<bitfield caption="Delay Selection" mask="0x30" name="DLYSEL" values="XCL_DLYSEL"/>
|
|
|
|
|
<bitfield caption="Delay Configuration on LUT1" mask="0x0C" name="DLY1CONF" values="XCL_DLYCONF"/>
|
|
|
|
|
<bitfield caption="Delay Configuration on LUT0" mask="0x03" name="DLY0CONF" values="XCL_DLYCONF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Truth Table of LUT1" mask="0xF0" name="TRUTH1"/>
|
|
|
|
|
<bitfield caption="Truth Table of LUT0" mask="0x0F" name="TRUTH0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Command Selection" mask="0x80" name="CMDSEL" values="XCL_CMDSEL"/>
|
|
|
|
|
<bitfield caption="Timer/Counter Selection" mask="0x70" name="TCSEL" values="XCL_TCSEL"/>
|
|
|
|
|
<bitfield caption="Clock Selection" mask="0x0F" name="CLKSEL" values="XCL_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F" name="CTRLF" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Command Enable" mask="0xC0" name="CMDEN" values="XCL_CMDEN"/>
|
|
|
|
|
<bitfield caption="Compare Channel 1 Output Value" mask="0x20" name="CMP1" values="XCL_CMPEN"/>
|
|
|
|
|
<bitfield caption="Compare Channel 0 Output Value" mask="0x10" name="CMP0" values="XCL_CMPEN"/>
|
|
|
|
|
<bitfield caption="Compare or Capture Channel 1 Enable" mask="0x08" name="CCEN1"/>
|
|
|
|
|
<bitfield caption="Compare or Capture Channel 0 Enable" mask="0x04" name="CCEN0"/>
|
|
|
|
|
<bitfield caption="Timer/Counter Mode" mask="0x03" name="MODE" values="XCL_TCMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G" name="CTRLG" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Event Action Enable" mask="0x80" name="EVACTEN"/>
|
|
|
|
|
<bitfield caption="Event Action Selection on Timer/Counter 1" mask="0x60" name="EVACT1"
|
|
|
|
|
values="XCL_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Action Selection on Timer/Counter 0" mask="0x18" name="EVACT0"
|
|
|
|
|
values="XCL_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Source Selection" mask="0x07" name="EVSRC" values="XCL_EVSRC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Underflow 1 Interrupt Enable" mask="0x80" name="UNF1IE"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 1 Interrupt Enable" mask="0x80" name="PEC1IE"/>
|
|
|
|
|
<bitfield caption="Peripheral High Counter 2 Interrupt Enable" mask="0x80" name="PEC21IE"/>
|
|
|
|
|
<bitfield caption="Underflow 0 Interrupt Enable" mask="0x40" name="UNF0IE"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 0 Interrupt Enable" mask="0x40" name="PEC0IE"/>
|
|
|
|
|
<bitfield caption="Compare Or Capture 1 Interrupt Enable" mask="0x20" name="CC1IE"/>
|
|
|
|
|
<bitfield caption="Peripheral Low Counter 2 Interrupt Enable" mask="0x20" name="PEC20IE"/>
|
|
|
|
|
<bitfield caption="Compare Or Capture 0 Interrupt Enable" mask="0x10" name="CC0IE"/>
|
|
|
|
|
<bitfield caption="Timer Underflow Interrupt Level" mask="0x0C" name="UNFINTLVL"
|
|
|
|
|
values="XCL_UNF_INTLVL"/>
|
|
|
|
|
<bitfield caption="Timer Compare or Capture Interrupt Level" mask="0x03" name="CCINTLVL"
|
|
|
|
|
values="XCL_CC_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter 1 Underflow Interrupt Flag" mask="0x80" name="UNF1IF"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 1 Interrupt Flag" mask="0x80" name="PEC1IF"/>
|
|
|
|
|
<bitfield caption="Peripheral High Counter 2 Interrupt Flag" mask="0x80" name="PEC21IF"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 0 Underflow Interrupt Flag" mask="0x40" name="UNF0IF"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 0 Interrupt Flag" mask="0x40" name="PEC0IF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture Channel 1 Interrupt Flag" mask="0x20" name="CC1IF"/>
|
|
|
|
|
<bitfield caption="Peripheral Low Counter 2 Interrupt Flag" mask="0x20" name="PEC20IF"/>
|
|
|
|
|
<bitfield caption="Compare or Capture Channel 0 Interrupt Flag" mask="0x10" name="CC0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Peripheral Lenght Control Register " name="PLC" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Peripheral Lenght Control Bits" mask="0xFF" name="PLC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Counter Register Low" name="CNTL" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="BTC0 Counter Byte" mask="0xFF" name="BCNTO"/>
|
|
|
|
|
<bitfield caption="TC16 Counter Low Byte" mask="0xFF" name="CNTL"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 0 Byte" mask="0xFF" name="PCNTO"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Counter Register High" name="CNTH" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="BTC1 Counter Byte" mask="0xFF" name="BCNT1"/>
|
|
|
|
|
<bitfield caption="TC16 Counter High Byte" mask="0xFF" name="CNTH"/>
|
|
|
|
|
<bitfield caption="Peripheral Counter 1 Byte" mask="0xFF" name="PCNT1"/>
|
|
|
|
|
<bitfield caption="Peripheral High Counter 2 Bits" mask="0xF0" name="PCNT21"/>
|
|
|
|
|
<bitfield caption="Peripheral Low Counter 2 Bits" mask="0x0F" name="PCNT20"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Compare Register Low" name="CMPL" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="TC16 Compare Low Byte" mask="0xFF" name="CMPL"/>
|
|
|
|
|
<bitfield caption="BTC0 Compare Byte" mask="0xFF" name="BCMP0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Compare Register High" name="CMPH" offset="0x0D" size="1">
|
|
|
|
|
<bitfield caption="TC16 Compare High Byte" mask="0xFF" name="CMPH"/>
|
|
|
|
|
<bitfield caption="BTC1 Compare Byte" mask="0xFF" name="BCMP1"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Period or Capture Register Low" name="PERCAPTL" offset="0x0E" size="1">
|
|
|
|
|
<bitfield caption="TC16 Low Byte Period" mask="0xFF" name="PERL"/>
|
|
|
|
|
<bitfield caption="TC16 Capture Value Low Byte" mask="0xFF" name="CAPTL"/>
|
|
|
|
|
<bitfield caption="BTC0 Period" mask="0xFF" name="BPER0"/>
|
|
|
|
|
<bitfield caption="BTC0 Capture Value Byte" mask="0xFF" name="BCAPT0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Period or Capture Register High" name="PERCAPTH" offset="0x0F" size="1">
|
|
|
|
|
<bitfield caption="TC16 High Byte Period" mask="0xFF" name="PERH"/>
|
|
|
|
|
<bitfield caption="TC16 Capture Value High Byte" mask="0xFF" name="CAPTH"/>
|
|
|
|
|
<bitfield caption="BTC1 Period" mask="0xFF" name="BPER1"/>
|
|
|
|
|
<bitfield caption="BTC1 Capture Value Byte" mask="0xFF" name="BCAPT1"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="LUT0 Output Enable" name="XCL_LUT0OUTEN">
|
|
|
|
|
<value caption="LUT0 output disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="LUT0 Output to pin 0" name="PIN0" value="0x01"/>
|
|
|
|
|
<value caption="LUT0 Output to pin 4" name="PIN4" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Port Selection" name="XCL_PORTSEL">
|
|
|
|
|
<value caption="Port C for LUT or USARTC0 for PEC" name="PC" value="0x00"/>
|
|
|
|
|
<value caption="Port D for LUT or USARTD0 for PEC" name="PD" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="LUT Configuration" name="XCL_LUTCONF">
|
|
|
|
|
<value caption="2-Input two LUT" name="2LUT2IN" value="0x00"/>
|
|
|
|
|
<value caption="Two LUT with duplicated input " name="2LUT1IN" value="0x01"/>
|
|
|
|
|
<value caption="Two LUT with one common input " name="2LUT3IN" value="0x02"/>
|
|
|
|
|
<value caption="3-Input LUT " name="1LUT3IN" value="0x03"/>
|
|
|
|
|
<value caption="One LUT Mux " name="MUX" value="0x04"/>
|
|
|
|
|
<value caption="One D-Latch LUT " name="DLATCH" value="0x05"/>
|
|
|
|
|
<value caption="One RS-Latch LUT " name="RSLATCH" value="0x06"/>
|
|
|
|
|
<value caption="One DFF LUT " name="DFF" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input Selection" name="XCL_INSEL">
|
|
|
|
|
<value caption="Event system selected as source" name="EVSYS" value="0x00"/>
|
|
|
|
|
<value caption="XCL selected as source" name="XCL" value="0x01"/>
|
|
|
|
|
<value caption="LSB port pin selected as source" name="PINL" value="0x02"/>
|
|
|
|
|
<value caption="MSB port pin selected as source" name="PINH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Delay Configuration on LUT" name="XCL_DLYCONF">
|
|
|
|
|
<value caption="Delay element disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Delay enabled on LUT input" name="IN" value="0x01"/>
|
|
|
|
|
<value caption="Delay enabled on LUT output" name="OUT" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Delay Selection" name="XCL_DLYSEL">
|
|
|
|
|
<value caption="One cycle delay for each LUT1 and LUT0" name="DLY11" value="0x00"/>
|
|
|
|
|
<value caption="One cycle delay for LUT1 and two cycles for LUT0" name="DLY12" value="0x01"/>
|
|
|
|
|
<value caption="Two cycles delay for LUT1 and one cycle for LUT0" name="DLY21" value="0x02"/>
|
|
|
|
|
<value caption="Two cycle delays for each LUT1 and LUT0" name="DLY22" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Clock Selection" name="XCL_CLKSEL">
|
|
|
|
|
<value caption="OFF" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Prescaler clk" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="Prescaler clk/2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="Prescaler clk/4" name="DIV4" value="0x03"/>
|
|
|
|
|
<value caption="Prescaler clk/8" name="DIV8" value="0x04"/>
|
|
|
|
|
<value caption="Prescaler clk/64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="Prescaler clk/256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="Prescaler clk/1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
<value caption="Event channel 0" name="EVCH0" value="0x08"/>
|
|
|
|
|
<value caption="Event channel 1" name="EVCH1" value="0x09"/>
|
|
|
|
|
<value caption="Event channel 2" name="EVCH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event channel 3" name="EVCH3" value="0x0B"/>
|
|
|
|
|
<value caption="Event channel 4" name="EVCH4" value="0x0C"/>
|
|
|
|
|
<value caption="Event channel 5" name="EVCH5" value="0x0D"/>
|
|
|
|
|
<value caption="Event channel 6" name="EVCH6" value="0x0E"/>
|
|
|
|
|
<value caption="Event channel 7" name="EVCH7" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Command Selection" name="XCL_CMDSEL">
|
|
|
|
|
<value caption="None" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Force restart" name="RESTART" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Selection" name="XCL_TCSEL">
|
|
|
|
|
<value caption="16-bit timer/counter" name="TC16" value="0x00"/>
|
|
|
|
|
<value caption="One 8-bit timer/counter" name="BTC0" value="0x01"/>
|
|
|
|
|
<value caption="Two 8-bit timer/counters" name="BTC01" value="0x02"/>
|
|
|
|
|
<value caption="One 8-bit timer/counter and one 8-bit peripheral transmitter counter" name="BTC0PEC1"
|
|
|
|
|
value="0x03"/>
|
|
|
|
|
<value caption="One 8-bit timer/counter and one 8-bit peripheral receiver counter" name="PEC0BTC1"
|
|
|
|
|
value="0x04"/>
|
|
|
|
|
<value caption="Two 8-bit peripheral counters" name="PEC01" value="0x05"/>
|
|
|
|
|
<value caption="One 8-bit timer/counter and two 4-bit peripheral counters" name="BTC0PEC2"
|
|
|
|
|
value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Mode" name="XCL_TCMODE">
|
|
|
|
|
<value caption="Normal mode with compare/period" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Capture mode" name="CAPT" value="0x01"/>
|
|
|
|
|
<value caption="Single Slope PWM" name="PWM" value="0x02"/>
|
|
|
|
|
<value caption="One-shot PWM" name="1SHOT" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare Output Value Timer" name="XCL_CMPEN">
|
|
|
|
|
<value caption="Clear WG Output " name="CLEAR" value="0x00"/>
|
|
|
|
|
<value caption="Set WG Output " name="SET" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Command Enable" name="XCL_CMDEN">
|
|
|
|
|
<value caption="Command Ignored" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Command valid for timer/counter 0" name="CMD0" value="0x01"/>
|
|
|
|
|
<value caption="Command valid for timer/counter 1" name="CMD1" value="0x02"/>
|
|
|
|
|
<value caption="Command valid for both timer/counter 0 and 1" name="CMD01" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Event Source Selection" name="XCL_EVSRC">
|
|
|
|
|
<value caption="Event channel 0" name="EVCH0" value="0x00"/>
|
|
|
|
|
<value caption="Event channel 1" name="EVCH1" value="0x01"/>
|
|
|
|
|
<value caption="Event channel 2" name="EVCH2" value="0x02"/>
|
|
|
|
|
<value caption="Event channel 3" name="EVCH3" value="0x03"/>
|
|
|
|
|
<value caption="Event channel 4" name="EVCH4" value="0x04"/>
|
|
|
|
|
<value caption="Event channel 5" name="EVCH5" value="0x05"/>
|
|
|
|
|
<value caption="Event channel 6" name="EVCH6" value="0x06"/>
|
|
|
|
|
<value caption="Event channel 7" name="EVCH7" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Event Action Selection" name="XCL_EVACT">
|
|
|
|
|
<value caption="Input Capture" name="INPUT" value="0x00"/>
|
|
|
|
|
<value caption="Frequency Capture" name="FREQ" value="0x01"/>
|
|
|
|
|
<value caption="Pulse Width Capture" name="PW" value="0x02"/>
|
|
|
|
|
<value caption="Restart timer/counter" name="RESTART" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Underflow Interrupt level" name="XCL_UNF_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare/Capture Interrupt level" name="XCL_CC_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="XCL">
|
|
|
|
|
<interrupt index="0" name="UNF" caption="Timer/Counter Underflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="CC" caption="Timer/Counter Compare or Capture Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TWI" id="I6089" version="XMEGAE" caption="Two-Wire Interface">
|
|
|
|
|
<register-group caption="Two-Wire Interface" name="TWI" size="14">
|
|
|
|
|
<register caption="TWI Common Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Bridge Enable" mask="0x80" name="BRIDGEEN"/>
|
|
|
|
|
<bitfield caption="Slave Fast Mode Plus Enable" mask="0x40" name="SFMPEN"/>
|
|
|
|
|
<bitfield caption="Slave SDA Hold Time Enable" mask="0x30" name="SSDAHOLD" values="TWI_SDAHOLD"/>
|
|
|
|
|
<bitfield caption="FMPLUS Enable" mask="0x08" name="FMPEN"/>
|
|
|
|
|
<bitfield caption="SDA Hold Time Enable" mask="0x06" name="SDAHOLD" values="TWI_SDAHOLD"/>
|
|
|
|
|
<bitfield caption="External Driver Interface Enable" mask="0x01" name="EDIEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register-group caption="TWI master module" name="MASTER" offset="0x0001" name-in-module="TWI_MASTER"/>
|
|
|
|
|
<register-group caption="TWI slave module" name="SLAVE" offset="0x0008" name-in-module="TWI_SLAVE"/>
|
|
|
|
|
<register-group caption="TWI SMBUS timeout module" name="TIMEOUT" offset="0x000E"
|
|
|
|
|
name-in-module="TWI_TIMEOUT"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="" name="TWI_MASTER" size="7">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0xC0" name="INTLVL" values="TWI_MASTER_INTLVL"/>
|
|
|
|
|
<bitfield caption="Read Interrupt Enable" mask="0x20" name="RIEN"/>
|
|
|
|
|
<bitfield caption="Write Interrupt Enable" mask="0x10" name="WIEN"/>
|
|
|
|
|
<bitfield caption="Enable TWI Master" mask="0x08" name="ENABLE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Inactive Bus Timeout" mask="0x0C" name="TIMEOUT" values="TWI_MASTER_TIMEOUT"/>
|
|
|
|
|
<bitfield caption="Quick Command Enable" mask="0x02" name="QCEN"/>
|
|
|
|
|
<bitfield caption="Smart Mode Enable" mask="0x01" name="SMEN"/>
|
|
|
|
|
<bitfield caption="Ttimeout Enable" mask="0x10" name="TTOUTEN"/>
|
|
|
|
|
<bitfield caption="Slave Extend Timeout Enable" mask="0x20" name="TSEXTEN"/>
|
|
|
|
|
<bitfield caption="Master Extend Timeout Enable" mask="0x40" name="TMEXTEN"/>
|
|
|
|
|
<bitfield caption="Timeout Interrupt Enable" mask="0x80" name="TOIE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Acknowledge Action" mask="0x04" name="ACKACT"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x03" name="CMD" values="TWI_MASTER_CMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Read Interrupt Flag" mask="0x80" name="RIF"/>
|
|
|
|
|
<bitfield caption="Write Interrupt Flag" mask="0x40" name="WIF"/>
|
|
|
|
|
<bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD"/>
|
|
|
|
|
<bitfield caption="Received Acknowledge" mask="0x10" name="RXACK"/>
|
|
|
|
|
<bitfield caption="Arbitration Lost" mask="0x08" name="ARBLOST"/>
|
|
|
|
|
<bitfield caption="Bus Error" mask="0x04" name="BUSERR"/>
|
|
|
|
|
<bitfield caption="Bus State" mask="0x03" name="BUSSTATE" values="TWI_MASTER_BUSSTATE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register" name="BAUD" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Address Register" name="ADDR" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x06" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="" name="TWI_SLAVE" size="6">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Level" mask="0xC0" name="INTLVL" values="TWI_SLAVE_INTLVL"/>
|
|
|
|
|
<bitfield caption="Data Interrupt Enable" mask="0x20" name="DIEN"/>
|
|
|
|
|
<bitfield caption="Address/Stop Interrupt Enable" mask="0x10" name="APIEN"/>
|
|
|
|
|
<bitfield caption="Enable TWI Slave" mask="0x08" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Stop Interrupt Enable" mask="0x04" name="PIEN"/>
|
|
|
|
|
<bitfield caption="Promiscuous Mode Enable" mask="0x02" name="PMEN"/>
|
|
|
|
|
<bitfield caption="Smart Mode Enable" mask="0x01" name="SMEN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Acknowledge Action" mask="0x04" name="ACKACT"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x03" name="CMD" values="TWI_SLAVE_CMD"/>
|
|
|
|
|
<bitfield caption="Ttimeout Enable" mask="0x10" name="TTOUTEN"/>
|
|
|
|
|
<bitfield caption="Timeout Interrupt Enable" mask="0x80" name="TOIE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Data Interrupt Flag" mask="0x80" name="DIF"/>
|
|
|
|
|
<bitfield caption="Address/Stop Interrupt Flag" mask="0x40" name="APIF"/>
|
|
|
|
|
<bitfield caption="Clock Hold" mask="0x20" name="CLKHOLD"/>
|
|
|
|
|
<bitfield caption="Received Acknowledge" mask="0x10" name="RXACK"/>
|
|
|
|
|
<bitfield caption="Collision" mask="0x08" name="COLL"/>
|
|
|
|
|
<bitfield caption="Bus Error" mask="0x04" name="BUSERR"/>
|
|
|
|
|
<bitfield caption="Read/Write Direction" mask="0x02" name="DIR"/>
|
|
|
|
|
<bitfield caption="Slave Address or Stop" mask="0x01" name="AP"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Address Register" name="ADDR" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Address Mask Register" name="ADDRMASK" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Address Mask" mask="0xFE" name="ADDRMASK"/>
|
|
|
|
|
<bitfield caption="Address Enable" mask="0x01" name="ADDREN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="" name="TWI_TIMEOUT" size="2">
|
|
|
|
|
<register caption="Timeout Status Register" name="TOS" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Master Ttimeout Interrupt Flag" mask="0x01" name="TTOUTMIF"/>
|
|
|
|
|
<bitfield caption="Slave Extend Interrupt Flag" mask="0x02" name="TSEXTIF"/>
|
|
|
|
|
<bitfield caption="Master Extend Interrupt Flag" mask="0x04" name="TMEXTIF"/>
|
|
|
|
|
<bitfield caption="Slave Ttimeout Interrupt Flag" mask="0x10" name="TTOUTSIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Timeout Configuration Register" name="TOCONF" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Master Ttimeout Select" mask="0x07" name="TTOUTMSEL"
|
|
|
|
|
values="TWI_MASTER_TTIMEOUT"/>
|
|
|
|
|
<bitfield caption="Master/Slave Timeout Select" mask="0x18" name="TMSEXTSEL"
|
|
|
|
|
values="TWI_MASTER_TMSEXT"/>
|
|
|
|
|
<bitfield caption="Slave Ttimeout Select" mask="0xE0" name="TTOUTSSEL" values="TWI_SLAVE_TTIMEOUT"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="SDA Hold Time" name="TWI_SDAHOLD">
|
|
|
|
|
<value caption="SDA Hold Time off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="SDA Hold Time 50 ns" name="50NS" value="0x01"/>
|
|
|
|
|
<value caption="SDA Hold Time 300 ns" name="300NS" value="0x02"/>
|
|
|
|
|
<value caption="SDA Hold Time 400 ns" name="400NS" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Interrupt Level" name="TWI_MASTER_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Inactive Timeout" name="TWI_MASTER_TIMEOUT">
|
|
|
|
|
<value caption="Bus Timeout Disabled" name="DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="50 Microseconds" name="50US" value="0x01"/>
|
|
|
|
|
<value caption="100 Microseconds" name="100US" value="0x02"/>
|
|
|
|
|
<value caption="200 Microseconds" name="200US" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Command" name="TWI_MASTER_CMD">
|
|
|
|
|
<value caption="No Action" name="NOACT" value="0x00"/>
|
|
|
|
|
<value caption="Issue Repeated Start Condition" name="REPSTART" value="0x01"/>
|
|
|
|
|
<value caption="Receive or Transmit Data" name="RECVTRANS" value="0x02"/>
|
|
|
|
|
<value caption="Issue Stop Condition" name="STOP" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Bus State" name="TWI_MASTER_BUSSTATE">
|
|
|
|
|
<value caption="Unknown Bus State" name="UNKNOWN" value="0x00"/>
|
|
|
|
|
<value caption="Bus is Idle" name="IDLE" value="0x01"/>
|
|
|
|
|
<value caption="This Module Controls The Bus" name="OWNER" value="0x02"/>
|
|
|
|
|
<value caption="The Bus is Busy" name="BUSY" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Slave Interrupt Level" name="TWI_SLAVE_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Slave Command" name="TWI_SLAVE_CMD">
|
|
|
|
|
<value caption="No Action" name="NOACT" value="0x00"/>
|
|
|
|
|
<value caption="Used To Complete a Transaction" name="COMPTRANS" value="0x02"/>
|
|
|
|
|
<value caption="Used in Response to Address/Data Interrupt" name="RESPONSE" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master Timeout" name="TWI_MASTER_TTIMEOUT">
|
|
|
|
|
<value caption="25 Milliseconds" name="25MS" value="0x000"/>
|
|
|
|
|
<value caption="24 Milliseconds" name="24MS" value="0x001"/>
|
|
|
|
|
<value caption="23 Milliseconds" name="23MS" value="0x002"/>
|
|
|
|
|
<value caption="22 Milliseconds" name="22MS" value="0x003"/>
|
|
|
|
|
<value caption="26 Milliseconds" name="26MS" value="0x004"/>
|
|
|
|
|
<value caption="27 Milliseconds" name="27MS" value="0x005"/>
|
|
|
|
|
<value caption="28 Milliseconds" name="28MS" value="0x006"/>
|
|
|
|
|
<value caption="29 Milliseconds" name="29MS" value="0x007"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Slave Ttimeout" name="TWI_SLAVE_TTIMEOUT">
|
|
|
|
|
<value caption="25 Milliseconds" name="25MS" value="0x000"/>
|
|
|
|
|
<value caption="24 Milliseconds" name="24MS" value="0x001"/>
|
|
|
|
|
<value caption="23 Milliseconds" name="23MS" value="0x002"/>
|
|
|
|
|
<value caption="22 Milliseconds" name="22MS" value="0x003"/>
|
|
|
|
|
<value caption="26 Milliseconds" name="26MS" value="0x004"/>
|
|
|
|
|
<value caption="27 Milliseconds" name="27MS" value="0x005"/>
|
|
|
|
|
<value caption="28 Milliseconds" name="28MS" value="0x006"/>
|
|
|
|
|
<value caption="29 Milliseconds" name="29MS" value="0x007"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Master/Slave Extend Timeout" name="TWI_MASTER_TMSEXT">
|
|
|
|
|
<value caption="Tmext 10ms Tsext 25ms" name="10MS25MS" value="0x00"/>
|
|
|
|
|
<value caption="Tmext 9ms Tsext 24ms" name="9MS24MS" value="0x01"/>
|
|
|
|
|
<value caption="Tmext 11ms Tsext 26ms" name="11MS26MS" value="0x02"/>
|
|
|
|
|
<value caption="Tmext 12ms Tsext 27ms" name="12MS27MS" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="TWI">
|
|
|
|
|
<interrupt index="0" name="TWIS" caption="TWI Slave Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="TWIM" caption="TWI Master Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="PORT" id="I6075" version="XMEGAE" caption="Port Configuration">
|
|
|
|
|
<register-group caption="I/O Ports" name="PORT" size="24">
|
|
|
|
|
<register caption="I/O Port Data Direction" name="DIR" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Set" name="DIRSET" offset="0x01" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Clear" name="DIRCLR" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="I/O Port Data Direction Toggle" name="DIRTGL" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output" name="OUT" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Set" name="OUTSET" offset="0x05" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Clear" name="OUTCLR" offset="0x06" size="1"/>
|
|
|
|
|
<register caption="I/O Port Output Toggle" name="OUTTGL" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="I/O port Input" name="IN" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Port Interrupt Level" mask="0x03" name="INTLVL" values="PORT_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Port Interrupt Mask" name="INTMASK" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Pin 7 Interrupt Flag" mask="0x80" name="INT7IF"/>
|
|
|
|
|
<bitfield caption="Pin 6 Interrupt Flag" mask="0x40" name="INT6IF"/>
|
|
|
|
|
<bitfield caption="Pin 5 Interrupt Flag" mask="0x20" name="INT5IF"/>
|
|
|
|
|
<bitfield caption="Pin 4 Interrupt Flag" mask="0x10" name="INT4IF"/>
|
|
|
|
|
<bitfield caption="Pin 3 Interrupt Flag" mask="0x08" name="INT3IF"/>
|
|
|
|
|
<bitfield caption="Pin 2 Interrupt Flag" mask="0x04" name="INT2IF"/>
|
|
|
|
|
<bitfield caption="Pin 1 Interrupt Flag" mask="0x02" name="INT1IF"/>
|
|
|
|
|
<bitfield caption="Pin 0 Interrupt Flag" mask="0x01" name="INT0IF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin Remap Register" name="REMAP" offset="0x0E" size="1">
|
|
|
|
|
<bitfield caption="Usart0" mask="0x10" name="USART0"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 4 Output Compare D" mask="0x08" name="TC4D"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 4 Output Compare C" mask="0x04" name="TC4C"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 4 Output Compare B" mask="0x02" name="TC4B"/>
|
|
|
|
|
<bitfield caption="Timer/Counter 4 Output Compare A" mask="0x01" name="TC4A"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 0 Control Register" name="PIN0CTRL" offset="0x10" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 1 Control Register" name="PIN1CTRL" offset="0x11" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 2 Control Register" name="PIN2CTRL" offset="0x12" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 3 Control Register" name="PIN3CTRL" offset="0x13" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 4 Control Register" name="PIN4CTRL" offset="0x14" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 5 Control Register" name="PIN5CTRL" offset="0x15" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 6 Control Register" name="PIN6CTRL" offset="0x16" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pin 7 Control Register" name="PIN7CTRL" offset="0x17" size="1">
|
|
|
|
|
<bitfield caption="Inverted I/O Enable" mask="0x40" name="INVEN"/>
|
|
|
|
|
<bitfield caption="Output/Pull Configuration" mask="0x38" name="OPC" values="PORT_OPC"/>
|
|
|
|
|
<bitfield caption="Input/Sense Configuration" mask="0x07" name="ISC" values="PORT_ISC"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Port Interrupt Level" name="PORT_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Output/Pull Configuration" name="PORT_OPC">
|
|
|
|
|
<value caption="Totempole" name="TOTEM" value="0x00"/>
|
|
|
|
|
<value caption="Totempole w/ Bus keeper on Input and Output" name="BUSKEEPER" value="0x01"/>
|
|
|
|
|
<value caption="Totempole w/ Pull-down on Input" name="PULLDOWN" value="0x02"/>
|
|
|
|
|
<value caption="Totempole w/ Pull-up on Input" name="PULLUP" value="0x03"/>
|
|
|
|
|
<value caption="Wired OR" name="WIREDOR" value="0x04"/>
|
|
|
|
|
<value caption="Wired AND" name="WIREDAND" value="0x05"/>
|
|
|
|
|
<value caption="Wired OR w/ Pull-down" name="WIREDORPULL" value="0x06"/>
|
|
|
|
|
<value caption="Wired AND w/ Pull-up" name="WIREDANDPULL" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Input/Sense Configuration" name="PORT_ISC">
|
|
|
|
|
<value caption="Sense Both Edges" name="BOTHEDGES" value="0x00"/>
|
|
|
|
|
<value caption="Sense Rising Edge" name="RISING" value="0x01"/>
|
|
|
|
|
<value caption="Sense Falling Edge" name="FALLING" value="0x02"/>
|
|
|
|
|
<value caption="Sense Level (Transparent For Events)" name="LEVEL" value="0x03"/>
|
|
|
|
|
<value caption="Digital Input Buffer Forced Enable" name="FORCE_ENABLE" value="0x06"/>
|
|
|
|
|
<value caption="Disable Digital Input Buffer" name="INPUT_DISABLE" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="PORT">
|
|
|
|
|
<interrupt index="0" name="INT" caption="External Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="TC" id="I3007" version="XMEGAE" caption="16-bit Timer/Counter With PWM">
|
|
|
|
|
<register-group caption="16-bit Timer/Counter 4" name="TC4" size="64">
|
2021-09-17 22:44:36 +01:00
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
|
|
|
|
|
<bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
|
|
|
|
|
<bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
|
|
|
|
|
<bitfield caption="Clock Select" mask="0x0F" name="CLKSEL" values="TC45_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Byte Mode" mask="0xC0" name="BYTEM" values="TC45_BYTEM"/>
|
|
|
|
|
<bitfield caption="Circular Buffer Enable" mask="0x30" name="CIRCEN" values="TC45_CIRCEN"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x07" name="WGMODE" values="TC45_WGMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Channel D Output Polarity" mask="0x80" name="POLD"/>
|
|
|
|
|
<bitfield caption="Channel C Output Polarity" mask="0x40" name="POLC"/>
|
|
|
|
|
<bitfield caption="Channel B Output Polarity" mask="0x20" name="POLB"/>
|
|
|
|
|
<bitfield caption="Channel A Output Polarity" mask="0x10" name="POLA"/>
|
|
|
|
|
<bitfield caption="Channel D Compare Output Value" mask="0x08" name="CMPD"/>
|
|
|
|
|
<bitfield caption="Channel C Compare Output Value" mask="0x04" name="CMPC"/>
|
|
|
|
|
<bitfield caption="Channel B Compare Output Value" mask="0x02" name="CMPB"/>
|
|
|
|
|
<bitfield caption="Channel A Compare Output Value" mask="0x01" name="CMPA"/>
|
|
|
|
|
<bitfield caption="High Channel D Compare Output Value" mask="0x80" name="HCMPD"/>
|
|
|
|
|
<bitfield caption="High Channel C Compare Output Value" mask="0x40" name="HCMPC"/>
|
|
|
|
|
<bitfield caption="High Channel B Compare Output Value" mask="0x20" name="HCMPB"/>
|
|
|
|
|
<bitfield caption="High Channel A Compare Output Value" mask="0x10" name="HCMPA"/>
|
|
|
|
|
<bitfield caption="Low Channel D Compare Output Value" mask="0x08" name="LCMPD"/>
|
|
|
|
|
<bitfield caption="Low Channel C Compare Output Value" mask="0x04" name="LCMPC"/>
|
|
|
|
|
<bitfield caption="Low Channel B Compare Output Value" mask="0x02" name="LCMPB"/>
|
|
|
|
|
<bitfield caption="Low Channel A Compare Output Value" mask="0x01" name="LCMPA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Action" mask="0xE0" name="EVACT" values="TC45_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Delay" mask="0x10" name="EVDLY"/>
|
|
|
|
|
<bitfield caption="Event Source Select" mask="0x0F" name="EVSEL" values="TC45_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Channel D Compare or Capture Mode" mask="0xC0" name="CCDMODE"
|
|
|
|
|
values="TC45_CCDMODE"/>
|
|
|
|
|
<bitfield caption="Channel C Compare or Capture Mode" mask="0x30" name="CCCMODE"
|
|
|
|
|
values="TC45_CCCMODE"/>
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Mode" mask="0x0C" name="CCBMODE"
|
|
|
|
|
values="TC45_CCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Mode" mask="0x03" name="CCAMODE"
|
|
|
|
|
values="TC45_CCAMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low D Compare or Capture Mode" mask="0xC0" name="LCCDMODE"
|
|
|
|
|
values="TC45_LCCDMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low C Compare or Capture Mode" mask="0x30" name="LCCCMODE"
|
|
|
|
|
values="TC45_LCCCMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Mode" mask="0x0C" name="LCCBMODE"
|
|
|
|
|
values="TC45_LCCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Mode" mask="0x03" name="LCCAMODE"
|
|
|
|
|
values="TC45_LCCAMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F" name="CTRLF" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Channel High D Compare or Capture Mode" mask="0xC0" name="HCCDMODE"
|
|
|
|
|
values="TC45_HCCDMODE"/>
|
|
|
|
|
<bitfield caption="Channel High C Compare or Capture Mode" mask="0x30" name="HCCCMODE"
|
|
|
|
|
values="TC45_HCCCMODE"/>
|
|
|
|
|
<bitfield caption="Channel High B Compare or Capture Mode" mask="0x0C" name="HCCBMODE"
|
|
|
|
|
values="TC45_HCCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel High A Compare or Capture Mode" mask="0x03" name="HCCAMODE"
|
|
|
|
|
values="TC45_HCCAMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Timer Trigger Restart Interrupt Level" mask="0x30" name="TRGINTLVL"
|
|
|
|
|
values="TC45_TRGINTLVL"/>
|
|
|
|
|
<bitfield caption="Timer Error Interrupt Level" mask="0x0C" name="ERRINTLVL"
|
|
|
|
|
values="TC45_ERRINTLVL"/>
|
|
|
|
|
<bitfield caption="Timer Overflow/Underflow Interrupt Level" mask="0x03" name="OVFINTLVL"
|
|
|
|
|
values="TC45_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Channel D Compare or Capture Interrupt Level" mask="0xC0" name="CCDINTLVL"
|
|
|
|
|
values="TC45_CCDINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel C Compare or Capture Interrupt Level" mask="0x30" name="CCCINTLVL"
|
|
|
|
|
values="TC45_CCCINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Interrupt Level" mask="0x0C" name="CCBINTLVL"
|
|
|
|
|
values="TC45_CCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Interrupt Level" mask="0x03" name="CCAINTLVL"
|
|
|
|
|
values="TC45_CCAINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low D Compare or Capture Interrupt Level" mask="0xC0" name="LCCDINTLVL"
|
|
|
|
|
values="TC45_LCCDINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low C Compare or Capture Interrupt Level" mask="0x30" name="LCCCINTLVL"
|
|
|
|
|
values="TC45_LCCCINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Interrupt Level" mask="0x0C" name="LCCBINTLVL"
|
|
|
|
|
values="TC45_LCCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Interrupt Level" mask="0x03" name="LCCAINTLVL"
|
|
|
|
|
values="TC45_LCCAINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Clear" name="CTRLGCLR" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Stop" mask="0x20" name="STOP"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC45_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Counter Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Set" name="CTRLGSET" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Stop" mask="0x20" name="STOP"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC45_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Counter Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register H Clear" name="CTRLHCLR" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Channel D Compare or Capture Buffer Valid" mask="0x10" name="CCDBV"/>
|
|
|
|
|
<bitfield caption="Channel C Compare or Capture Buffer Valid" mask="0x08" name="CCCBV"/>
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
<bitfield caption="Channel Low D Compare or Capture Buffer Valid" mask="0x10" name="LCCDBV"/>
|
|
|
|
|
<bitfield caption="Channel Low C Compare or Capture Buffer Valid" mask="0x08" name="LCCCBV"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Buffer Valid" mask="0x04" name="LCCBBV"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Buffer Valid" mask="0x02" name="LCCABV"/>
|
|
|
|
|
<bitfield caption="Period Low Buffer Valid" mask="0x01" name="LPERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register H Set" name="CTRLHSET" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Channel D Compare or Capture Buffer Valid" mask="0x10" name="CCDBV"/>
|
|
|
|
|
<bitfield caption="Channel C Compare or Capture Buffer Valid" mask="0x08" name="CCCBV"/>
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
<bitfield caption="Channel Low D Compare or Capture Buffer Valid" mask="0x10" name="LCCDBV"/>
|
|
|
|
|
<bitfield caption="Channel Low C Compare or Capture Buffer Valid" mask="0x08" name="LCCCBV"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Buffer Valid" mask="0x04" name="LCCBBV"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Buffer Valid" mask="0x02" name="LCCABV"/>
|
|
|
|
|
<bitfield caption="Period Low Buffer Valid" mask="0x01" name="LPERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Channel D Compare or Capture Interrupt Flag" mask="0x80" name="CCDIF"/>
|
|
|
|
|
<bitfield caption="Channel C Compare or Capture Interrupt Flag" mask="0x40" name="CCCIF"/>
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Interrupt Flag" mask="0x20" name="CCBIF"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Interrupt Flag" mask="0x10" name="CCAIF"/>
|
|
|
|
|
<bitfield caption="Trigger Restart Interrupt Flag" mask="0x04" name="TRGIF"/>
|
|
|
|
|
<bitfield caption="Error Interrupt Flag" mask="0x02" name="ERRIF"/>
|
|
|
|
|
<bitfield caption="Overflow/Underflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
<bitfield caption="Channel Low D Compare or Capture Interrupt Flag" mask="0x80" name="LCCDIF"/>
|
|
|
|
|
<bitfield caption="Channel Low C Compare or Capture Interrupt Flag" mask="0x40" name="LCCCIF"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Interrupt Flag" mask="0x20" name="LCCBIF"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Interrupt Flag" mask="0x10" name="LCCAIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register For 16-bit Access" name="TEMP" offset="0x0F" size="1"/>
|
|
|
|
|
<register caption="Count" name="CNT" offset="0x20" size="2"/>
|
|
|
|
|
<register caption="Period" name="PER" offset="0x26" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture A" name="CCA" offset="0x28" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture B" name="CCB" offset="0x2A" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture C" name="CCC" offset="0x2C" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture D" name="CCD" offset="0x2E" size="2"/>
|
|
|
|
|
<register caption="Period Buffer" name="PERBUF" offset="0x36" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture A Buffer" name="CCABUF" offset="0x38" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture B Buffer" name="CCBBUF" offset="0x3A" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture C Buffer" name="CCCBUF" offset="0x3C" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture D Buffer" name="CCDBUF" offset="0x3E" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="16-bit Timer/Counter 5" name="TC5" size="64">
|
2021-09-17 22:44:36 +01:00
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
2021-04-04 21:04:12 +01:00
|
|
|
<bitfield caption="Synchronization Enabled" mask="0x40" name="SYNCHEN"/>
|
|
|
|
|
<bitfield caption="Start on Next Event" mask="0x20" name="EVSTART"/>
|
|
|
|
|
<bitfield caption="Stop on Next Update" mask="0x10" name="UPSTOP"/>
|
|
|
|
|
<bitfield caption="Clock Select" mask="0x0F" name="CLKSEL" values="TC45_CLKSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Byte Mode" mask="0xC0" name="BYTEM" values="TC45_BYTEM"/>
|
|
|
|
|
<bitfield caption="Circular Buffer Enable" mask="0x30" name="CIRCEN" values="TC45_CIRCEN"/>
|
|
|
|
|
<bitfield caption="Waveform Generation Mode" mask="0x07" name="WGMODE" values="TC45_WGMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control register C" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Channel B Output Polarity" mask="0x20" name="POLB"/>
|
|
|
|
|
<bitfield caption="Channel A Output Polarity" mask="0x10" name="POLA"/>
|
|
|
|
|
<bitfield caption="Channel B Compare Output Value" mask="0x02" name="CMPB"/>
|
|
|
|
|
<bitfield caption="Channel A Compare Output Value" mask="0x01" name="CMPA"/>
|
|
|
|
|
<bitfield caption="High Channel B Compare Output Value" mask="0x20" name="HCMPB"/>
|
|
|
|
|
<bitfield caption="High Channel A Compare Output Value" mask="0x10" name="HCMPA"/>
|
|
|
|
|
<bitfield caption="Low Channel B Compare Output Value" mask="0x02" name="LCMPB"/>
|
|
|
|
|
<bitfield caption="Low Channel A Compare Output Value" mask="0x01" name="LCMPA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Event Action" mask="0xE0" name="EVACT" values="TC45_EVACT"/>
|
|
|
|
|
<bitfield caption="Event Delay" mask="0x10" name="EVDLY"/>
|
|
|
|
|
<bitfield caption="Event Source Select" mask="0x0F" name="EVSEL" values="TC45_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register E" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Mode" mask="0x0C" name="CCBMODE"
|
|
|
|
|
values="TC45_CCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Mode" mask="0x03" name="CCAMODE"
|
|
|
|
|
values="TC45_CCAMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Mode" mask="0x0C" name="LCCBMODE"
|
|
|
|
|
values="TC45_LCCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Mode" mask="0x03" name="LCCAMODE"
|
|
|
|
|
values="TC45_LCCAMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register F" name="CTRLF" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Channel High B Compare or Capture Mode" mask="0x0C" name="HCCBMODE"
|
|
|
|
|
values="TC45_HCCBMODE"/>
|
|
|
|
|
<bitfield caption="Channel High A Compare or Capture Mode" mask="0x03" name="HCCAMODE"
|
|
|
|
|
values="TC45_HCCAMODE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register A" name="INTCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Timer Trigger Restart Interrupt Level" mask="0x30" name="TRGINTLVL"
|
|
|
|
|
values="TC45_TRGINTLVL"/>
|
|
|
|
|
<bitfield caption="Timer Error Interrupt Level" mask="0x0C" name="ERRINTLVL"
|
|
|
|
|
values="TC45_ERRINTLVL"/>
|
|
|
|
|
<bitfield caption="Timer Overflow/Underflow Interrupt Level" mask="0x03" name="OVFINTLVL"
|
|
|
|
|
values="TC45_OVFINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register B" name="INTCTRLB" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Interrupt Level" mask="0x0C" name="CCBINTLVL"
|
|
|
|
|
values="TC45_CCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Interrupt Level" mask="0x03" name="CCAINTLVL"
|
|
|
|
|
values="TC45_CCAINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Interrupt Level" mask="0x0C" name="LCCBINTLVL"
|
|
|
|
|
values="TC45_LCCBINTLVL"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Interrupt Level" mask="0x03" name="LCCAINTLVL"
|
|
|
|
|
values="TC45_LCCAINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Clear" name="CTRLGCLR" offset="0x08" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Stop" mask="0x20" name="STOP"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC45_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Counter Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Set" name="CTRLGSET" offset="0x09" size="1">
|
|
|
|
|
<bitfield caption="Timer/Counter Stop" mask="0x10" name="STOP"/>
|
|
|
|
|
<bitfield caption="Command" mask="0x0C" name="CMD" values="TC45_CMD"/>
|
|
|
|
|
<bitfield caption="Lock Update" mask="0x02" name="LUPD"/>
|
|
|
|
|
<bitfield caption="Counter Direction" mask="0x01" name="DIR"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register H Clear" name="CTRLHCLR" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Buffer Valid" mask="0x04" name="LCCBBV"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Buffer Valid" mask="0x02" name="LCCABV"/>
|
|
|
|
|
<bitfield caption="Period Low Buffer Valid" mask="0x01" name="LPERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register H Set" name="CTRLHSET" offset="0x0B" size="1">
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Buffer Valid" mask="0x04" name="CCBBV"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Buffer Valid" mask="0x02" name="CCABV"/>
|
|
|
|
|
<bitfield caption="Period Buffer Valid" mask="0x01" name="PERBV"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Buffer Valid" mask="0x04" name="LCCBBV"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Buffer Valid" mask="0x02" name="LCCABV"/>
|
|
|
|
|
<bitfield caption="Period Low Buffer Valid" mask="0x01" name="LPERBV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Flag Register" name="INTFLAGS" offset="0x0C" size="1">
|
|
|
|
|
<bitfield caption="Channel B Compare or Capture Interrupt Flag" mask="0x20" name="CCBIF"/>
|
|
|
|
|
<bitfield caption="Channel A Compare or Capture Interrupt Flag" mask="0x10" name="CCAIF"/>
|
|
|
|
|
<bitfield caption="Trigger Restart Interrupt Flag" mask="0x04" name="TRGIF"/>
|
|
|
|
|
<bitfield caption="Error Interrupt Flag" mask="0x02" name="ERRIF"/>
|
|
|
|
|
<bitfield caption="Overflow/Underflow Interrupt Flag" mask="0x01" name="OVFIF"/>
|
|
|
|
|
<bitfield caption="Channel Low B Compare or Capture Interrupt Flag" mask="0x20" name="LCCBIF"/>
|
|
|
|
|
<bitfield caption="Channel Low A Compare or Capture Interrupt Flag" mask="0x10" name="LCCAIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Temporary Register For 16-bit Access" name="TEMP" offset="0x0F" size="1"/>
|
|
|
|
|
<register caption="Count" name="CNT" offset="0x20" size="2"/>
|
|
|
|
|
<register caption="Period" name="PER" offset="0x26" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture A" name="CCA" offset="0x28" size="2"/>
|
|
|
|
|
<register caption="Compare or Capture B" name="CCB" offset="0x2A" size="2"/>
|
|
|
|
|
<register caption="Period Buffer" name="PERBUF" offset="0x36" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture A Buffer" name="CCABUF" offset="0x38" size="2"/>
|
|
|
|
|
<register caption="Compare Or Capture B Buffer" name="CCBBUF" offset="0x3A" size="2"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Clock Selection" name="TC45_CLKSEL">
|
|
|
|
|
<value caption="Timer Off" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="System Clock" name="DIV1" value="0x01"/>
|
|
|
|
|
<value caption="System Clock / 2" name="DIV2" value="0x02"/>
|
|
|
|
|
<value caption="System Clock / 4" name="DIV4" value="0x03"/>
|
|
|
|
|
<value caption="System Clock / 8" name="DIV8" value="0x04"/>
|
|
|
|
|
<value caption="System Clock / 64" name="DIV64" value="0x05"/>
|
|
|
|
|
<value caption="System Clock / 256" name="DIV256" value="0x06"/>
|
|
|
|
|
<value caption="System Clock / 1024" name="DIV1024" value="0x07"/>
|
|
|
|
|
<value caption="Event Channel 0" name="EVCH0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="EVCH1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="EVCH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="EVCH3" value="0x0B"/>
|
|
|
|
|
<value caption="Event Channel 4" name="EVCH4" value="0x0C"/>
|
|
|
|
|
<value caption="Event Channel 5" name="EVCH5" value="0x0D"/>
|
|
|
|
|
<value caption="Event Channel 6" name="EVCH6" value="0x0E"/>
|
|
|
|
|
<value caption="Event Channel 7" name="EVCH7" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Byte Mode" name="TC45_BYTEM">
|
|
|
|
|
<value caption="16-bit mode" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Timer/Counter Operating in Byte Mode Only" name="BYTEMODE" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Circular Enable Mode" name="TC45_CIRCEN">
|
|
|
|
|
<value caption="Circular Buffer Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Circular Buffer Enabled on PER/PERBUF" name="PER" value="0x01"/>
|
|
|
|
|
<value caption="Circular Buffer Enabled on CCA/CCABUF" name="CCA" value="0x02"/>
|
|
|
|
|
<value caption="Circular Buffer Enabled on All Buffered Registers" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Waveform Generation Mode" name="TC45_WGMODE">
|
|
|
|
|
<value caption="Normal Mode" name="NORMAL" value="0x00"/>
|
|
|
|
|
<value caption="Frequency Generation Mode" name="FRQ" value="0x01"/>
|
|
|
|
|
<value caption="Single Slope" name="SINGLESLOPE" value="0x03"/>
|
|
|
|
|
<value caption="Dual Slope, Update on TOP" name="DSTOP" value="0x05"/>
|
|
|
|
|
<value caption="Dual Slope, Both" name="DSBOTH" value="0x06"/>
|
|
|
|
|
<value caption="Dual Slope, Update on BOTTOM" name="DSBOTTOM" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Action" name="TC45_EVACT">
|
|
|
|
|
<value caption="No Event Action" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Fault Mode 1 capture" name="FMODE1" value="0x01"/>
|
|
|
|
|
<value caption="Fault Mode 2 capture" name="FMODE2" value="0x02"/>
|
|
|
|
|
<value caption="Up/down count" name="UPDOWN" value="0x03"/>
|
|
|
|
|
<value caption="Quadrature decode" name="QDEC" value="0x04"/>
|
|
|
|
|
<value caption="Restart" name="RESTART" value="0x05"/>
|
|
|
|
|
<value caption="Pulse-width Capture" name="PWF" value="0x06"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Event Selection" name="TC45_EVSEL">
|
|
|
|
|
<value caption="No Event Source" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 0" name="CH0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="CH1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="CH2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="CH3" value="0x0B"/>
|
|
|
|
|
<value caption="Event Channel 4" name="CH4" value="0x0C"/>
|
|
|
|
|
<value caption="Event Channel 5" name="CH5" value="0x0D"/>
|
|
|
|
|
<value caption="Event Channel 6" name="CH6" value="0x0E"/>
|
|
|
|
|
<value caption="Event Channel 7" name="CH7" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel A Mode" name="TC45_CCAMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel B Mode" name="TC45_CCBMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel C Mode" name="TC45_CCCMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel D Mode" name="TC45_CCDMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel A Mode" name="TC45_LCCAMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel B Mode" name="TC45_LCCBMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel C Mode" name="TC45_LCCCMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel D Mode" name="TC45_LCCDMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture High Channel A Mode" name="TC45_HCCAMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture High Channel B Mode" name="TC45_HCCBMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture High Channel C Mode" name="TC45_HCCCMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture High Channel D Mode" name="TC45_HCCDMODE">
|
|
|
|
|
<value caption="Channel Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Output Compare enabled" name="COMP" value="0x01"/>
|
|
|
|
|
<value caption="Input Capture enabled" name="CAPT" value="0x02"/>
|
|
|
|
|
<value caption="Both Compare and Capture enabled" name="BOTHCC" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer Trigger Restart Interrupt Level" name="TC45_TRGINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Error Interrupt Level" name="TC45_ERRINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Overflow Interrupt Level" name="TC45_OVFINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel A Interrupt Level" name="TC45_CCAINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel B Interrupt Level" name="TC45_CCBINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel C Interrupt Level" name="TC45_CCCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Channel D Interrupt Level" name="TC45_CCDINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel A Interrupt Level" name="TC45_LCCAINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel B Interrupt Level" name="TC45_LCCBINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel C Interrupt Level" name="TC45_LCCCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Compare or Capture Low Channel D Interrupt Level" name="TC45_LCCDINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Timer/Counter Command" name="TC45_CMD">
|
|
|
|
|
<value caption="No Command" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Force Update" name="UPDATE" value="0x01"/>
|
|
|
|
|
<value caption="Force Restart" name="RESTART" value="0x02"/>
|
|
|
|
|
<value caption="Force Hard Reset" name="RESET" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="TC4">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="ERR" caption="Error Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="CCA" caption="Channel A Compare or Capture Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="CCB" caption="Channel B Compare or Capture Interrupt"/>
|
|
|
|
|
<interrupt index="4" name="CCC" caption="Channel C Compare or Capture Interrupt"/>
|
|
|
|
|
<interrupt index="5" name="CCD" caption="Channel D Compare or Capture Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
<interrupt-group name="TC5">
|
|
|
|
|
<interrupt index="0" name="OVF" caption="Overflow Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="ERR" caption="Error Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="CCA" caption="Channel A Compare or Capture Interrupt"/>
|
|
|
|
|
<interrupt index="3" name="CCB" caption="Channel B Compare or Capture Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FAULT" id="I3620" version="XMEGAE" caption="Fault Extension">
|
|
|
|
|
<register-group caption="Fault Extension" name="FAULT" size="8">
|
|
|
|
|
<register caption="Control A Register" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Ramp Mode Selection" mask="0xC0" name="RAMP" values="FAULT_RAMP"/>
|
|
|
|
|
<bitfield caption="Fault on Debug Break Detection" mask="0x20" name="FDDBD"/>
|
|
|
|
|
<bitfield caption="Port Control Mode" mask="0x10" name="PORTCTRL"/>
|
|
|
|
|
<bitfield caption="Fuse State " mask="0x08" name="FUSE"/>
|
|
|
|
|
<bitfield caption="Fault E Digital Filter Selection" mask="0x04" name="FILTERE"/>
|
|
|
|
|
<bitfield caption="Fault E Input selection" mask="0x03" name="SRCE" values="FAULT_SRCE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control B Register" name="CTRLB" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Fault A Software Mode" mask="0x80" name="SOFTA"/>
|
|
|
|
|
<bitfield caption="Fault A Halt Action" mask="0x60" name="HALTA" values="FAULT_HALTA"/>
|
|
|
|
|
<bitfield caption="Fault A Restart Action" mask="0x10" name="RESTARTA"/>
|
|
|
|
|
<bitfield caption="Fault A Keep Action" mask="0x08" name="KEEPA"/>
|
|
|
|
|
<bitfield caption="Fault A Source Selection" mask="0x03" name="SRCA" values="FAULT_SRCA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control C Register" name="CTRLC" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Fault A Capture" mask="0x20" name="CAPTA"/>
|
|
|
|
|
<bitfield caption="Fault A Digital Filter Selection" mask="0x04" name="FILTERA"/>
|
|
|
|
|
<bitfield caption="Fault A Blanking" mask="0x02" name="BLANKA"/>
|
|
|
|
|
<bitfield caption="Fault A Qualification" mask="0x01" name="QUALA"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control D Register" name="CTRLD" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="Fault B Software Mode" mask="0x80" name="SOFTB"/>
|
|
|
|
|
<bitfield caption="Fault B Halt Action" mask="0x60" name="HALTB" values="FAULT_HALTB"/>
|
|
|
|
|
<bitfield caption="Fault B Restart Action" mask="0x10" name="RESTARTB"/>
|
|
|
|
|
<bitfield caption="Fault B Keep Action" mask="0x08" name="KEEPB"/>
|
|
|
|
|
<bitfield caption="Fault B Source Selection" mask="0x03" name="SRCB" values="FAULT_SRCB"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control E Register" name="CTRLE" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Fault B Capture" mask="0x20" name="CAPTB"/>
|
|
|
|
|
<bitfield caption="Fault B Digital Filter Selection" mask="0x04" name="FILTERB"/>
|
|
|
|
|
<bitfield caption="Fault B Blanking" mask="0x02" name="BLANKB"/>
|
|
|
|
|
<bitfield caption="Fault B Qualification" mask="0x01" name="QUALB"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Fault B State" mask="0x80" name="STATEB"/>
|
|
|
|
|
<bitfield caption="Fault A State" mask="0x40" name="STATEA"/>
|
|
|
|
|
<bitfield caption="Fault E State" mask="0x20" name="STATEE"/>
|
|
|
|
|
<bitfield caption="Channel Index Flag" mask="0x08" name="IDX"/>
|
|
|
|
|
<bitfield caption="Fault B Flag" mask="0x04" name="FAULTBIN"/>
|
|
|
|
|
<bitfield caption="Fault A Flag" mask="0x02" name="FAULTAIN"/>
|
|
|
|
|
<bitfield caption="Fault E Flag" mask="0x01" name="FAULTEIN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G Clear" name="CTRLGCLR" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="State B Clear" mask="0x80" name="HALTBCLR"/>
|
|
|
|
|
<bitfield caption="State A Clear" mask="0x40" name="HALTACLR"/>
|
|
|
|
|
<bitfield caption="State E Clear" mask="0x20" name="STATEECLR"/>
|
|
|
|
|
<bitfield caption="Fault B Flag" mask="0x04" name="FAULTB"/>
|
|
|
|
|
<bitfield caption="Fault A Flag" mask="0x02" name="FAULTA"/>
|
|
|
|
|
<bitfield caption="Fault E Flag" mask="0x01" name="FAULTE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register G set" name="CTRLGSET" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Software Fault B" mask="0x80" name="FAULTBSW"/>
|
|
|
|
|
<bitfield caption="Software Fault A" mask="0x40" name="FAULTASW"/>
|
|
|
|
|
<bitfield caption="Software Fault E" mask="0x20" name="FAULTESW"/>
|
|
|
|
|
<bitfield caption="Channel index Command" mask="0x18" name="IDXCMD" values="FAULT_IDXCMD"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Ramp Mode Selection" name="FAULT_RAMP">
|
|
|
|
|
<value caption="Normal Mode" name="RAMP1" value="0x00"/>
|
|
|
|
|
<value caption="RAMP2 Mode" name="RAMP2" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Fault E Input Source Selection" name="FAULT_SRCE">
|
|
|
|
|
<value caption="Fault Protection Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel n" name="CHN" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel n+1" name="CHN1" value="0x02"/>
|
|
|
|
|
<value caption="Event Channel n+2" name="CHN2" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Fault A Halt Action Selection" name="FAULT_HALTA">
|
|
|
|
|
<value caption="Halt Action Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Hardware Halt Action" name="HW" value="0x01"/>
|
|
|
|
|
<value caption="Software Halt Action" name="SW" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Fault A Source Selection" name="FAULT_SRCA">
|
|
|
|
|
<value caption="Fault A Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel n" name="CHN" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel n+1" name="CHN1" value="0x02"/>
|
|
|
|
|
<value caption="Fault A linked to Fault B State from previous cycle" name="LINK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Fault B Halt Action Selection" name="FAULT_HALTB">
|
|
|
|
|
<value caption="Halt Action Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Hardware Halt Action" name="HW" value="0x01"/>
|
|
|
|
|
<value caption="Software Halt Action" name="SW" value="0x02"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Fault B Source Selection" name="FAULT_SRCB">
|
|
|
|
|
<value caption="Fault B disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel n" name="CHN" value="0x01"/>
|
|
|
|
|
<value caption="Event Channel n+1" name="CHN1" value="0x02"/>
|
|
|
|
|
<value caption="Fault B linked to Fault A State from previous cycle" name="LINK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Channel index Command" name="FAULT_IDXCMD">
|
|
|
|
|
<value caption="Command Disabled" name="DISABLE" value="0x00"/>
|
|
|
|
|
<value caption="Force Cycle B in Next Cycle" name="SET" value="0x01"/>
|
|
|
|
|
<value caption="Force Cycle A in Next Cycle" name="CLEAR" value="0x02"/>
|
|
|
|
|
<value caption="Hold Current Cycle Index in Next Cycle " name="HOLD" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="WEX" id="I3007" version="XMEGAE" caption="Waveform Extension">
|
|
|
|
|
<register-group caption="Waveform Extension" name="WEX" size="16">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Update Source Selection" mask="0x80" name="UPSEL"/>
|
|
|
|
|
<bitfield caption="Output Matrix" mask="0x70" name="OTMX" values="WEX_OTMX"/>
|
|
|
|
|
<bitfield caption="Dead-Time Insertion Generator 3 Enable" mask="0x08" name="DTI3EN"/>
|
|
|
|
|
<bitfield caption="Dead-Time Insertion Generator 2 Enable" mask="0x04" name="DTI2EN"/>
|
|
|
|
|
<bitfield caption="Dead-Time Insertion Generator 1 Enable" mask="0x02" name="DTI1EN"/>
|
|
|
|
|
<bitfield caption="Dead-Time Insertion Generator 0 Enable" mask="0x01" name="DTI0EN"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Dead-time Concurrent Write to Both Sides Register" name="DTBOTH" offset="0x01"
|
|
|
|
|
size="1"/>
|
|
|
|
|
<register caption="Dead-time Low Side Register" name="DTLS" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="Dead-time High Side Register" name="DTHS" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Status Clear Register" name="STATUSCLR" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Swap Buffer Valid " mask="0x04" name="SWAPBUF"/>
|
|
|
|
|
<bitfield caption="Pattern Generator Value Buffer Valid " mask="0x02" name="PGVBUFV"/>
|
|
|
|
|
<bitfield caption="Pattern Generator Overwrite Buffer Valid" mask="0x01" name="PGOBUFV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Set Register" name="STATUSSET" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Swap Buffer Valid " mask="0x04" name="SWAPBUF"/>
|
|
|
|
|
<bitfield caption="Pattern Generator Value Buffer Valid " mask="0x02" name="PGVBUFV"/>
|
|
|
|
|
<bitfield caption="Pattern Generator Overwrite Buffer Valid " mask="0x01" name="PGOBUFV"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Swap Register" name="SWAP" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Swap DTI output pair 3" mask="0x08" name="SWAP3"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 2" mask="0x04" name="SWAP2"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 1" mask="0x02" name="SWAP1"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 0" mask="0x01" name="SWAP0"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pattern Generation Override Register" name="PGO" offset="0x07" size="1"/>
|
|
|
|
|
<register caption="Pattern Generation Value Register" name="PGV" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Dead Time Low Side Buffer" name="SWAPBUF" offset="0x0A" size="1">
|
|
|
|
|
<bitfield caption="Swap DTI output pair 3 " mask="0x08" name="SWAP3BUF"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 2" mask="0x04" name="SWAP2BUF"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 1 " mask="0x02" name="SWAP1BUF"/>
|
|
|
|
|
<bitfield caption="Swap DTI output pair 0" mask="0x01" name="SWAP0BUF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Pattern Generation Overwrite Buffer Register" name="PGOBUF" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Pattern Generation Value Buffer Register" name="PGVBUF" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Output Override Disable Register " name="OUTOVDIS" offset="0x0F" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Output Matrix Mode" name="WEX_OTMX">
|
|
|
|
|
<value caption="Default Output Matrix Mode" name="DEFAULT" value="0x00"/>
|
|
|
|
|
<value caption="First Output matrix Mode" name="FIRST" value="0x01"/>
|
|
|
|
|
<value caption="Second Output matrix Mode" name="SECOND" value="0x02"/>
|
|
|
|
|
<value caption="Third Output matrix Mode" name="THIRD" value="0x03"/>
|
|
|
|
|
<value caption="Fourth Output matrix Mode" name="FOURTH" value="0x04"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="HIRES" id="I3620" version="XMEGAE" caption="High-Resolution Extension">
|
|
|
|
|
<register-group caption="High-Resolution Extension" name="HIRES" size="1">
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="High Resolution Plus" mask="0x0C" name="HRPLUS" values="HIRES_HRPLUS"/>
|
|
|
|
|
<bitfield caption="High Resolution Mode" mask="0x03" name="HREN" values="HIRES_HREN"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="High Resolution Plus Mode" name="HIRES_HRPLUS">
|
|
|
|
|
<value caption="No Hi-Res Plus" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Hi-Res Plus enabled on Timer 4" name="HRP4" value="0x01"/>
|
|
|
|
|
<value caption="Hi-Res Plus enabled on Timer 5" name="HRP5" value="0x02"/>
|
|
|
|
|
<value caption="Hi-Res Plus enabled on Timer 4 and 5" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="High Resolution Mode" name="HIRES_HREN">
|
|
|
|
|
<value caption="No Hi-Res" name="NONE" value="0x00"/>
|
|
|
|
|
<value caption="Hi-Res enabled on Timer 4" name="HRP4" value="0x01"/>
|
|
|
|
|
<value caption="Hi-Res enabled on Timer 5" name="HRP5" value="0x02"/>
|
|
|
|
|
<value caption="Hi-Res enabled on Timer 4 and 5" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="USART" id="I4000" version="XMEGAE" caption="Universal Asynchronous Receiver-Transmitter">
|
|
|
|
|
<register-group caption="Universal Synchronous/Asynchronous Receiver/Transmitter" name="USART" size="8">
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Receive Interrupt Flag" mask="0x80" name="RXCIF"/>
|
|
|
|
|
<bitfield caption="Transmit Interrupt Flag" mask="0x40" name="TXCIF"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Flag" mask="0x20" name="DREIF"/>
|
|
|
|
|
<bitfield caption="Frame Error" mask="0x10" name="FERR"/>
|
|
|
|
|
<bitfield caption="Buffer Overflow" mask="0x08" name="BUFOVF"/>
|
|
|
|
|
<bitfield caption="Parity Error" mask="0x04" name="PERR"/>
|
|
|
|
|
<bitfield caption="Receive Start Bit Interrupt Flag" mask="0x02" name="RXSIF"/>
|
|
|
|
|
<bitfield caption="Receive Bit 8" mask="0x01" name="RXB8"/>
|
|
|
|
|
<bitfield caption="Data Reception Flag" mask="0x01" name="DRIF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register A" name="CTRLA" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Receive Start Interrupt Enable" mask="0x80" name="RXSIE"/>
|
|
|
|
|
<bitfield caption="Data Reception Interrupt Enable" mask="0x40" name="DRIE"/>
|
|
|
|
|
<bitfield caption="Receive Interrupt Level" mask="0x30" name="RXCINTLVL" values="USART_RXCINTLVL"/>
|
|
|
|
|
<bitfield caption="Transmit Interrupt Level" mask="0x0C" name="TXCINTLVL" values="USART_TXCINTLVL"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Interrupt Level" mask="0x03" name="DREINTLVL"
|
|
|
|
|
values="USART_DREINTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x03" size="1">
|
|
|
|
|
<bitfield caption="One Wire Mode" mask="0x80" name="ONEWIRE"/>
|
|
|
|
|
<bitfield caption="Start Frame Detection Enable" mask="0x40" name="SFDEN"/>
|
|
|
|
|
<bitfield caption="Receiver Enable" mask="0x10" name="RXEN"/>
|
|
|
|
|
<bitfield caption="Transmitter Enable" mask="0x08" name="TXEN"/>
|
|
|
|
|
<bitfield caption="Double transmission speed" mask="0x04" name="CLK2X"/>
|
|
|
|
|
<bitfield caption="Multi-processor Communication Mode" mask="0x02" name="MPCM"/>
|
|
|
|
|
<bitfield caption="Transmit bit 8" mask="0x01" name="TXB8"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register C" name="CTRLC" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Communication Mode" mask="0xC0" name="CMODE" values="USART_CMODE"/>
|
|
|
|
|
<bitfield caption="Parity Mode" mask="0x30" name="PMODE" values="USART_PMODE"/>
|
|
|
|
|
<bitfield caption="Stop Bit Mode" mask="0x08" name="SBMODE"/>
|
|
|
|
|
<bitfield caption="Character Size" mask="0x07" name="CHSIZE" values="USART_CHSIZE"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Control Register D" name="CTRLD" offset="0x05" size="1">
|
|
|
|
|
<bitfield caption="Receive Interrupt Level" mask="0x30" name="DECTYPE" values="USART_DECTYPE"/>
|
|
|
|
|
<bitfield caption="Transmit Interrupt Level" mask="0x0C" name="LUTACT" values="USART_LUTACT"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Interrupt Level" mask="0x03" name="PECACT"
|
|
|
|
|
values="USART_PECACT"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register A" name="BAUDCTRLA" offset="0x06" size="1">
|
|
|
|
|
<bitfield caption="Baud Rate Selection Bits [7:0]" mask="0xFF" name="BSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Baud Rate Control Register B" name="BAUDCTRLB" offset="0x07" size="1">
|
|
|
|
|
<bitfield caption="Baud Rate Scale" mask="0xF0" name="BSCALE"/>
|
|
|
|
|
<bitfield caption="Baud Rate Selection bits[11:8]" mask="0x0F" name="BSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Receive Start Interrupt level" name="USART_RXSINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Receive Complete Interrupt level" name="USART_RXCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Transmit Complete Interrupt level" name="USART_TXCINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Data Register Empty Interrupt level" name="USART_DREINTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Character Size" name="USART_CHSIZE">
|
|
|
|
|
<value caption="Character size: 5 bit" name="5BIT" value="0x00"/>
|
|
|
|
|
<value caption="Character size: 6 bit" name="6BIT" value="0x01"/>
|
|
|
|
|
<value caption="Character size: 7 bit" name="7BIT" value="0x02"/>
|
|
|
|
|
<value caption="Character size: 8 bit" name="8BIT" value="0x03"/>
|
|
|
|
|
<value caption="Character size: 9 bit" name="9BIT" value="0x07"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Communication Mode" name="USART_CMODE">
|
|
|
|
|
<value caption="Asynchronous Mode" name="ASYNCHRONOUS" value="0x00"/>
|
|
|
|
|
<value caption="Synchronous Mode" name="SYNCHRONOUS" value="0x01"/>
|
|
|
|
|
<value caption="IrDA Mode" name="IRDA" value="0x02"/>
|
|
|
|
|
<value caption="Master SPI Mode" name="MSPI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Parity Mode" name="USART_PMODE">
|
|
|
|
|
<value caption="No Parity" name="DISABLED" value="0x00"/>
|
|
|
|
|
<value caption="Even Parity" name="EVEN" value="0x02"/>
|
|
|
|
|
<value caption="Odd Parity" name="ODD" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Encoding and Decoding Type" name="USART_DECTYPE">
|
|
|
|
|
<value caption="DATA Field Encoding" name="DATA" value="0x00"/>
|
|
|
|
|
<value caption="Start and Data Fields Encoding" name="SDATA" value="0x02"/>
|
|
|
|
|
<value caption="Start and Data Fields Encoding, with invertion in START field" name="NOTSDATA"
|
|
|
|
|
value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="XCL LUT Action" name="USART_LUTACT">
|
|
|
|
|
<value caption="Standard Frame Configuration" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Receiver Decoding Enabled" name="RX" value="0x01"/>
|
|
|
|
|
<value caption="Transmitter Encoding Enabled" name="TX" value="0x02"/>
|
|
|
|
|
<value caption="Both Encoding and Decoding Enabled" name="BOTH" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="XCL Peripheral Counter Action" name="USART_PECACT">
|
|
|
|
|
<value caption="Standard Mode" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Variable Data Lenght in Reception" name="PEC0" value="0x01"/>
|
|
|
|
|
<value caption="Variable Data Lenght in Transmission" name="PEC1" value="0x02"/>
|
|
|
|
|
<value caption="Variable Data Lenght in both Reception and Transmission" name="PERC01" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="USART">
|
|
|
|
|
<interrupt index="0" name="RXC" caption="Reception Complete Interrupt"/>
|
|
|
|
|
<interrupt index="1" name="DRE" caption="Data Register Empty Interrupt"/>
|
|
|
|
|
<interrupt index="2" name="TXC" caption="Transmission Complete Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SPI" id="I6090" version="XMEGAE" caption="Serial Peripheral Interface">
|
|
|
|
|
<register-group caption="Serial Peripheral Interface with Buffer Modes" name="SPI" size="5">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Enable Double Speed" mask="0x80" name="CLK2X"/>
|
|
|
|
|
<bitfield caption="Enable SPI Module" mask="0x40" name="ENABLE"/>
|
|
|
|
|
<bitfield caption="Data Order Setting" mask="0x20" name="DORD"/>
|
|
|
|
|
<bitfield caption="Master Operation Enable" mask="0x10" name="MASTER"/>
|
|
|
|
|
<bitfield caption="SPI Mode" mask="0x0C" name="MODE" values="SPI_MODE"/>
|
|
|
|
|
<bitfield caption="Prescaler" mask="0x03" name="PRESCALER" values="SPI_PRESCALER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Interrupt Control Register" name="INTCTRL" offset="0x01" size="1">
|
|
|
|
|
<bitfield caption="Receive Complete Interrupt Enable (In Buffer Modes Only)." mask="0x80"
|
|
|
|
|
name="RXCIE"/>
|
|
|
|
|
<bitfield caption="Transmit Complete Interrupt Enable (In Buffer Modes Only)." mask="0x40"
|
|
|
|
|
name="TXCIE"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Interrupt Enable (In Buffer Modes Only)." mask="0x20"
|
|
|
|
|
name="DREIE"/>
|
|
|
|
|
<bitfield caption="Slave Select Trigger Interrupt Enable (In Buffer Modes Only)." mask="0x10"
|
|
|
|
|
name="SSIE"/>
|
|
|
|
|
<bitfield caption="Interrupt level" mask="0x03" name="INTLVL" values="SPI_INTLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Status Register" name="STATUS" offset="0x02" size="1">
|
|
|
|
|
<bitfield caption="Interrupt Flag (In Standard Mode Only)." mask="0x80" name="IF"/>
|
|
|
|
|
<bitfield caption="Receive Complete Interrupt Flag (In Buffer Modes Only)." mask="0x80"
|
|
|
|
|
name="RXCIF"/>
|
|
|
|
|
<bitfield caption="Write Collision Flag (In Standard Mode Only)." mask="0x40" name="WRCOL"/>
|
|
|
|
|
<bitfield caption="Transmit Complete Interrupt Flag (In Buffer Modes Only)." mask="0x40"
|
|
|
|
|
name="TXCIF"/>
|
|
|
|
|
<bitfield caption="Data Register Empty Interrupt Flag (In Buffer Modes Only)." mask="0x20"
|
|
|
|
|
name="DREIF"/>
|
|
|
|
|
<bitfield caption="Slave Select Trigger Interrupt Flag (In Buffer Modes Only)." mask="0x10"
|
|
|
|
|
name="SSIF"/>
|
|
|
|
|
<bitfield caption="Buffer Overflow (In Buffer Modes Only)." mask="0x01" name="BUFOVF"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Data Register" name="DATA" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="Control Register B" name="CTRLB" offset="0x04" size="1">
|
|
|
|
|
<bitfield caption="Buffer Modes" mask="0xC0" name="BUFMODE" values="SPI_BUFMODE"/>
|
|
|
|
|
<bitfield caption="Slave Select Disable" mask="0x04" name="SSD"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="SPI Mode" name="SPI_MODE">
|
|
|
|
|
<value caption="SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling)."
|
|
|
|
|
name="0" value="0x00"/>
|
|
|
|
|
<value caption="SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling)."
|
|
|
|
|
name="1" value="0x01"/>
|
|
|
|
|
<value caption="SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising)."
|
|
|
|
|
name="2" value="0x02"/>
|
|
|
|
|
<value caption="SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising)."
|
|
|
|
|
name="3" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Prescaler setting" name="SPI_PRESCALER">
|
|
|
|
|
<value caption="If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4." name="DIV4" value="0x00"/>
|
|
|
|
|
<value caption="If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16." name="DIV16" value="0x01"/>
|
|
|
|
|
<value caption="If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64." name="DIV64" value="0x02"/>
|
|
|
|
|
<value caption="If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128." name="DIV128" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Interrupt level" name="SPI_INTLVL">
|
|
|
|
|
<value caption="Interrupt Disabled" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Low Level" name="LO" value="0x01"/>
|
|
|
|
|
<value caption="Medium Level" name="MED" value="0x02"/>
|
|
|
|
|
<value caption="High Level" name="HI" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Buffer Modes" name="SPI_BUFMODE">
|
|
|
|
|
<value caption="SPI Unbuffered Mode" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Buffer Mode 1 (with dummy byte)" name="BUFMODE1" value="0x02"/>
|
|
|
|
|
<value caption="Buffer Mode 2 (no dummy byte)" name="BUFMODE2" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<interrupt-group name="SPI">
|
|
|
|
|
<interrupt index="0" name="INT" caption="SPI Interrupt"/>
|
|
|
|
|
</interrupt-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="IRCOM" id="I6090" version="XMEGAAU" caption="IR Communication Module">
|
|
|
|
|
<register-group caption="IR Communication Module" name="IRCOM" size="3">
|
|
|
|
|
<register caption="Control Register" name="CTRL" offset="0x00" size="1">
|
|
|
|
|
<bitfield caption="Event Channel Select" mask="0x0F" name="EVSEL" values="IRDA_EVSEL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="IrDA Transmitter Pulse Length Control Register" name="TXPLCTRL" offset="0x01"
|
|
|
|
|
size="1"/>
|
|
|
|
|
<register caption="IrDA Receiver Pulse Length Control Register" name="RXPLCTRL" offset="0x02" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Event channel selection" name="IRDA_EVSEL">
|
|
|
|
|
<value caption="No Event Source" name="OFF" value="0x00"/>
|
|
|
|
|
<value caption="Event Channel 0" name="0" value="0x08"/>
|
|
|
|
|
<value caption="Event Channel 1" name="1" value="0x09"/>
|
|
|
|
|
<value caption="Event Channel 2" name="2" value="0x0A"/>
|
|
|
|
|
<value caption="Event Channel 3" name="3" value="0x0B"/>
|
|
|
|
|
<value caption="Event Channel 4" name="4" value="0x0C"/>
|
|
|
|
|
<value caption="Event Channel 5" name="5" value="0x0D"/>
|
|
|
|
|
<value caption="Event Channel 6" name="6" value="0x0E"/>
|
|
|
|
|
<value caption="Event Channel 7" name="7" value="0x0F"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="FUSE" id="I3620" version="XMEGAE" caption="Fuses and Lockbits">
|
|
|
|
|
<register-group caption="Lock Bits" name="NVM_LOCKBITS" size="1">
|
|
|
|
|
<register caption="Lock Bits" name="LOCKBITS" offset="0x00" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Boot Section" mask="0xC0" name="BLBB" values="FUSE_BLBB"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Section" mask="0x30" name="BLBA"
|
|
|
|
|
values="FUSE_BLBA"/>
|
|
|
|
|
<bitfield caption="Boot Lock Bits - Application Table" mask="0x0C" name="BLBAT"
|
|
|
|
|
values="FUSE_BLBAT"/>
|
|
|
|
|
<bitfield caption="Lock Bits" mask="0x03" name="LB" values="FUSE_LB"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<register-group caption="Fuses" name="NVM_FUSES" size="7">
|
|
|
|
|
<register caption="Watchdog Configuration" name="FUSEBYTE1" offset="0x01" size="1" initval="0x00">
|
|
|
|
|
<bitfield caption="Watchdog Window Timeout Period" mask="0xF0" name="WDWPER" values="WDWPER"/>
|
|
|
|
|
<bitfield caption="Watchdog Timeout Period" mask="0x0F" name="WDPER" values="WDPER"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Reset Configuration" name="FUSEBYTE2" offset="0x02" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Boot Loader Section Reset Vector" mask="0x40" name="BOOTRST" values="BOOTRST"/>
|
|
|
|
|
<bitfield caption="BOD Operation in Power-Down Mode" mask="0x03" name="BODPD" values="BODPD"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Start-up Configuration" name="FUSEBYTE4" offset="0x04" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="External Reset Disable" mask="0x10" name="RSTDISBL"/>
|
|
|
|
|
<bitfield caption="Start-up Time" mask="0x0C" name="STARTUPTIME" values="SUT"/>
|
|
|
|
|
<bitfield caption="Watchdog Timer Lock" mask="0x02" name="WDLOCK"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="EESAVE and BOD Level" name="FUSEBYTE5" offset="0x05" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="BOD Operation in Active Mode" mask="0x30" name="BODACT" values="BODACT"/>
|
|
|
|
|
<bitfield caption="Preserve EEPROM Through Chip Erase" mask="0x08" name="EESAVE"/>
|
|
|
|
|
<bitfield caption="Brownout Detection Voltage Level" mask="0x07" name="BODLEVEL" values="BODLVL"/>
|
|
|
|
|
</register>
|
|
|
|
|
<register caption="Fault State" name="FUSEBYTE6" offset="0x06" size="1" initval="0xFF">
|
|
|
|
|
<bitfield caption="Fault Dectection Action on TC5" mask="0x80" name="FDACT5"/>
|
|
|
|
|
<bitfield caption="Fault Dectection Action on TC4" mask="0x40" name="FDACT4"/>
|
|
|
|
|
<bitfield caption="Port Pin Value" mask="0x3F" name="VALUE"/>
|
|
|
|
|
</register>
|
|
|
|
|
</register-group>
|
|
|
|
|
<value-group caption="Boot lock bits - boot section" name="FUSE_BLBB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application section" name="FUSE_BLBA">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot lock bits - application table section" name="FUSE_BLBAT">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Read not allowed" name="RLOCK" value="0x01"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Lock bits" name="FUSE_LB">
|
|
|
|
|
<value caption="Read and write not allowed" name="RWLOCK" value="0x00"/>
|
|
|
|
|
<value caption="Write not allowed" name="WLOCK" value="0x02"/>
|
|
|
|
|
<value caption="No locks" name="NOLOCK" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Boot Loader Section Reset Vector" name="BOOTRST">
|
|
|
|
|
<value caption="Boot Loader Reset" name="BOOTLDR" value="0x00"/>
|
|
|
|
|
<value caption="Application Reset" name="APPLICATION" value="0x01"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="BOD operation" name="BODPD">
|
|
|
|
|
<value caption="BOD enabled in sampled mode" name="SAMPLED" value="0x01"/>
|
|
|
|
|
<value caption="BOD enabled continuously" name="CONTINUOUS" value="0x02"/>
|
|
|
|
|
<value caption="BOD Disabled" name="DISABLED" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="BOD operation" name="BODACT">
|
|
|
|
|
<value caption="BOD enabled in sampled mode" name="SAMPLED" value="0x01"/>
|
|
|
|
|
<value caption="BOD enabled continuously" name="CONTINUOUS" value="0x02"/>
|
|
|
|
|
<value caption="BOD Disabled" name="DISABLED" value="0x03"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Watchdog (Window) Timeout Period" name="WDWPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.125s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.25s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.5s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Watchdog (Window) Timeout Period" name="WDPER">
|
|
|
|
|
<value caption="8 cycles (8ms @ 3.3V)" name="8CLK" value="0x00"/>
|
|
|
|
|
<value caption="16 cycles (16ms @ 3.3V)" name="16CLK" value="0x01"/>
|
|
|
|
|
<value caption="32 cycles (32ms @ 3.3V)" name="32CLK" value="0x02"/>
|
|
|
|
|
<value caption="64 cycles (64ms @ 3.3V)" name="64CLK" value="0x03"/>
|
|
|
|
|
<value caption="128 cycles (0.125s @ 3.3V)" name="128CLK" value="0x04"/>
|
|
|
|
|
<value caption="256 cycles (0.25s @ 3.3V)" name="256CLK" value="0x05"/>
|
|
|
|
|
<value caption="512 cycles (0.5s @ 3.3V)" name="512CLK" value="0x06"/>
|
|
|
|
|
<value caption="1K cycles (1s @ 3.3V)" name="1KCLK" value="0x07"/>
|
|
|
|
|
<value caption="2K cycles (2s @ 3.3V)" name="2KCLK" value="0x08"/>
|
|
|
|
|
<value caption="4K cycles (4s @ 3.3V)" name="4KCLK" value="0x09"/>
|
|
|
|
|
<value caption="8K cycles (8s @ 3.3V)" name="8KCLK" value="0x0A"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Start-up Time" name="SUT">
|
|
|
|
|
<value caption="0 ms" name="0MS" value="0x03"/>
|
|
|
|
|
<value caption="4 ms" name="4MS" value="0x01"/>
|
|
|
|
|
<value caption="64 ms" name="64MS" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
<value-group caption="Brownout Detection Voltage Level" name="BODLVL">
|
|
|
|
|
<value caption="1.6 V" name="1V6" value="0x07"/>
|
|
|
|
|
<value caption="1.8 V" name="1V8" value="0x06"/>
|
|
|
|
|
<value caption="2.0 V" name="2V0" value="0x05"/>
|
|
|
|
|
<value caption="2.2 V" name="2V2" value="0x04"/>
|
|
|
|
|
<value caption="2.4 V" name="2V4" value="0x03"/>
|
|
|
|
|
<value caption="2.6 V" name="2V6" value="0x02"/>
|
|
|
|
|
<value caption="2.8 V" name="2V8" value="0x01"/>
|
|
|
|
|
<value caption="3.0 V" name="3V0" value="0x00"/>
|
|
|
|
|
</value-group>
|
|
|
|
|
</module>
|
|
|
|
|
<module name="SIGROW" id="I3620" version="XMEGAE" caption="Signature Row">
|
|
|
|
|
<register-group caption="Production Signatures" name="NVM_PROD_SIGNATURES" size="64">
|
|
|
|
|
<register caption="RCOSC 8MHz Calibration Value" name="RCOSC8M" offset="0x00" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32.768 kHz Calibration Value" name="RCOSC32K" offset="0x02" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32 MHz Calibration Value B" name="RCOSC32M" offset="0x03" size="1"/>
|
|
|
|
|
<register caption="RCOSC 32 MHz Calibration Value A" name="RCOSC32MA" offset="0x04" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 0, ASCII" name="LOTNUM0" offset="0x08" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 1, ASCII" name="LOTNUM1" offset="0x09" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 2, ASCII" name="LOTNUM2" offset="0x0A" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 3, ASCII" name="LOTNUM3" offset="0x0B" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 4, ASCII" name="LOTNUM4" offset="0x0C" size="1"/>
|
|
|
|
|
<register caption="Lot Number Byte 5, ASCII" name="LOTNUM5" offset="0x0D" size="1"/>
|
|
|
|
|
<register caption="Wafer Number" name="WAFNUM" offset="0x10" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate X Byte 0" name="COORDX0" offset="0x12" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate X Byte 1" name="COORDX1" offset="0x13" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate Y Byte 0" name="COORDY0" offset="0x14" size="1"/>
|
|
|
|
|
<register caption="Wafer Coordinate Y Byte 1" name="COORDY1" offset="0x15" size="1"/>
|
|
|
|
|
<register caption="Temperature corresponds to TEMPSENSE3/2" name="ROOMTEMP" offset="0x1E" size="1"/>
|
|
|
|
|
<register caption="Temperature corresponds to TEMPSENSE1/0" name="HOTTEMP" offset="0x1F" size="1"/>
|
|
|
|
|
<register caption="ADCA Calibration Byte 0" name="ADCACAL0" offset="0x20" size="1"/>
|
|
|
|
|
<register caption="ADCA Calibration Byte 1" name="ADCACAL1" offset="0x21" size="1"/>
|
|
|
|
|
<register caption="ACA Current Calibration Byte" name="ACACURRCAL" offset="0x28" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 2" name="TEMPSENSE2" offset="0x2C" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 3" name="TEMPSENSE3" offset="0x2D" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 0" name="TEMPSENSE0" offset="0x2E" size="1"/>
|
|
|
|
|
<register caption="Temperature Sensor Calibration Byte 1" name="TEMPSENSE1" offset="0x2F" size="1"/>
|
|
|
|
|
<register caption="DACA0 Calibration Byte 0" name="DACA0OFFCAL" offset="0x30" size="1"/>
|
|
|
|
|
<register caption="DACA0 Calibration Byte 1" name="DACA0GAINCAL" offset="0x31" size="1"/>
|
|
|
|
|
<register caption="DACA1 Calibration Byte 0" name="DACA1OFFCAL" offset="0x34" size="1"/>
|
|
|
|
|
<register caption="DACA1 Calibration Byte 1" name="DACA1GAINCAL" offset="0x35" size="1"/>
|
|
|
|
|
</register-group>
|
|
|
|
|
</module>
|
|
|
|
|
</modules>
|
|
|
|
|
<pinouts>
|
|
|
|
|
<pinout name="QFP_QFN_32">
|
|
|
|
|
<pin pad="GND" position="1"/>
|
|
|
|
|
<pin pad="PA4" position="2"/>
|
|
|
|
|
<pin pad="PA3" position="3"/>
|
|
|
|
|
<pin pad="PA2" position="4"/>
|
|
|
|
|
<pin pad="PA1" position="5"/>
|
|
|
|
|
<pin pad="PA0" position="6"/>
|
|
|
|
|
<pin pad="PDI" position="7"/>
|
|
|
|
|
<pin pad="RESET" position="8"/>
|
|
|
|
|
<pin pad="PC7" position="9"/>
|
|
|
|
|
<pin pad="PC6" position="10"/>
|
|
|
|
|
<pin pad="PC5" position="11"/>
|
|
|
|
|
<pin pad="PC4" position="12"/>
|
|
|
|
|
<pin pad="PC3" position="13"/>
|
|
|
|
|
<pin pad="PC2" position="14"/>
|
|
|
|
|
<pin pad="PC1" position="15"/>
|
|
|
|
|
<pin pad="PC0" position="16"/>
|
|
|
|
|
<pin pad="VCC" position="17"/>
|
|
|
|
|
<pin pad="GND" position="18"/>
|
|
|
|
|
<pin pad="PR1" position="19"/>
|
|
|
|
|
<pin pad="PR0" position="20"/>
|
|
|
|
|
<pin pad="PD7" position="21"/>
|
|
|
|
|
<pin pad="PD6" position="22"/>
|
|
|
|
|
<pin pad="PD5" position="23"/>
|
|
|
|
|
<pin pad="PD4" position="24"/>
|
|
|
|
|
<pin pad="PD3" position="25"/>
|
|
|
|
|
<pin pad="PD2" position="26"/>
|
|
|
|
|
<pin pad="PD1" position="27"/>
|
|
|
|
|
<pin pad="PD0" position="28"/>
|
|
|
|
|
<pin pad="PA7" position="29"/>
|
|
|
|
|
<pin pad="PA6" position="30"/>
|
|
|
|
|
<pin pad="PA5" position="31"/>
|
|
|
|
|
<pin pad="AVCC" position="32"/>
|
|
|
|
|
</pinout>
|
|
|
|
|
</pinouts>
|
2021-05-31 01:01:14 +01:00
|
|
|
</target-description-file>
|
